JP2020123382A - Control program - Google Patents

Abstract

To provide a control program for integrally controlling multiple CPUs controlled by different information processing devices.SOLUTION: A control program (hypervisor) makes a first information processing device 200 refer to management tables 204a, 204b associating virtual addresses specifying storage areas in a virtual memory space managed by an OS running on the first information processing device and physical addresses specifying storage areas in a real memory space of a second information processing device connected via a general-purpose network, and send a processing instruction to the second information processing device.SELECTED DRAWING: Figure 2

Description

The present invention relates to an information processing device, a program, and a recording medium having a function of operating a virtual machine across a plurality of different hypervisors.

In recent years, virtualization technology of computer architecture has been attracting attention in various fields. The virtualization technology is to abstract computer resources and is a technology for handling computer hardware as a virtual one. A virtual machine (Virtual Machine: VM) is known as one of the virtualization technologies for computer architecture.

A virtual machine is software that emulates the behavior of a computer or the emulated virtual computer itself. By introducing the concept of a virtual machine, it is possible to operate a plurality of OSs (operating systems) on a single computer. When operating a plurality of OSs on one computer, there is a control program for controlling those OSs. This is the hypervisor.

By executing the hypervisor on the server, it is possible to operate a plurality of virtual machines (that is, a plurality of kernels). This makes it possible to operate different OSs (called guest OSs) on a single server. Then, it is possible to provide the user with various interfaces depending on each OS.

By the way, conventionally, the hypervisor operates for each server and cannot cooperate with other hypervisors operating in other servers. For example, as shown in FIG. 14, it is assumed that a plurality of OSs 12 to 14 are operating under the control of the hypervisor 11 that operates on a certain server. At this time, each of the OSs 12 to 14 is actually processed by a CPU (Central Processing Unit) (not shown) in the hypervisor 11, and can access only a memory (not shown) in the hypervisor 11. That is, the hypervisor 11 can use only the resources existing in the server in which it operates.

Similarly, it is assumed that another OS 15 is operating under the control of another hypervisor 22 that operates on another server. As described above, since the resources cannot be shared between the hypervisors, the different hypervisors 11 and 22 can only control the OSs 12 to 15 independently, and one OS can be extended across the hypervisors. It was not possible to operate (virtual machine).

As a result, when it is necessary to improve server performance or to secure redundancy to deal with server trouble, the only effective measure is to increase the parallelism of the server and deal with it (scale out). However, there is a problem that the software development cost and the operation cost increase.

In order to deal with such a problem, in recent years, as a parallel processing technique of a computer, a technique of sharing a memory between physically separated CPUs has been developed. For example, in Patent Document 1, a hypervisor detects a layout relationship among a local memory, a remote memory, and a CPU, and a remote memory is viewed from a CPU assigned to a virtual machine. A technique for moving necessary data to a memory serving as a local memory is described.

Further, Patent Document 2 describes a process of performing address conversion using a memory table in a blade server and accessing a memory on another blade. That is, a technique for causing a blade server to function as an SMP (Symmetric Multiple Processor) server is described.

JP, 2011-238278, A JP2012-113604A

However, neither of the techniques described in Patent Documents 1 and 2 integrates and controls virtual machines under the control of different hypervisors, but simply distributes them to CPUs under the control of different hypervisors. It is what causes processing. Therefore, although the processing load on each CPU can be reduced, it is necessary to perform communication for synchronizing the processing results with each other, and the overhead resulting from the communication processing results in a factor that hinders the processing efficiency of the entire system. It was also accompanied.

In addition, when the CPU performs distributed processing, for example, even when one additional CPU is newly required to operate a certain virtual machine, a server equipped with 16 CPUs as an expansion unit In some cases, such as the need to prepare separately, it becomes necessary to procure extra hardware resources in excess of the required resources.

The present invention was created to overcome such obstacles, and an information processing device, a program, and a memory that enable integrated control of a plurality of virtual machines under the control of different hypervisors. It provides a medium.

An information processing apparatus according to an embodiment of the present invention includes an address of a memory managed by a first hypervisor, an address of a memory managed by a second hypervisor connected to the first hypervisor, and the second hypervisor. An address management table for recording an identifier for identifying a visor, and an issuing unit for referring to the address management table and issuing command and control information to the second hypervisor from the first hypervisor. The control information is information indicating the state of the logical processor operating in the second hypervisor.

An information processing apparatus according to an embodiment of the present invention includes an address of a virtual memory space managed by a first hypervisor, an identifier for identifying a second hypervisor different from the first hypervisor, and the second hypervisor. An address management table that stores the addresses of the memories managed by the hypervisor in association with each other, and a control information storage that stores control information indicating the state of the logical processor operating in the first hypervisor or the second hypervisor. The first hypervisor can send and receive the control information to and from the second hypervisor, and refers to the address management table to refer to the address of the virtual memory space. The address of the memory managed by the second hypervisor, which is associated with the.

The control information may be at least one of a register value indicating the state of the logical processor, a program counter value, and a pointer to the memory.

The first hypervisor and the second hypervisor may be connected by a general-purpose network in which a destination can be designated by an identifier.

The first hypervisor has the second hypervisor if the processing target data does not exist in the memory managed by itself and the processing target data exists in the memory managed by the second hypervisor. The control information may be transmitted to the visor.

The control information is stored in the first hypervisor and the second hypervisor according to the usage status of the resource managed by the first hypervisor or the usage status of the resource managed by the second hypervisor. It may be transmitted and received between. In particular, it is preferable that the control information is transmitted to the hypervisor that manages the resource having the surplus usage status.

It is preferable to transmit and receive data related to the control information (for example, data that is frequently referred to such as data cached by the logical processor) together with the transmission and reception of the control information.

According to the present invention, a plurality of CPUs under the control of different hypervisors can be integrated and controlled, and higher processing performance can be realized.

In addition, it is possible to improve the economical efficiency of having to procure extra resources required for desired processing and perform distributed processing, and to achieve higher utilization efficiency of hardware resources.

It is a block diagram which shows the information processing system which concerns on 1st Embodiment of this invention. It is a block diagram showing an information processor concerning a 1st embodiment of the present invention. It is a conceptual diagram which shows the principle in the information processing system of 1st Embodiment of this invention. It is a figure explaining the role of the control information mounted in the information processing system which concerns on 1st Embodiment of this invention. It is a figure explaining the procedure of establishing the connection in the information processing system which concerns on 1st Embodiment of this invention. It is a figure explaining the role of the address management table mounted in the information processing system which concerns on 1st Embodiment of this invention. It is a figure which shows the comparison of the information processing system which concerns on 1st Embodiment of this invention, and the conventional information processing system. It is a figure which shows the comparison of the information processing system which concerns on 1st Embodiment of this invention, and the conventional information processing system. It is a block diagram which shows the information processing system which concerns on 2nd Embodiment of this invention. It is a block diagram which shows the information processing system which concerns on 3rd Embodiment of this invention. It is a block diagram which shows the information processing system which concerns on 4th Embodiment of this invention. It is a block diagram which shows the information processing system which concerns on 5th Embodiment of this invention. It is a figure which shows the structure of the address management table mounted in the information processing system which concerns on 6th Embodiment of this invention. It is a block diagram which shows the conventional information processing system.

Hereinafter, a mobile terminal according to an embodiment of the present invention will be described in detail with reference to the drawings. The embodiments described below are examples of the embodiments of the present invention, and the present invention is not limited to these embodiments. Note that in the drawings referred to in this embodiment, the same portions or portions having similar functions are denoted by the same reference numerals or similar reference numerals (reference numerals having only A or B after the number), and the repetition thereof. May be omitted. In addition, the dimensional ratios in the drawings may differ from the actual ratios for convenience of description, or some of the configurations may be omitted from the drawings.

(First embodiment)
<System configuration>
FIG. 1 is a configuration diagram showing an information processing system 100 according to the first embodiment of the present invention. In FIG. 1, reference numeral 101 denotes a general-purpose network, to which the information processing apparatuses 102 to 107 are connected. Here, the general-purpose network refers to a network whose destination can be designated by using an identifier, such as the Internet, a LAN (Local Area Network), and a WAN (Wide Area Network).

The information processing apparatuses 102 to 107 can communicate with each other via the network 101 according to a predetermined protocol. Although the protocol differs depending on the general-purpose network, in the information processing system according to the first embodiment, it is not necessary for the information processing apparatuses 102 to 107 to be connected by the same general-purpose network. The general-purpose network connecting the device 105 and the general-purpose network connecting the information processing device 105 and the information processing device 106 may be different.

FIG. 2 is a block diagram showing the information processing device 200 according to the first embodiment of the present invention. The information processing devices 102 to 107 in FIG. 1 all have the same configuration as the information processing device 200.

In FIG. 2, 201 is a multi-core processor, which is provided with two CPU cores 202a and 202b. Each of the CPU cores 202a and 202b has a memory management unit (MMU) 203a and 203b built therein. Although a multi-core processor is illustrated in FIG. 2, it may be a single-core processor or a multi-processor provided with a plurality of processors.

The memory management units 203a and 203b hold address management tables 204a and 204b, respectively. The address management table associates an address designating a storage area of a virtual memory space (hereinafter referred to as “virtual address”) with an address designating a storage area of memory as a hardware resource (hereinafter referred to as “physical address”). It is a table for. The information processing system of the first embodiment uses a table different from the conventional address management table in that an identifier (a network address such as a MAC address) that specifies another information processing device is stored together with the physical address. Details will be described later.

Reference numeral 205 denotes a bus, which is a communication path that connects the multi-core processor 201 and each element described later. A RAM (Random Access Memory) 206 has a work area 207 and a system memory area 208 used by the multi-core processor 201. The information processing apparatus 200 according to the first embodiment holds, in the system memory area 208, control information 209 indicating the state (status) of the logical processor operating on the hypervisor. That is, the system memory area 208 corresponds to the “control information storage section” of the present invention. The control information 209 exists as many as the number of logical processors operating on the hypervisor.

As such control information 209, VMCS (Virtual Machine Control Structure) used in the virtualization support function of Intel Corporation and VMCB (Virtual Machine Control Block) used in the virtualization support function of AMD are known. Any control information may be used as long as it is information indicating the state of the logical processor (for example, at least one of a register value indicating the state of the logical processor, a program counter value, and a pointer to the memory). The operation using the control information 209 will be described later.

In FIG. 2, reference numeral 210 denotes a ROM (Read Only Memory), which stores various programs such as BIOS. An input/output unit (I/O unit) 211 inputs and outputs various data. A communication unit 212 communicates with another information processing device via the general-purpose network 101 in FIG. The communication system may be a wireless system or a wired system, and may have a mechanism for short-range wireless communication. A storage 213 functions as a database, and can use a large-capacity storage medium such as a hard disk. Of course, another recording medium may be used, or data may be held using cloud computing without having a unique storage.

<System principle>
FIG. 3 is a conceptual diagram showing the principle of the information processing system of the first embodiment. Reference numerals 301a to 301f are hypervisors that are executed by the control unit (specifically, a multi-core processor) of the information processing device. That is, the hypervisor is executed in each of the information processing apparatuses illustrated in FIGS. 1 and 2 to construct an information processing system in which a plurality of hypervisors 301a to 301f are connected via a general-purpose network.

Reference numerals 302a to 302i are virtual machines (herein referred to as OS) that operate on the hypervisor. A major difference from the conventional example shown in FIG. 14 is that in the information processing system of the first embodiment, a virtual machine operates across hypervisors. For example, in FIG. 3, the OS 302c operates across four hypervisors 301a to 301d, and each hypervisor cooperates to operate one virtual machine.

As described above, in the information processing system according to the first embodiment, the OSs 302a to 302i operate seamlessly among the hypervisors 301a to 301f, and each hypervisor has hardware resources such as a CPU core and a memory (hardware resources). , Or simply resources). That is, an information processing system is constructed in which the hypervisors 301a to 301f cooperate with each other to share hardware resources with each other and enable dynamic scale-up of virtual machines.

Next, a specific mounting method for constructing such an information processing system will be described. FIG. 4 is a diagram for explaining the role of control information implemented in the information processing device that constitutes the information processing system according to the first embodiment. Here, it is shown that a certain logical processor transits between hypervisors.

In FIG. 4, 401a and 401b are hypervisors, respectively. The hypervisors 401a and 401b have memories 402a and 402b, respectively, and hold various data. The memory 402a is a hardware resource included in the information processing apparatus that executes the hypervisor 401a, and the memory 402b is a hardware resource included in the information processing apparatus that executes the hypervisor 401b.

In the hypervisor 401a, three logical processors 403a to 403c are currently operating, and one logical processor is being newly added. In the hypervisor 401b, two logical processors 403d and 403e are currently operating. Reference numeral 403f indicates a logical processor that was operating before the time t in FIG.

Each of the logical processors 403a to 403e holds control information 404a to 404e in the system memory area. Then, the control information 404f indicating the state of the logical processor 403f that was operating before the time t from the time of FIG. 4 is in the transition process from the hypervisor 401b to the hypervisor 401a, as shown in FIG. As described above, the control information 404f is transmitted via the general-purpose network. Then, in the hypervisor 401a, the logical processor 403f can be restarted based on the received control information 404f.

As described above, in the information processing system 100 of the first embodiment, the control information 404 is transmitted/received across the physical barriers between the hypervisors, so that the logical processor 403 operates without depending on the hypervisors. As a result, the virtual machine (OS) 405 can be operated across the hypervisors 401a and 401b.

Regarding which CPU of the hypervisor 401a processes the control information 404f, it is desirable to arbitrate between the hypervisors 401a and 401b in advance before transmitting the control information 404f. For example, the CPU of a hypervisor with insufficient resources may broadcast a request command for searching for a hypervisor with insufficient resources on the network, or may send it to a server that manages resource usage. There may be a process of obtaining the destination of the control information.

When the destination of the control information is determined, a command for requesting permission to use the resource may be transmitted to the hypervisor for preconfirmation. Then, when the arbitration is completed, the control information is transmitted to the hypervisor that has permitted the use of the resource, so that the resource of the hypervisor that has received the control information can be used. Such arbitration is performed by the CPU under the control of each hypervisor, and the CPU in this case corresponds to the “issuing unit” of the present invention.

For transmission/reception of control information via a general-purpose network, an appropriate protocol may be selected according to the network used. For example, FIG. 5 shows a case where an IP network is used as a general-purpose network and TCP/IP is used as a protocol.

As shown in FIG. 5, in the TCP protocol, the connection between the hypervisor 401a and the hypervisor 401b is established by the "3-way handshake". After that, the control information 404f and the data 406 are transmitted from the hypervisor 401b to the hypervisor 401a. After that, the control information 501 and the data 502 may be transmitted from the hypervisor 401a to the hypervisor 401b.

As described above, when transitioning the logical processor 403 from the hypervisor 401b to the hypervisor 401a, the data cached in the logical processor (for example, the data stored in the L1 to L3 caches of the logical processor) and the logical processor are It is preferable that the data 406 that is frequently referred to, such as stack data of a process in which the CPU that was executing the process is in charge, also transit along with the control information 404. As a result, even if the logical processor 403 transits between hypervisors, the data 406 that is frequently referred to also transits together, so that it is possible to continuously execute processing. The data 406 with high reference frequency is data related to the logical processor that refers to it, in other words, data related to control information indicating the state of the logical processor.

The address management table may be referred to in order to transmit the data 406 that is frequently referred to. For example, the hypervisor 401b can identify the data required for transmission by referring to its own address management table, read it from the memory under its control, and transmit it.

Further, as shown in FIG. 4, when the logical processor 403f that was processing in the hypervisor 401b transits to the hypervisor 401a, most of the data that was processed before the transition is stored in the memory 402b. There is. Therefore, if the processing is continued after the transition to the hypervisor 401a, it becomes necessary to refer to the memory 402b.

Therefore, in the information processing system 100 of the first embodiment, a specific means for allowing each hypervisor to access a memory under the control of another hypervisor via a general-purpose network is implemented. FIG. 6 is a diagram illustrating the role of the address management table implemented in the information processing device that constitutes the information processing system according to the first embodiment.

FIG. 6 shows the state after the transition of the logical processor 403f described with reference to FIG. An address management table 601 is the same as the address management tables 204a and 204b shown in FIG. The address management table 601 associates the virtual address that specifies the storage area of the virtual memory space managed by the OS 405 with the physical address that specifies the storage area of the actual memory space (memory space configured by the memories 402a and 402b). Table.

The physical address of the address management table 601 includes two types of physical addresses. The first physical address specifies the physical address of the memory 402a provided in the information processing device (hypervisor 401a) in which the address management table 601 is stored (“55”, “56”, “57” in FIG. 6). The second physical address designates a physical address of the memory 402b provided in another information processing device (hypervisor 401b) (“identifier+81”, “identifier+83”, etc. in FIG. 6). ).

Here, the second physical address stores not only the physical address but also an identifier (network address) for designating another information processing device on the network. In the first embodiment, it is expressed as “identifier+81”, but not limited to this, any form may be used as long as it is a combination of an identifier and a physical address. As the identifier, an identifier corresponding to the protocol of the general-purpose network connecting the hypervisors may be used. For example, a "MAC address" or "IP address" can be used.

In order to reduce the overhead in memory reference between hypervisors via the general-purpose network as shown in FIG. 6, it is desirable to use a general-purpose network with low latency and wide bandwidth. For example, "infiniBand", "Converged Enhanced Ethernet (registered trademark)", and "Serial RapidIO" can be used. However, it is possible to select a general-purpose network in the right place in accordance with the environment to be used, budget, etc. For example, when focusing on low cost rather than low latency, use "IP network" etc. There are no particular restrictions on the general-purpose network that can be used.

As described above, the information processing apparatus 200 that constructs the information processing system 100 according to the first embodiment can transition the logical processors between the hypervisors by transmitting and receiving the control information of each logical processor between the hypervisors. , One virtual machine (OS) can be operated across hypervisors.

Furthermore, by providing the CPU under the control of each hypervisor with the address management table shown in FIG. 6, it is possible to refer to memory between different hypervisors via a general-purpose network, and to physically separate the hypervisors. It is possible to operate virtual machines across hypervisors without being aware of the above. As a result, a plurality of CPUs under the control of different hypervisors can be integrated and controlled, and higher processing performance can be realized.

For example, conventionally, in order to improve the performance of an application, it has been necessary to adopt a scale-out type approach as shown in FIG. That is, when the plurality of hypervisors 701a to 701d operate the virtual machines (OS) 702a to 702d independently to improve the performance of the application, the number of the virtual machines, that is, the number of hypervisors is increased. I have dealt with it.

However, in this case, for example, the virtual machine 701a functions as a command tower (host) and the virtual machines 702a to 702d function as processing nodes (slave) to perform application processing. It was necessary to perform requests and replies, data synchronization, processing timing adjustments, etc., and there was a problem that a large number of man-hours and high technical skills were required for development.

On the other hand, in the information processing system 100 of the first embodiment, as shown in FIG. 7B, a scale-up type approach in which the virtual machine 702a is operated across the hypervisors 701a to 701d can be adopted. .. Therefore, it is possible to easily improve the application performance without paying attention to the overhead associated with network communication, and only by paying attention to only multithreading when developing a program.

In addition, the resources of each hypervisor can be efficiently used by transitioning the logical processor to a hypervisor having sufficient resources (for example, CPU cores and memories). That is, by dynamically changing the logical processors (changing the control information) according to the usage status of the resources of each hypervisor, the information processing system can be efficiently used.

For example, as shown in FIG. 7A, it is assumed that the virtual machine (OS1) 702a is operating in the hypervisor 701a and the CPU core 703a is insufficient. On the other hand, it is assumed that the virtual machine (OS2) 702b is operating in the hypervisor 701b and one of the CPU cores 703b is left over.

In this case, as shown in FIG. 7B, by extending the virtual machine 702a operating on the hypervisor 701a to the hypervisor 701b, the surplus CPU core of the hypervisor 701b is allocated to the virtual machine 702a. Is possible. Therefore, it is possible to improve the economical efficiency that the resources required for the desired processing are additionally procured and the distributed processing is performed, and it is possible to realize higher utilization efficiency of the hardware resources.

In addition, it is assumed that the virtual machine (OS1) 702a is operating in the hypervisor 701a and the memory (not shown) in the information processing device in which the hypervisor 701a operates is insufficient. On the other hand, it is assumed that there is a free area in the memory in the information processing device in which the hypervisor 701b operates and there is a free capacity.

In this case, by expanding the virtual machine 702a operating on the hypervisor 701a to the hypervisor 701b, it becomes possible to allocate an empty area of the memory managed by the hypervisor 701b to the virtual machine 702a.

(Second embodiment)
An information processing system 900 according to the second embodiment of the present invention will be described with reference to FIG. The information processing system 900 according to the second embodiment has a function added to the information processing system 100 according to the first embodiment, in which the performance of the CPU to be used is hierarchical within one virtual machine.

Conventionally, only one CPU of the same performance can be used in one virtual machine, and a virtual machine having an appropriate processing capacity is operated for high-level processing, or a backup virtual machine is operated. , It was necessary to decide the processing level (processing amount) for each virtual machine. Therefore, it has been difficult to flexibly cope with the situation in which the required processing dynamically changes.

However, in the information processing system 900 according to the second embodiment, the advantage that the virtual machine 903 can be operated across a plurality of different hypervisors is utilized, and the CPU performance to be used depends on the required processing level. It is characterized by a change that dynamically changes the allocation.

In FIG. 9, a hypervisor 901a operates with an information processing apparatus equipped with a CPU having a first performance (hereinafter referred to as “high-performance CPU”) 902a, and a hypervisor 901b has a CPU having a second performance. The hypervisor 901c operates as an information processing device having a 902b (hereinafter referred to as "medium performance CPU"), and the hypervisor 901c is an information processing device having a CPU 902c having a third performance (hereinafter referred to as "low performance CPU") Operate. Here, the first performance is the highest, followed by the second performance, the third performance, and so on.

The high-performance CPU does not mean absolute performance, but is a relative comparison of the respective CPUs. That is, as long as the relationship of the first performance>the second performance>the third performance is satisfied, the CPU may have any performance.

Therefore, the hypervisor 901a is equipped with the high-performance CPU 902a, so that it is possible to perform a relatively higher level of processing than the other hypervisors 901b and 901c. On the contrary, since the hypervisor 901a is equipped with the low-performance CPU 902c, the hypervisor 901a can perform only a relatively lower level of processing than the other hypervisors 901a and 901b.

However, even when the low-performance CPU 902c is used, the processing capacity becomes high if the number of allocations is large. Therefore, even if the high-performance CPU 902a is allocated to another virtual machine and is insufficient, as shown in FIG. 9, for example, one high-performance CPU 902a is provided for one virtual machine 903, It is possible to deal with the required processing by allocating two medium performance CPUs 902b and three low performance CPUs 902c. Of course, if the high-performance CPU 902a is free, it is possible to dynamically change the allocation such as two high-performance CPUs and one medium-performance CPU and continue the processing.

As described above, the information processing system 900 according to the second embodiment constantly monitors the usage status of the CPUs 902a to 902c managed by the hypervisors 901a to 901c, and according to the requested processing level inside the virtual machine 903. Thus, appropriate CPU allocation can be dynamically executed, and the CPU performance can be tiered. Further, by allocating the minimum CPU performance, it is possible to further improve the usage efficiency of the hardware resources managed by the hypervisors 901a to 901c.

(Third Embodiment)
An information processing system 1000 according to the third embodiment of the present invention will be described with reference to FIG.
The information processing system 1000 of the third embodiment has a failover function added to the information processing system 100 of the first embodiment.

Conventionally, in order to realize a non-stop fail server when an information processing device used as a server or the like fails, as shown in FIG. 10(a), a hypervisor for backup that copies the entire state of the hypervisor 1001a is used. It was necessary to provide 1001b. In this case, the cost for preparing the hypervisor 1001b and the network band for copying the whole image are consumed, and there is a problem that the economy is poor.

However, in the information processing system 1000 of the third embodiment, taking advantage of the fact that the memory can be shared by a plurality of different hypervisors, the parity data of the memory managed by each hypervisor is transferred to another hypervisor. It is characterized in that it is stored in a memory managed by and is used to realize non-stop failover by using parity data when the information processing device (hypervisor) fails.

In FIG. 10B, virtual machines 1002a and 1002b are operating in the hypervisor 1001a, and each virtual machine 1002a and 1002b occupies a predetermined memory area in the memory managed by the hypervisor 1001a. There is. On the other hand, in the hypervisor 1001b, in addition to the virtual machine 1002c, a memory area 1003 for storing parity data is secured. The virtual machine 1002c occupies a predetermined memory area in the memory managed by the hypervisor 1001b.

The parity data of the memory used by each of the virtual machines 1002a to 1002c is stored in the memory area 1003. Accordingly, even if the hypervisor 1001a is stopped due to some failure, the virtual machines 1002a and 1002b can be restored by another hypervisor using the parity data stored in the memory area 1003, and non-stop failover can be performed. Can be realized.

Although the parity data of the memory areas used by the virtual machines 1002a to 1002c are all stored in the memory area 1003 here, the parity data should be distributed to the memories managed by different hypervisors. Is also possible.

As described above, in the information processing system 1000 according to the second embodiment, it is possible to add the failover function only with the memory area having the capacity of parity data and the network band. This makes it possible to realize failover with excellent redundancy with a small number of information processing devices.

(Fourth Embodiment)
An information processing system 1100 according to the fourth embodiment of the present invention will be described with reference to FIG.
The information processing system 1100 of the fourth embodiment is characterized in that the processing of data stored in the memory managed by a specific hypervisor can be outsourced to another hypervisor. For example, there may be a case where a country that cannot bring data out of the country due to various circumstances outsources only the processing using the data to another country.

In FIG. 11, the hypervisor 1101a located in country A manages the memory 1102a. It is assumed that the data stored in the memory 1102a is prohibited from being taken out of the country due to circumstances peculiar to country A.

On the other hand, the hypervisor 1101b located in country B manages the memory 1102b. Then, it is assumed that Country B uses the information processing system according to the present invention to provide outsourcing to hypervisors of other countries.

In the information processing system 1100 of the fourth embodiment, a plurality of logical processors 1104a to 1104c are operated in a virtual machine (OS) 1103 on a hypervisor 1101a in country A to perform processing, and if necessary, for example, in country A. When the hardware resource (CPU core or the like) has insufficient computing capacity, as shown in FIG. 11, the control information 1105 and the cache data 1106 of a certain logical processor 1104c are transferred to the hypervisor 1101b of country B via the general-purpose network. Transition to. Of course, other than the cached data, other data with high reference frequency may be included.

As a result, the virtual machine 1103 can be operated across the hypervisor 1101a of country A and the hypervisor 1101b of country B, and the hypervisor 1101a of country A can utilize the hardware resources of country B. You can In other words, country B contracts to allow the hypervisor 1101b of country B to be designated as the destination of the control information of the logical processor 1104 operating on the hypervisor 1101a of country A. It enables outsourcing of visors (or hardware resources).

In order to construct the information processing system 1100 of the fourth embodiment, the hypervisor 1101a of country A may specify only the hypervisor 1101b of country B as the destination of the control information of the logical processor 1104. desirable. This is because if the destination is not explicitly decided, the control information may be transmitted to the hypervisor other than country B.

Further, it is desirable that both the hypervisor 1101a of country A and the hypervisor 1101b of country B specify the memory 1102a of country A as a data storage destination. This is because processing data should not be stored in the memory 1102b of country B because the export of data from country A is prohibited.

Strictly speaking, data equivalent to the cache data flows from Country A to Country B. However, the cache data is a very small amount of data in the first place, and the content differs depending on the processing at that time, and is only fragmentary data with high reference frequency. Therefore, although a small amount of fragmentary data flows at the time of the processing, the cache data changes sequentially as the processing progresses, so unlike the case of exporting all the data of country A to the outside of country B, Therefore, it cannot be said that the data of country A has been acquired.

As described above, the information processing system 1100 of the fourth embodiment makes it possible to process only the data existing in the first country in the second country (other countries) without substantially taking the data out of the country. It is possible to utilize the hardware resources of other countries even if there is no hardware resource with high processing capacity in the home country.

(Fifth Embodiment)
In the first to fourth embodiments, an example in which a virtual machine is shared between two hypervisors has been shown, but in the information processing system 1200 of the fifth embodiment, three or more hypervisors are virtualized. An example of sharing a machine is shown.

FIG. 12 shows an information processing system 1200 according to the fifth embodiment. The information processing system 1200 includes four hypervisors 1201a to 1201d, and each hypervisor manages the memories 1202a to 1202d. Then, the virtual machine (OS) 1203 operates across each hypervisor.

Control information 1204a to 1204d and high-reference-frequency data (for example, cache data) 1205a to 1205d are transmitted and received between the hypervisors. As a result, each hypervisor can share the resources (hardware resources) of other hypervisors, and can dynamically provide necessary resources to the virtual machine.

The transmission/reception sequence of each of the control information 1204a to 1204d may be performed simultaneously in parallel or may be performed sequentially. When the simultaneous change is performed, the processing waiting time is reduced and the processing speed can be improved. Further, in the case of performing sequentially, the procedure for establishing the connection is simplified, which has an advantage of requiring less processing when expanding the virtual machine to another hypervisor.

In the present embodiment, an example in which a connection is established between the upper, lower, left, and right hypervisors is schematically shown, but the hypervisor 1202a and the hypervisor 1202d directly send and receive control information 1204 and data 1205 with high reference frequency. Naturally, such a mode is also possible.

Further, it is also possible to transmit/receive the control information 1204 and the data 1205 having high reference frequency to/from a target hypervisor via another hypervisor. For example, when the hypervisor 1202a shares the virtual machine 1203 with the hypervisor 1202d, the control information 1204 and the frequently-referenced data 1205 may be transmitted and received via the hypervisor 1202b or the hypervisor 1202c.

Furthermore, in the present embodiment, an example in which a virtual machine is shared among four hypervisors has been shown, but it is also possible to share a virtual machine among five or more hypervisors.

As described above, in the information processing system 1200 according to the fifth embodiment, by operating the virtual machine across three or more hypervisors, the virtual machine is shared among many hypervisors and the application can be easily performed. It is possible to improve the scale-up type of performance.

(Sixth Embodiment)
An information processing system 1300 according to the sixth embodiment of the present invention will be described with reference to FIG.
The information processing system 1300 of the sixth embodiment differs from the information processing system 100 of the first embodiment in the configuration of the address management table.

In FIG. 13, the hypervisor A 1301a and the hypervisor B 1301b share a virtual machine (OS) 1302. The virtual machine 1302 has a unique address management table 1303 (referred to as an OS address management table). This OS address management table 1303 is an MMU (not shown) in the CPU core that executes the hypervisor A 1301a. ).

The OS address management table 1303 has a function of converting a virtual address in the virtual memory space managed by the virtual machine 1302 into a virtual address (VM internal address) assigned to each virtual machine.

Each hypervisor A 1301a and hypervisor B 1301b has hypervisor address management tables 1304a and 1304b, respectively. The hypervisor address management tables 1304a and 1304b include areas for holding a virtual machine ID (VMID), a virtual machine address (VM internal address), a hypervisor ID, a physical address, and data, respectively.

The virtual machine ID is an ID (identifier) associated with the virtual machine 1302 operating on the hypervisor, and indicates which virtual machine holds the data associated with it. For example, when the virtual machine ID is “OS1”, it means that each area of the row is associated with OS1.

The virtual machine address is an address assigned to each virtual machine, and is an address that can be referred to by the virtual machine indicated by the virtual machine ID.

The hypervisor ID is an identifier indicating the hypervisor of the reference destination or the hypervisor of the reference source. For example, in the hypervisor address management table 1304a in FIG. 13, effective data does not exist in the “physical address” and “data” columns corresponding to the VM internal address “58”. That is, the target data does not exist in the memory managed by the hypervisor A 1031a.

However, in the information processing system 1300 of the sixth embodiment, since the hypervisor ID indicates “B” as the reference destination, the hypervisor address management table 1304b stored in the hypervisor B1301b is referred to and the VM in the table is referred to. By referring to the internal address “58”, the target data “&&&” can be found at the physical address “83” of the memory managed by the hypervisor B1301b.

As described above, in the information processing system 1300 of the sixth embodiment, a hypervisor address management table is provided for each hypervisor, and the concept of hypervisor ID is introduced into the management table, so that the hypervisor of its own Even when the target data does not exist, it is possible to easily refer to the memory of another hypervisor.

Then, if the target data exists in the memory within its own hypervisor, the corresponding physical address is referenced in the address management table for hypervisor, and the target data exists in the memory within its own hypervisor. Otherwise, the hypervisor ID can be used to refer to the corresponding physical address in another hypervisor address management table.

100: Information processing system, 101... General-purpose network, 102-107... Information processing apparatus, 301a-301f... Hypervisor, 302a-302i... Virtual machine (OS), 401a, 401b... Hypervisor, 402a, 402b... Memory, 403a -403f... Logical processor, 404a-404f... Control information, 405... Virtual machine (OS), 406... Data with high reference frequency, 601... Address management table

Claims (3)

In the first information processing device,
A virtual address designating a storage area of a virtual memory space managed by the OS operating on the first information processing apparatus and a storage area of a real memory space in the second information processing apparatus connected via a general-purpose network are designated. A control program for transmitting a processing command to the second information processing apparatus by referring to a management table that correlates with a physical address. The control program according to claim 1, wherein the management table further includes a physical address that specifies a storage area of a real memory space in the first information processing apparatus. The control program according to claim 1, wherein the first information processing apparatus operates the OS, and the second information processing apparatus also operates the OS.

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