JP6351387B2 - INFORMATION PROCESSING APPARATUS, PROGRAM, AND RECORDING MEDIUM - Google Patents

Description

  The present invention relates to an information processing apparatus having a function of operating a virtual machine across a plurality of different hypervisors, a program, and a recording medium.

  In recent years, virtualization technology of computer architecture has attracted attention in various fields. Virtualization technology is the abstraction of computer resources and is a technology that treats computer hardware as virtual. A virtual machine (VM) is known as one of the computer architecture virtualization technologies.

  A virtual machine is software that emulates the operation of a computer or an emulated virtual computer itself. By introducing the concept of virtual machine, it is possible to operate a plurality of operating systems (operating systems) on one computer. And when operating several OS on one computer, the control program which controls those OS exists. This is the hypervisor.

  By running the hypervisor on the server, it is possible to run multiple virtual machines (i.e. multiple kernels). This makes it possible to operate different OSs (referred to as guest OSs) on a single server. And, it is possible to provide the user with various interfaces depending on each OS.

  By the way, conventionally, the hypervisor operates on each server and can not cooperate with other hypervisors operating on other servers. For example, as shown in FIG. 14, it is assumed that a plurality of OSs 12 to 14 are operating under the control of the hypervisor 11 operating on a certain server. At this time, each of the OSs 12 to 14 is actually processed by the CPU (central processing unit) (not shown) in the hypervisor 11 and can access only the memory (not shown) in the hypervisor 11. That is, the hypervisor 11 can use only the resources existing in the server on which the hypervisor 11 operates.

  Similarly, another OS 15 is assumed to be operating under the control of another hypervisor 22 operating on another server. As described above, since resources can not be shared between hypervisors, different hypervisors 11 and 22 can only control OSs 12 to 15 independently, respectively, and one OS is straddled across hypervisors. It was not possible to operate (virtual machine).

  As a result, if it is necessary to improve server performance, or if it is necessary to ensure redundancy in order to cope with server problems, it is only effective to increase the degree of parallelism of the server (scale out). There is a problem that the software development cost and the operation cost become high.

  In order to cope with such a problem, in recent years, as a parallel processing technology of computers, a technology of sharing memory between physically separated CPUs has been developed. For example, in Patent Document 1, the hypervisor detects the arrangement relationship between the local memory, the remote memory, and the CPU, and the memory viewed from the CPU allocated to the virtual machine becomes the remote memory as viewed from the CPU. There is described a technique for moving necessary data to a memory which becomes a local memory.

  Further, Patent Document 2 describes a process of performing address conversion using a memory table in a blade server and accessing a memory on another blade. That is, a technology for causing a blade server to function as an SMP (Symmetric Multiple Processor) server is described.

JP, 2011-238278, A JP, 2012-113604, A

  However, the techniques described in Patent Literatures 1 and 2 do not integrate and control virtual machines under control of different hypervisors, but merely distribute to CPUs under control of different hypervisors. It is what makes processing. Therefore, although it is possible to reduce the processing load of each CPU, it is necessary to perform communication to synchronize processing results with each other, and the overhead resulting from the communication processing results in a factor that hinders the processing efficiency as a whole system. It was also with me.

  In addition, when distributed processing is performed by a CPU, for example, even if one additional CPU is required to operate a virtual machine, a server mounted with 16 CPUs as an extension unit In some cases, extra hardware resources may need to be procured, for example, if the necessary resources are exceeded.

  The present invention is created to overcome such impediment factors, and is an information processing apparatus, program and storage capable of integrating and controlling a plurality of virtual machines under the control of different hypervisors. It provides a medium.

  An information processing apparatus according to an embodiment of the present invention includes an address of a memory managed by a first hypervisor, an address of a memory managed by a second hypervisor connected to the first hypervisor, and the second hypervisor. An address management table for recording an identifier for identifying a visor, and an issuing unit for referring to the address management table and issuing an instruction and control information to the second hypervisor from the first hypervisor. The control information is information indicating a state of a logical processor operating in the second hypervisor.

  An information processing apparatus according to an embodiment of the present invention includes an address of a virtual memory space managed by a first hypervisor, an identifier for identifying a second hypervisor different from the first hypervisor, and the second identifier. An address management table that stores the addresses of memories managed by the hypervisor in association with one another, and control information storage that stores control information indicating the state of the logical processor operating in the first hypervisor or the second hypervisor. And the first hypervisor is capable of transmitting and receiving the control information to and from the second hypervisor, and referring to the address management table, the address of the virtual memory space. An address of a memory managed by the second hypervisor is associated with the second memory.

  The control information may be at least one of a register value indicating a state of the logical processor, a program counter value, and a pointer to a memory.

  The first hypervisor and the second hypervisor may be connected by a general-purpose network that can be addressed by an identifier.

  If the processing target data does not exist in the memory managed by the first hypervisor and the processing target data exists in the memory managed by the second hypervisor, the second hypervisor The control information may be sent to the visor.

  The control information may be the first hypervisor and the second hypervisor according to the usage status of the resource managed by the first hypervisor or the usage status of the resource managed by the second hypervisor. May be sent and received between In particular, it is preferable that the control information be sent to a hypervisor that manages a resource with a surplus in the use status.

  It is preferable to transmit and receive data related to the control information (for example, data having a high reference frequency such as data cached by a logical processor) as well as transmitting and receiving the control information.

  According to the present invention, a plurality of CPUs under control of different hypervisors can be integrated and controlled, and higher processing performance can be realized.

  In addition, it is possible to improve the uneconomicalness of having to procure extra resources required for desired processing to carry out distributed processing, and to realize higher utilization efficiency of hardware resources.

It is a block diagram showing the information processing system concerning a 1st embodiment of the present invention. It is a block diagram showing an information processor concerning a 1st embodiment of the present invention. It is a conceptual diagram which shows the principle in the information processing system of 1st Embodiment of this invention. It is a figure explaining the role of the control information mounted in the information processing system which concerns on 1st Embodiment of this invention. It is a figure explaining the connection establishment procedure in the information processing system concerning a 1st embodiment of the present invention. It is a figure explaining the role of the address management table mounted in the information processing system which concerns on 1st Embodiment of this invention. It is a figure which shows the comparison with the information processing system which concerns on 1st Embodiment of this invention, and the conventional information processing system. It is a figure which shows the comparison with the information processing system which concerns on 1st Embodiment of this invention, and the conventional information processing system. It is a block diagram which shows the information processing system which concerns on 2nd Embodiment of this invention. It is a block diagram which shows the information processing system which concerns on 3rd Embodiment of this invention. It is a block diagram which shows the information processing system which concerns on 4th Embodiment of this invention. It is a block diagram which shows the information processing system which concerns on 5th Embodiment of this invention. It is a figure which shows the structure of the address management table mounted in the information processing system which concerns on 6th Embodiment of this invention. It is a block diagram which shows the conventional information processing system.

  Hereinafter, a mobile terminal according to an embodiment of the present invention will be described in detail with reference to the drawings. The embodiment shown below is an example of the embodiment of the present invention, and the present invention is not limited to these embodiments. In the drawings referred to in this embodiment, the same portions or portions having similar functions are denoted by the same reference numerals or similar reference numerals (reference numerals with A, B, etc. appended after numbers), and the repetition thereof The description of may be omitted. Further, the dimensional ratio of the drawings may be different from the actual ratio for convenience of explanation, or part of the configuration may be omitted from the drawings.

First Embodiment
<System configuration>
FIG. 1 is a block diagram showing an information processing system 100 according to the first embodiment of the present invention. In FIG. 1, reference numeral 101 denotes a general-purpose network, to which information processing apparatuses 102 to 107 are connected via the general-purpose network. Here, the general-purpose network refers to a network whose destination can be specified using an identifier, such as the Internet, a local area network (LAN), and a wide area network (WAN).

  The information processing apparatuses 102 to 107 can communicate with each other via the network 101 according to a predetermined protocol. The protocol differs depending on the general-purpose network, but in the information processing system in the first embodiment, the information processing apparatuses 102 to 107 do not need to be connected by the same general-purpose network. For example, the information processing apparatus 102 and the information processing The general-purpose network connecting the device 105 and the general-purpose network connecting the information processing device 105 and the information processing device 106 may be different.

  FIG. 2 is a block diagram showing an information processing apparatus 200 according to the first embodiment of the present invention. The information processing apparatuses 102 to 107 in FIG. 1 all have the same configuration as the information processing apparatus 200.

  In FIG. 2, reference numeral 201 denotes a multi-core processor, which includes two CPU cores 202 a and 202 b here. Each of the CPU cores 202a and 202b incorporates a memory management unit (MMU) 203a and 203b. Although FIG. 2 exemplifies a multi-core processor, it may be a single core processor or a multiprocessor provided with a plurality of processors.

  The memory management units 203a and 203b hold address management tables 204a and 204b, respectively. The address management table associates an address specifying a storage area of a virtual memory space (hereinafter referred to as "virtual address") with an address specifying a storage area of memory as a hardware resource (hereinafter referred to as "physical address"). It is a table for The information processing system of the first embodiment uses a table different from the conventional address management table in that the physical address and an identifier (a network address such as a MAC address) for specifying another information processing apparatus are stored. Details will be described later.

  Reference numeral 205 denotes a bus, which is a communication path connecting the multi-core processor 201 and each element to be described later. A random access memory (RAM) 206 has a work area 207 and a system memory area 208 used by the multi-core processor 201. The information processing apparatus 200 according to the first embodiment holds, in the system memory area 208, control information 209 indicating the state (status) of the logical processor operating on the hypervisor. That is, the system memory area 208 corresponds to the "control information storage unit" of the present invention. The control information 209 is present as many as the number of logical processors operating on the hypervisor.

  As such control information 209, VMCS (Virtual Machine Control Structure) used by Intel's virtualization support function and VMCB (Virtual Machine Control Block) used by AMD's virtualization support function are known. Any control information may be used as long as it is information indicating the state of the logical processor (for example, at least one of a register value indicating the state of the logical processor, a program counter value, and a pointer to the memory). The operation using the control information 209 will be described later.

  In FIG. 2, reference numeral 210 denotes a ROM (Read Only Memory), which stores various programs such as BIOS. An input / output unit (I / O unit) 211 performs input / output of various data. Reference numeral 212 denotes a communication unit, which performs communication with another information processing apparatus via the general-purpose network 101 of FIG. The communication method may be a wireless method or a wired method, and may have a mechanism for near field communication. Reference numeral 213 denotes a storage that functions as a database, and a large-capacity storage medium such as a hard disk can be used. Of course, other recording media may be used, or cloud computing may be used to hold data without having a specific storage.

<Principle of system>
FIG. 3 is a conceptual view showing the principle of the information processing system of the first embodiment. Reference numerals 301a to 301f denote hypervisors executed by the control unit (specifically, a multi-core processor) of the information processing apparatus. That is, the hypervisor is executed in each information processing apparatus shown in FIGS. 1 and 2 to construct an information processing system in which a plurality of hypervisors 301 a to 301 f are connected via a general-purpose network.

  Reference numerals 302a to 302i denote virtual machines (here, referred to as OS) operating on the hypervisor. A significant difference from the conventional example shown in FIG. 00 is that, in the information processing system of the first embodiment, a virtual machine operates across hypervisors. For example, in FIG. 3, the OS 302 c operates across four hypervisors 301 a to 301 d, and the hypervisors cooperate to operate one virtual machine.

  As described above, in the information processing system according to the first embodiment, the OSs 302a to 302i seamlessly operate among the hypervisors 301a to 301f, and each hypervisor is a hardware resource such as a CPU core or a memory (hardware resources Or simply referred to as resources). That is, the hypervisors 301a to 301f cooperate with each other to share hardware resources with each other, and an information processing system capable of dynamically scaling up virtual machines is constructed.

  Next, a specific implementation method for constructing such an information processing system will be described. FIG. 4 is a diagram for explaining the role of control information implemented in the information processing apparatus constructing the information processing system according to the first embodiment. Here, it is shown that a certain logical processor is transitioning between hypervisors.

  In FIG. 4, 401a and 401b are hypervisors respectively. Each hypervisor 401a, 401b has a memory 402a, 402b, respectively, and holds various data. The memory 402a is a hardware resource provided in the information processing apparatus executing the hypervisor 401a, and the memory 402b is a hardware resource provided in the information processing apparatus executing the hypervisor 401b.

  In the hypervisor 401a, three logical processors 403a to 403c are currently operating, and one new logical processor is to be added. In the hypervisor 401 b, two logical processors 403 d and 403 e are currently operating. 403 f indicates a logical processor that has been operating a time t earlier than the time point of FIG. 4.

  Each of the logical processors 403a to 403e holds control information 404a to 404e in the system memory area. The control information 404f indicating the state of the logical processor 403f that has been operating for a time t before the time point of FIG. 4 is in the transition process from the hypervisor 401b to the hypervisor 401a, as shown in FIG. As described above, transmission of control information 404f is performed via a general-purpose network. Then, the hypervisor 401a can restart the logical processor 403f based on the received control information 404f.

  As described above, in the information processing system 100 according to the first embodiment, the control information 404 is transmitted and received across physical boundaries between hypervisors to operate the logical processor 403 without depending on the hypervisor. As a result, the virtual machine (OS) 405 can be operated to span the hypervisors 401a and 401b.

  As to which CPU of the hypervisor 401a processes the control information 404f, it is desirable to arbitrate between the hypervisors 401a and 401b in advance before transmitting the control information 404f. For example, the CPU of a resource-deficient hypervisor broadcasts a request command for finding a resource-remaining hypervisor on the network or sends it to a server that manages resource usage status. There may be a process of obtaining a transmission destination of control information.

  Once the destination of the control information is determined, an instruction may be sent to the hypervisor asking for permission to use the resource to perform prior confirmation. Then, when the arbitration is completed, the control information is transmitted to the hypervisor which issued the use permission of the resource, so that the resource of the hypervisor which has received the control information can be used. Such arbitration is performed by a CPU under the control of each hypervisor, and the CPU in this case corresponds to the "issue unit" of the present invention.

  Transmission and reception of control information via a general-purpose network may be performed by selecting an appropriate protocol according to the network to be used. For example, FIG. 5 shows a case where an IP network is used as a general-purpose network and TCP / IP is used as a protocol.

  As shown in FIG. 5, in the TCP protocol, the connection between the hypervisor 401 a and the hypervisor 401 b is established by “3 way handshake”. Thereafter, control information 404f and data 406 are transmitted from the hypervisor 401b to the hypervisor 401a. Furthermore, after that, the control information 501 and the data 502 may be transmitted from the hypervisor 401a to the hypervisor 401b.

  As described above, when transitioning the logical processor 403 from the hypervisor 401 b to the hypervisor 401 a, the data cached in the logical processor (for example, data stored in the L1 to L3 caches of the logical processor) or the logical processor It is preferable to cause data 406 with a high reference frequency, such as stack data of the process being handled by the CPU being executed, to transition along with the control information 404. As a result, even if the logical processor 403 makes a transition between hypervisors, the data 406 with a high reference frequency also makes a transition together, so that processing can be executed continuously. Such frequently referenced data 406 is data associated with a logical processor that references it, in other words, data associated with control information indicating the state of the logical processor.

  The address management table may be referred to in order to transmit the data 406 having a high reference frequency. For example, the hypervisor 401b can identify data necessary for transmission by referring to its own address management table, and read out and transmit it from a memory under its management.

  Also, as shown in FIG. 4, when the logical processor 403f that has been processed by the hypervisor 401b transitions to the hypervisor 401a, most of the data that was being processed before the transition is stored in the memory 402b. There is. Therefore, if processing is continued after transition to the hypervisor 401a, the necessity to refer to the memory 402b arises.

  Therefore, in the information processing system 100 according to the first embodiment, a specific means for enabling each hypervisor to access a memory under control of another hypervisor is implemented via a general-purpose network. FIG. 6 is a diagram for explaining the role of the address management table implemented in the information processing apparatus constructing the information processing system according to the first embodiment.

  FIG. 6 shows the state after the transition of the logical processor 403f described with reference to FIG. An address management table 601 is the same as the address management tables 204a and 204b shown in FIG. The address management table 601 associates a virtual address specifying a storage area of a virtual memory space managed by the OS 405 with a physical address specifying a storage area of an actual memory space (a memory space configured by the memories 402a and 402b). Table.

  The physical addresses of the address management table 601 include two types of physical addresses. The first physical address specifies the physical address of the memory 402 a provided in the information processing apparatus (hypervisor 401 a) in which the address management table 601 is stored (“55”, “56”, “57 in FIG. Etc.) and the second physical address specifies the physical address of the memory 402 b provided in another information processing apparatus (hypervisor 401 b) (“identifier + 81”, “identifier + 82”, etc. in FIG. ).

  Here, the second physical address not only designates the physical address but also stores together an identifier (network address) for designating another information processing apparatus on the network. In the first embodiment, although it is expressed as "identifier + 81", the present invention is not limited to this, and any form may be used as long as it is a combination of an identifier and a physical address. As the identifier, an identifier corresponding to a protocol of a general purpose network connecting between hypervisors may be used. For example, "MAC address" or "IP address" can be used.

  It is desirable to use a low latency, wide bandwidth general purpose network to reduce the overhead in inter-hypervisor memory references through the general purpose network as shown in FIG. For example, "infiniBand", "Converged Enhanced Ethernet (registered trademark)", "Serial RapidIO" can be used. However, it is possible to select a general-purpose network at the right place according to the environment, budget, etc. to be used, and use "IP network", for example, to emphasize low cost rather than low latency. There is no particular limitation on the usable general purpose network.

  As described above, the information processing apparatus 200 constructing the information processing system 100 according to the first embodiment can transition the logical processor between the hypervisors by transmitting and receiving control information of each logical processor between the hypervisors. , And one virtual machine (OS) can be operated across hypervisors.

  Furthermore, by providing the address management table shown in FIG. 6 in the CPU under control of each hypervisor, it becomes possible to refer to memory via a general-purpose network between different hypervisors, and physical isolation of the hypervisors. You can operate virtual machines across hypervisors without being aware of As a result, multiple CPUs under control of different hypervisors can be integrated and controlled, and higher processing performance can be realized.

  For example, conventionally, in order to improve the performance of an application, as shown in FIG. 7A, it has been necessary to adopt a scale-out type approach. That is, virtual machines (OS) 702a to 702d are operated independently in a plurality of hypervisors 701a to 701d, respectively, and when the performance of an application is improved, the number of virtual machines, that is, the number of hypervisors is increased. It corresponded by that.

  However, in this case, for example, the virtual machine 701a functions as a command tower (host) and the virtual machines 702a to 702d function as processing nodes (slaves) to perform application processing. There is a problem that it is necessary to perform requests and answers, data synchronization, processing timing adjustment, etc., and a large number of man-hours and high technology are required for development.

  On the other hand, in the information processing system 100 according to the first embodiment, as shown in FIG. 7B, it is possible to adopt a scale-up type approach of operating the virtual machine 702a across the hypervisors 701a to 701d. . Therefore, the application performance can be easily improved simply by performing program development while being aware of only multithreading without being aware of the overhead involved in network communication.

  In addition, the resource of each hypervisor can be efficiently used by transitioning the logical processor to a hypervisor with ample resources (for example, CPU core and memory). That is, by making the logical processor dynamically transition (transition of control information) according to the use status of the resource of each hypervisor, efficient use of the information processing system becomes possible.

  For example, as shown in FIG. 7A, it is assumed that the virtual machine (OS1) 702a is operating in the hypervisor 701a and the CPU core 703a is insufficient. On the other hand, it is assumed that the virtual machine (OS2) 702b is operating in the hypervisor 701b, and one CPU core 703b is left.

  In this case, as shown in FIG. 7B, the surplus CPU core of the hypervisor 701b is allocated to the virtual machine 702a by extending the virtual machine 702a operating on the hypervisor 701a to the hypervisor 701b. Is possible. Therefore, it is possible to improve the uneconomicalness of having to procure extra resources required for desired processing and to carry out distributed processing, and to realize higher utilization efficiency of hardware resources.

  In addition, it is assumed that the virtual machine (OS1) 702a is operating in the hypervisor 701a, and the memory (not shown) in the information processing apparatus in which the hypervisor 701a operates is insufficient. On the other hand, it is assumed that a free space exists in the memory in the information processing apparatus in which the hypervisor 701 b operates, and there is a surplus in capacity.

  In this case, by expanding the virtual machine 702a operating on the hypervisor 701a to the hypervisor 701b, it becomes possible to allocate a free space in the memory managed by the hypervisor 701b to the virtual machine 702a.

Second Embodiment
An information processing system 900 according to a second embodiment of the present invention will be described with reference to FIG. An information processing system 900 according to the second embodiment is obtained by adding a function of tiering CPU performance to be used inside one virtual machine to the information processing system 100 according to the first embodiment.

  Conventionally, only one CPU with the same performance can be used in one virtual machine, and a virtual machine having a corresponding processing capacity is operated for high-level processing, or a virtual machine for backup is operated, etc. , Had to determine the processing level (processing amount) for each virtual machine. Therefore, it has been difficult to flexibly cope with a situation where the required processing changes dynamically.

  However, in the information processing system 900 of the second embodiment, taking advantage of the ability to operate the virtual machine 903 across a plurality of different hypervisors, the CPU performance to be used according to the required processing level can be obtained. It is characterized by changes that dynamically change allocations.

  In FIG. 9, a hypervisor 901a operates in an information processing apparatus equipped with a CPU (hereinafter referred to as "high performance CPU") 902a having a first performance, and a hypervisor 901b has a CPU having a second performance. The hypervisor 901c is an information processing apparatus mounted with a CPU (hereinafter referred to as a "low performance CPU") 902c having a third performance (hereinafter referred to as "medium performance CPU"). Operate. Here, the first performance is the highest, followed by the second performance, the third performance, and so on.

  The term "high-performance CPU" does not mean absolute performance, but rather is a relative comparison of each CPU. That is, as long as the relationship of the first performance> the second performance> the third performance is satisfied, the CPU may have any performance.

  Therefore, since the hypervisor 901a is equipped with the high-performance CPU 902a, it is possible to perform processing at a level relatively higher than that of the other hypervisors 901b and 901c. On the other hand, since the hypervisor 901a is equipped with the low-performance CPU 902c, it can perform processing only at a level relatively lower than that of the other hypervisors 901a and 901b.

  However, even when the low-performance CPU 902 c is used, the processing capacity also increases as the number of allocations increases. Therefore, even if the high-performance CPU 902a is allocated to another virtual machine and is in a deficient state, for example, one high-performance CPU 902a for one virtual machine 903 as shown in FIG. It is possible to cope with the required processing by allocating two medium performance CPUs 902 b and three low performance CPUs 902 c. Of course, if the high-performance CPU 902a is left, it is possible to dynamically change the allocation, such as two high-performance CPUs and one medium-performance CPU, and continue the processing.

  As described above, the information processing system 900 according to the second embodiment constantly monitors the usage status of the CPUs 902a to 902c managed by the hypervisors 901a to 901c, and according to the required processing level inside the virtual machine 903. Thus, it is possible to dynamically execute appropriate CPU allocation and to tier CPU performance. In addition, by allocating the minimum CPU performance, it is possible to further improve the use efficiency of hardware resources managed by each of the hypervisors 901a to 901c.

Third Embodiment
An information processing system 1000 according to a third embodiment of the present invention will be described with reference to FIG. An information processing system 1000 of the third embodiment is obtained by adding a failover function to the information processing system 100 of the first embodiment.

  Conventionally, when an information processing apparatus used as a server or the like breaks down, in order to realize a non-stop fail server, as shown in FIG. 10A, a backup hypervisor which copied the entire state of the hypervisor 1001a. It was necessary to provide 1001b. In this case, the cost for preparing the hypervisor 1001 b and the network bandwidth for copying the whole are consumed, and there is a problem that the economy is bad.

  However, in the information processing system 1000 of the third embodiment, taking advantage of the fact that memory can be shared among a plurality of different hypervisors, parity data of memory managed by each hypervisor can be used as another hypervisor. The present invention is characterized in that non-stop failover is realized by storing the data in a memory managed by the V.5 and utilizing parity data at the time of failure of the information processing apparatus (hypervisor).

  In FIG. 10B, virtual machines 1002a and 1002b are operating in the hypervisor 1001a, and the virtual machines 1002a and 1002b occupy a predetermined memory area in the memory managed by the hypervisor 1001a. There is. On the other hand, in the hypervisor 1001 b, in addition to the virtual machine 1002 c, a memory area 1003 for storing parity data is secured. The virtual machine 1002c occupies a predetermined memory area in the memory managed by the hypervisor 1001b.

  The parity data of the memory used by each of the virtual machines 1002 a to 1002 c is all stored in the memory area 1003. Thus, even if the hypervisor 1001a stops due to any failure, the virtual machines 1002a and 1002b can be repaired by another hypervisor using parity data stored in the memory area 1003, and non-stop failover is performed. It can be realized.

  Although all parity data in the memory area used by each of the virtual machines 1002a to 1002c is stored in the memory area 1003 here, the parity data is distributed to memories managed by a plurality of different hypervisors. Is also possible.

  As described above, in the information processing system 1000 of the second embodiment, it is possible to add the failover function only with the memory area and the network band of the capacity for parity data. As a result, it is possible to realize failover with excellent redundancy with a small number of information processing apparatuses.

Fourth Embodiment
An information processing system 1100 according to a fourth embodiment of the present invention will be described with reference to FIG. The information processing system 1100 of the fourth embodiment is characterized in that processing of data stored in a memory managed by a specific hypervisor can be outsourced to another hypervisor. For example, there may be a case where a country that can not bring data out of the country due to various circumstances outsources processing using only that data to another country.

  In FIG. 11, a hypervisor 1101a disposed in country A manages a memory 1102a. Then, it is assumed that the data stored in the memory 1102a is prohibited from being taken out of the country due to circumstances specific to Country A.

  On the other hand, the hypervisor 1101b disposed in the country B manages the memory 1102b. Country B then uses the information processing system according to the present invention to provide outsourcing to hypervisors in other countries.

  In the information processing system 1100 of the fourth embodiment, a plurality of logical processors 1104a to 1104c are operated and processed in a virtual machine (OS) 1103 on a hypervisor 1101a of country A, for example, if necessary. When hardware resources (CPU core etc.) run out of computing capacity, as shown in FIG. 11, control information 1105 and cache data 1106 of a certain logical processor 1104 c are stored in the hypervisor 1101 b of country B via a general purpose network. Transition to Of course, other than cache data, other frequently referenced data may be included.

  Thus, the virtual machine 1103 can be operated across the hypervisor 1101a of country A and the hypervisor 1101b of country B, and the hypervisor 1101a of country A utilizes hardware resources of country B. Can. In other words, the country B allows the country B hyper by permitting the country B hypervisor 1101 b to be designated as a transmission destination of control information of the logical processor 1104 operating on the country A hypervisor 1101 a. It enables outsourcing of visors (or hardware resources).

  In addition, in order to construct the information processing system 1100 of the fourth embodiment, the hypervisor 1101a of country A may designate only the hypervisor 1101b of country B as a transmission destination of control information of the logical processor 1104. desirable. This is because there is a risk that control information may be transmitted to hypervisors other than country B if the destination is not explicitly decided.

  Further, it is desirable that both the hypervisor 1101a of the country A and the hypervisor 1101b of the country B designate the memory 1102a of the country A as a data storage destination. This is because the processing data should not be stored in the memory 1102b of the country B as long as taking out the data from the country A is prohibited.

  Strictly speaking, data equivalent to cash data flows from country A to country B. However, the cache data is very small as the amount of data, and the content differs depending on the processing at that time, and it is only fragmentary data with a high reference frequency. Therefore, although a small amount of fragmented data flows at the time of processing, the cache data changes sequentially as the processing progresses, and this is different from bringing out data of Country A entirely, unlike from Country B It can be said that it does not mean that data on Country A has been acquired.

  As described above, the information processing system 1100 according to the fourth embodiment can process only the processing in the second country (other countries) without bringing the data existing in the first country out of the country substantially. It is possible to utilize hardware resources of other countries, even if there are no high-performance hardware resources in one's own country.

Fifth Embodiment
In the first to fourth embodiments, an example is shown in which a virtual machine is shared between two hypervisors, but in the information processing system 1200 of the fifth embodiment, virtual machines are shared between three or more hypervisors. An example of sharing a machine is shown.

  FIG. 12 shows an information processing system 1200 according to the fifth embodiment. The information processing system 1200 includes four hypervisors of hypervisors 1201 a to 1201 d, and each hypervisor manages the memories 1202 a to 1202 d. Then, a virtual machine (OS) 1203 operates across the hypervisors.

  Control information 1204 a to 1204 d and data with high reference frequency (for example, cache data) 1205 a to 1205 d are transmitted and received between the hypervisors. By this, each hypervisor can share the resources (hardware resources) of other hypervisors, and can dynamically provide necessary resources to the virtual machine.

  The transmission and reception sequences of the control information 1204 a to 1204 d may be performed simultaneously or in parallel. The simultaneous change reduces the processing waiting time and can improve the processing speed. In addition, in the case of sequential processing, the procedure for establishing a connection is simplified, so that there is an advantage that processing for extending a virtual machine to another hypervisor can be reduced.

  In the present embodiment, an example of establishing a connection between the upper, lower, left, and right hypervisors is schematically shown, but the hypervisor 1202 a and the hypervisor 1202 d directly transmit and receive the control information 1204 and the data 1205 having a high reference frequency. Naturally, it is also possible to take an aspect that

  In addition, it is also possible to transmit and receive control information 1204 and data 1205 with a high frequency of reference to and from a target hypervisor via another hypervisor. For example, when the hypervisor 1202a shares the virtual machine 1203 with the hypervisor 1202d, it may be possible to transmit and receive control information 1204 and frequently referenced data 1205 via the hypervisor 1202b or the hypervisor 1202c.

  Furthermore, in the present embodiment, an example in which virtual machines are shared among four hypervisors is shown, but virtual machines can be shared among five or more hypervisors.

  As described above, in the information processing system 1200 according to the fifth embodiment, a virtual machine is shared among many hypervisors by operating the virtual machine across three or more hypervisors, thereby facilitating application. Scale-up improvement of performance can be achieved.

Sixth Embodiment
An information processing system 1300 according to the sixth embodiment of the present invention will be described with reference to FIG. The information processing system 1300 of the sixth embodiment differs from the information processing system 100 of the first embodiment in the configuration of the address management table.

  In FIG. 13, the hypervisor A 1301 a and the hypervisor B 1301 b share a virtual machine (OS) 1302. The virtual machine 1302 has a unique address management table 1303 (referred to as an OS address management table). The OS address management table 1303 is an MMU (not shown) in the CPU core that executes the hypervisor A 1301 a Is stored in).

  The OS address management table 1303 has a function of converting a virtual address in a virtual memory space managed by the virtual machine 1302 into a virtual address (in-VM address) allocated for each virtual machine.

  Each hypervisor A 1301 a and hypervisor B 1301 b has hypervisor address management tables 1304 a and 1304 b, respectively. The hypervisor address management tables 1304a and 1304b respectively include virtual machine IDs (VMIDs), virtual machine internal addresses (VM internal addresses), hypervisor IDs, physical addresses, and areas for holding data.

  The virtual machine ID is an ID (identifier) associated with the virtual machine 1302 operating on the hypervisor, and indicates which virtual machine the data associated with is held. For example, when the virtual machine ID is "OS1", it means that each area of the row is associated with the OS1.

  The virtual machine internal address is an address allocated to each virtual machine, and is an address that can be referred to by the virtual machine indicated by the virtual machine ID.

  The hypervisor ID is an identifier that indicates a reference destination hypervisor or a reference source hypervisor. For example, in the hypervisor address management table 1304 a of FIG. 13, effective data does not exist in the “physical address” or “data” column corresponding to the in-VM address “58”. That is, the target data does not exist in the memory managed by the hypervisor A 1031a.

  However, in the information processing system 1300 of the sixth embodiment, since the hypervisor ID indicates “B” as a reference destination, the hypervisor address management table 1304 b stored in the hypervisor B 1301 b is referred to, and VMs in the table are referred to. By referring to the internal address “58”, the target data “&&&” can be found at the physical address “83” of the memory managed by the hypervisor B 1301 b.

  As described above, in the information processing system 1300 according to the sixth embodiment, the hypervisor address management table is provided for each hypervisor, and the concept of the hypervisor ID is introduced into the management table to allow the hypervisor itself to operate. Even when there is no target data, it is possible to easily refer to the memory of another hypervisor.

  Then, if the target data exists in the memory in its own hypervisor, the hypervisor address management table refers to the corresponding physical address, and the target data exists in the memory in its own hypervisor. If not, the corresponding physical address can be referred to in another hypervisor address management table using the hypervisor ID.

100: information processing system, 101: general-purpose network, 102 to 107: information processing device, 301a to 301f, hypervisor, 302a to 302i, virtual machine (OS), 401a, 401b: hypervisor, 402a, 402b: memory, 403a To 403 f: logical processor, 404 a to 404 f: control information, 405: virtual machine (OS), 406: data with high reference frequency, 601: address management table

Claims (13)

And a memory address managed by the first hypervisor, address records management and an identifier identifying the first second management addresses and the hypervisor of the second memory hypervisor to work with hypervisor Table,
An information processing apparatus, comprising: a communication unit that transmits and receives an instruction and control information between the first hypervisor and the second hypervisor with reference to the address management table.   The information processing apparatus according to claim 1, wherein the control information is information indicating a state of a logical processor operating in the second hypervisor. An address of a virtual memory space managed by a first hypervisor, an identifier identifying a second hypervisor different from the first hypervisor, and an address of a memory managed by the second hypervisor are associated with each other Address management table to be stored,
A control information storage unit storing control information indicating a state of a logical processor operating in the first hypervisor or the second hypervisor;
Have
The first hypervisor is capable of transmitting and receiving the control information to and from the second hypervisor, and refers to the address management table to associate the address with the address of the virtual memory space. An information processing apparatus capable of accessing an address of a memory managed by the second hypervisor.   The information processing apparatus according to any one of claims 1 to 3, wherein the control information is at least one of a register value indicating a state of a logical processor, a program counter value, and a pointer to a memory. The information processing apparatus according to any one of claims 1 to 4, wherein the first hypervisor and the second hypervisor cooperate with each other via a general-purpose network capable of destination specification by an identifier.   If the processing target data does not exist in the memory managed by the first hypervisor and the processing target data exists in the memory managed by the second hypervisor, the second hypervisor The information processing apparatus according to any one of claims 1 to 5, wherein the control information is transmitted to a visor.   The control information may be the first hypervisor and the second hypervisor according to the usage status of the resource managed by the first hypervisor or the usage status of the resource managed by the second hypervisor. The information processing apparatus according to any one of claims 1 to 6, wherein the information is transmitted and received.   The information processing apparatus according to claim 7, wherein the control information is transmitted to a hypervisor that manages a resource having a surplus in the use status.   The information processing apparatus according to any one of claims 1 to 6, which transmits and receives data related to the control information as well as transmitting and receiving the control information. Computer,
And a memory address managed by the first hypervisor, address records management and an identifier identifying the first second management addresses and the hypervisor of the second memory hypervisor to work with hypervisor An address management table storage unit for storing a table;
A program that functions as a communication unit that transmits and receives instructions and control information between the first hypervisor and the second hypervisor with reference to the address management table.   The program according to claim 10, wherein the control information is information indicating a state of a logical processor operating in the second hypervisor. Computer,
An address of a virtual memory space managed by a first hypervisor, an identifier identifying a second hypervisor different from the first hypervisor, and an address of a memory managed by the second hypervisor are associated with each other An address management table storage unit that stores an address management table to be stored;
It functions as a control information storage unit that stores control information indicating the state of a logical processor operating in the first hypervisor or the second hypervisor,
The first hypervisor is capable of transmitting and receiving the control information to and from the second hypervisor, and referring to the address management table, the first hypervisor is associated with the address of the virtual memory space, A program that enables access to memory addresses managed by the 2 hypervisor. A computer readable recording medium storing the program according to any one of claims 10 to 12.

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