JP2016536658A5 - - Google Patents

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Publication number
JP2016536658A5
JP2016536658A5 JP2016516553A JP2016516553A JP2016536658A5 JP 2016536658 A5 JP2016536658 A5 JP 2016536658A5 JP 2016516553 A JP2016516553 A JP 2016516553A JP 2016516553 A JP2016516553 A JP 2016516553A JP 2016536658 A5 JP2016536658 A5 JP 2016536658A5
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JP
Japan
Prior art keywords
memory
round
address bits
mapping
bits
Prior art date
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Application number
JP2016516553A
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English (en)
Japanese (ja)
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JP6105814B2 (ja
JP2016536658A (ja
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Priority claimed from US14/251,626 external-priority patent/US9495291B2/en
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Publication of JP2016536658A publication Critical patent/JP2016536658A/ja
Publication of JP2016536658A5 publication Critical patent/JP2016536658A5/ja
Application granted granted Critical
Publication of JP6105814B2 publication Critical patent/JP6105814B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2016516553A 2013-09-27 2014-09-12 メモリインターリーブのための構成可能な分散機能 Expired - Fee Related JP6105814B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361883833P 2013-09-27 2013-09-27
US61/883,833 2013-09-27
US14/251,626 2014-04-13
US14/251,626 US9495291B2 (en) 2013-09-27 2014-04-13 Configurable spreading function for memory interleaving
PCT/US2014/055449 WO2015047753A1 (en) 2013-09-27 2014-09-12 Configurable spreading function for memory interleaving

Publications (3)

Publication Number Publication Date
JP2016536658A JP2016536658A (ja) 2016-11-24
JP2016536658A5 true JP2016536658A5 (enExample) 2017-02-23
JP6105814B2 JP6105814B2 (ja) 2017-03-29

Family

ID=52741322

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016516553A Expired - Fee Related JP6105814B2 (ja) 2013-09-27 2014-09-12 メモリインターリーブのための構成可能な分散機能

Country Status (6)

Country Link
US (1) US9495291B2 (enExample)
EP (1) EP3049935B1 (enExample)
JP (1) JP6105814B2 (enExample)
KR (1) KR101779545B1 (enExample)
CN (1) CN105518632B (enExample)
WO (1) WO2015047753A1 (enExample)

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KR102464801B1 (ko) * 2015-04-14 2022-11-07 삼성전자주식회사 반도체 장치의 동작 방법 및 반도체 시스템
CN107180001B (zh) * 2016-03-10 2020-02-21 华为技术有限公司 访问动态随机存储器dram的方法和总线
US10140223B2 (en) 2016-06-27 2018-11-27 Qualcomm Incorporated System and method for odd modulus memory channel interleaving
US10037306B2 (en) * 2016-09-01 2018-07-31 Qualcomm Incorporated Approximation of non-linear functions in fixed point using look-up tables
US10642733B1 (en) * 2018-07-12 2020-05-05 Lightbits Labs Ltd. System and method for memory interface load balancing
CN112513824B (zh) * 2018-07-31 2024-04-09 华为技术有限公司 一种内存交织方法及装置
US10990517B1 (en) * 2019-01-28 2021-04-27 Xilinx, Inc. Configurable overlay on wide memory channels for efficient memory access
CN112395216B (zh) * 2019-07-31 2025-08-29 北京百度网讯科技有限公司 用于存储管理的方法、装置、设备和计算机可读存储介质
KR102879451B1 (ko) * 2019-12-20 2025-11-03 에스케이하이닉스 주식회사 데이터 저장 장치 및 그것의 동작 방법
JP2024044793A (ja) * 2022-09-21 2024-04-02 キオクシア株式会社 メモリシステム、制御装置および方法

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JPS6097446A (ja) * 1983-10-31 1985-05-31 Mitsubishi Electric Corp 記憶装置
US5341486A (en) * 1988-10-27 1994-08-23 Unisys Corporation Automatically variable memory interleaving system
US5479624A (en) * 1992-10-14 1995-12-26 Lee Research, Inc. High-performance interleaved memory system comprising a prime number of memory modules
US5924111A (en) * 1995-10-17 1999-07-13 Huang; Chu-Kai Method and system for interleaving data in multiple memory bank partitions
US6381669B1 (en) * 1999-12-27 2002-04-30 Gregory V. Chudnovsky Multi-bank, fault-tolerant, high-performance memory addressing system and method
JP2003228517A (ja) * 2002-02-01 2003-08-15 Matsushita Electric Ind Co Ltd メモリ装置
US6941438B2 (en) 2003-01-10 2005-09-06 Intel Corporation Memory interleaving
US20050172091A1 (en) 2004-01-29 2005-08-04 Rotithor Hemant G. Method and an apparatus for interleaving read data return in a packetized interconnect to memory
US8190809B2 (en) * 2004-11-23 2012-05-29 Efficient Memory Technology Shunted interleave for accessing plural memory banks, particularly those having partially accessed cells containing data for cache lines
KR100699491B1 (ko) * 2005-07-19 2007-03-26 삼성전자주식회사 인터리빙 방법 및 그 장치
CN101292229B (zh) * 2005-12-28 2012-05-30 富士通株式会社 用于控制存储器的方法和设备
US20080250212A1 (en) 2007-04-09 2008-10-09 Ati Technologies Ulc Method and apparatus for accessing memory using programmable memory accessing interleaving ratio information
US7996597B1 (en) * 2007-04-16 2011-08-09 Juniper Networks, Inc. Mapping address bits to improve spread of banks
US8051239B2 (en) * 2007-06-04 2011-11-01 Nokia Corporation Multiple access for parallel turbo decoder
US8438320B2 (en) 2007-06-25 2013-05-07 Sonics, Inc. Various methods and apparatus for address tiling and channel interleaving throughout the integrated system
US8751769B2 (en) * 2007-12-21 2014-06-10 Qualcomm Incorporated Efficient address generation for pruned interleavers and de-interleavers
US8886898B2 (en) * 2009-08-19 2014-11-11 Oracle America, Inc. Efficient interleaving between a non-power-of-two number of entities
US8438434B2 (en) * 2009-12-30 2013-05-07 Nxp B.V. N-way parallel turbo decoder architecture
US20120054455A1 (en) 2010-08-31 2012-03-01 Qualcomm Incorporated Non-Uniform Interleaving Scheme In Multiple Channel DRAM System
US20120137090A1 (en) * 2010-11-29 2012-05-31 Sukalpa Biswas Programmable Interleave Select in Memory Controller

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