JP6105814B2 - メモリインターリーブのための構成可能な分散機能 - Google Patents

メモリインターリーブのための構成可能な分散機能 Download PDF

Info

Publication number
JP6105814B2
JP6105814B2 JP2016516553A JP2016516553A JP6105814B2 JP 6105814 B2 JP6105814 B2 JP 6105814B2 JP 2016516553 A JP2016516553 A JP 2016516553A JP 2016516553 A JP2016516553 A JP 2016516553A JP 6105814 B2 JP6105814 B2 JP 6105814B2
Authority
JP
Japan
Prior art keywords
memory
address bits
round
bits
mapping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2016516553A
Other languages
English (en)
Japanese (ja)
Other versions
JP2016536658A (ja
JP2016536658A5 (enExample
Inventor
フェン・ワン
ボフスラフ・ライチリック
アンワル・ロヒリヤ
Original Assignee
クアルコム,インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by クアルコム,インコーポレイテッド filed Critical クアルコム,インコーポレイテッド
Publication of JP2016536658A publication Critical patent/JP2016536658A/ja
Publication of JP2016536658A5 publication Critical patent/JP2016536658A5/ja
Application granted granted Critical
Publication of JP6105814B2 publication Critical patent/JP6105814B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607Interleaved addressing
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10Providing a specific technical effect
    • G06F2212/1016Performance improvement

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2016516553A 2013-09-27 2014-09-12 メモリインターリーブのための構成可能な分散機能 Expired - Fee Related JP6105814B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361883833P 2013-09-27 2013-09-27
US61/883,833 2013-09-27
US14/251,626 2014-04-13
US14/251,626 US9495291B2 (en) 2013-09-27 2014-04-13 Configurable spreading function for memory interleaving
PCT/US2014/055449 WO2015047753A1 (en) 2013-09-27 2014-09-12 Configurable spreading function for memory interleaving

Publications (3)

Publication Number Publication Date
JP2016536658A JP2016536658A (ja) 2016-11-24
JP2016536658A5 JP2016536658A5 (enExample) 2017-02-23
JP6105814B2 true JP6105814B2 (ja) 2017-03-29

Family

ID=52741322

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016516553A Expired - Fee Related JP6105814B2 (ja) 2013-09-27 2014-09-12 メモリインターリーブのための構成可能な分散機能

Country Status (6)

Country Link
US (1) US9495291B2 (enExample)
EP (1) EP3049935B1 (enExample)
JP (1) JP6105814B2 (enExample)
KR (1) KR101779545B1 (enExample)
CN (1) CN105518632B (enExample)
WO (1) WO2015047753A1 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102464801B1 (ko) * 2015-04-14 2022-11-07 삼성전자주식회사 반도체 장치의 동작 방법 및 반도체 시스템
CN107180001B (zh) * 2016-03-10 2020-02-21 华为技术有限公司 访问动态随机存储器dram的方法和总线
US10140223B2 (en) 2016-06-27 2018-11-27 Qualcomm Incorporated System and method for odd modulus memory channel interleaving
US10037306B2 (en) * 2016-09-01 2018-07-31 Qualcomm Incorporated Approximation of non-linear functions in fixed point using look-up tables
US10642733B1 (en) * 2018-07-12 2020-05-05 Lightbits Labs Ltd. System and method for memory interface load balancing
CN112513824B (zh) * 2018-07-31 2024-04-09 华为技术有限公司 一种内存交织方法及装置
US10990517B1 (en) * 2019-01-28 2021-04-27 Xilinx, Inc. Configurable overlay on wide memory channels for efficient memory access
CN112395216B (zh) * 2019-07-31 2025-08-29 北京百度网讯科技有限公司 用于存储管理的方法、装置、设备和计算机可读存储介质
KR102879451B1 (ko) * 2019-12-20 2025-11-03 에스케이하이닉스 주식회사 데이터 저장 장치 및 그것의 동작 방법
JP2024044793A (ja) * 2022-09-21 2024-04-02 キオクシア株式会社 メモリシステム、制御装置および方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6097446A (ja) * 1983-10-31 1985-05-31 Mitsubishi Electric Corp 記憶装置
US5341486A (en) * 1988-10-27 1994-08-23 Unisys Corporation Automatically variable memory interleaving system
US5479624A (en) * 1992-10-14 1995-12-26 Lee Research, Inc. High-performance interleaved memory system comprising a prime number of memory modules
US5924111A (en) * 1995-10-17 1999-07-13 Huang; Chu-Kai Method and system for interleaving data in multiple memory bank partitions
US6381669B1 (en) * 1999-12-27 2002-04-30 Gregory V. Chudnovsky Multi-bank, fault-tolerant, high-performance memory addressing system and method
JP2003228517A (ja) * 2002-02-01 2003-08-15 Matsushita Electric Ind Co Ltd メモリ装置
US6941438B2 (en) 2003-01-10 2005-09-06 Intel Corporation Memory interleaving
US20050172091A1 (en) 2004-01-29 2005-08-04 Rotithor Hemant G. Method and an apparatus for interleaving read data return in a packetized interconnect to memory
US8190809B2 (en) * 2004-11-23 2012-05-29 Efficient Memory Technology Shunted interleave for accessing plural memory banks, particularly those having partially accessed cells containing data for cache lines
KR100699491B1 (ko) * 2005-07-19 2007-03-26 삼성전자주식회사 인터리빙 방법 및 그 장치
CN101292229B (zh) * 2005-12-28 2012-05-30 富士通株式会社 用于控制存储器的方法和设备
US20080250212A1 (en) 2007-04-09 2008-10-09 Ati Technologies Ulc Method and apparatus for accessing memory using programmable memory accessing interleaving ratio information
US7996597B1 (en) * 2007-04-16 2011-08-09 Juniper Networks, Inc. Mapping address bits to improve spread of banks
US8051239B2 (en) * 2007-06-04 2011-11-01 Nokia Corporation Multiple access for parallel turbo decoder
US8438320B2 (en) 2007-06-25 2013-05-07 Sonics, Inc. Various methods and apparatus for address tiling and channel interleaving throughout the integrated system
US8751769B2 (en) * 2007-12-21 2014-06-10 Qualcomm Incorporated Efficient address generation for pruned interleavers and de-interleavers
US8886898B2 (en) * 2009-08-19 2014-11-11 Oracle America, Inc. Efficient interleaving between a non-power-of-two number of entities
US8438434B2 (en) * 2009-12-30 2013-05-07 Nxp B.V. N-way parallel turbo decoder architecture
US20120054455A1 (en) 2010-08-31 2012-03-01 Qualcomm Incorporated Non-Uniform Interleaving Scheme In Multiple Channel DRAM System
US20120137090A1 (en) * 2010-11-29 2012-05-31 Sukalpa Biswas Programmable Interleave Select in Memory Controller

Also Published As

Publication number Publication date
EP3049935A1 (en) 2016-08-03
KR101779545B1 (ko) 2017-09-18
JP2016536658A (ja) 2016-11-24
CN105518632B (zh) 2019-07-09
WO2015047753A1 (en) 2015-04-02
EP3049935B1 (en) 2018-05-30
US20150095595A1 (en) 2015-04-02
US9495291B2 (en) 2016-11-15
KR20160061387A (ko) 2016-05-31
CN105518632A (zh) 2016-04-20

Similar Documents

Publication Publication Date Title
JP6105814B2 (ja) メモリインターリーブのための構成可能な分散機能
US11487676B2 (en) Address mapping in memory systems
US20220197820A1 (en) Isolated performance domains in a memory system
US8386701B2 (en) Apparatus and method for multi-level cache utilization
EP3485383B1 (en) Memory controller with flexible address decoding
US9213645B2 (en) Command aware partial page programming
US20100082917A1 (en) Solid state storage system and method of controlling solid state storage system using a multi-plane method and an interleaving method
US7318114B1 (en) System and method for dynamic memory interleaving and de-interleaving
TWI710899B (zh) 計算系統以及其操作方法
US11487447B2 (en) Hardware-software collaborative address mapping scheme for efficient processing-in-memory systems
CN106055495B (zh) 用于控制半导体装置的方法
JP2005092374A (ja) メモリインタリーブ方式
US11620225B1 (en) System and method for mapping memory addresses to locations in set-associative caches
EP3220276A1 (en) Non-linear cache logic
US9921969B2 (en) Generation of random address mapping in non-volatile memories using local and global interleaving
US20170108911A1 (en) System and method for page-by-page memory channel interleaving
KR20110050401A (ko) 개선된 마이크로프로세서 또는 마이크로컨트롤러
WO2006021747A1 (en) A memory controller
US9690715B2 (en) Selecting hash values based on matrix rank
US7787311B2 (en) Memory with programmable address strides for accessing and precharging during the same access cycle
US11194733B2 (en) Accelerating access to memory banks in a data storage system
US10579519B2 (en) Interleaved access of memory
JPH0981453A (ja) メモリ制御方法及びその実施装置
US12008248B2 (en) Systems, methods, and devices for utilization aware memory allocation
JP3704101B2 (ja) 画像処理装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170118

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20170118

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20170118

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20170126

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20170206

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20170302

R150 Certificate of patent or registration of utility model

Ref document number: 6105814

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees