JP2016532974A5 - - Google Patents
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- Publication number
- JP2016532974A5 JP2016532974A5 JP2016538917A JP2016538917A JP2016532974A5 JP 2016532974 A5 JP2016532974 A5 JP 2016532974A5 JP 2016538917 A JP2016538917 A JP 2016538917A JP 2016538917 A JP2016538917 A JP 2016538917A JP 2016532974 A5 JP2016532974 A5 JP 2016532974A5
- Authority
- JP
- Japan
- Prior art keywords
- memory
- umc
- host interface
- host
- interface circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
- 238000000034 method Methods 0.000 claims 7
- 230000008878 coupling Effects 0.000 claims 4
- 238000010168 coupling process Methods 0.000 claims 4
- 238000005859 coupling reaction Methods 0.000 claims 4
- 238000004891 communication Methods 0.000 claims 2
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/016,717 US10185515B2 (en) | 2013-09-03 | 2013-09-03 | Unified memory controller for heterogeneous memory on a multi-chip package |
| US14/016,717 | 2013-09-03 | ||
| PCT/US2014/045983 WO2015034580A1 (en) | 2013-09-03 | 2014-07-09 | Unified memory controller for heterogeneous memory on a multi-chip package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2016532974A JP2016532974A (ja) | 2016-10-20 |
| JP2016532974A5 true JP2016532974A5 (https=) | 2017-08-03 |
Family
ID=51293140
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016538917A Ceased JP2016532974A (ja) | 2013-09-03 | 2014-07-09 | マルチチップパッケージ上の異種メモリ用の統合メモリコントローラ |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US10185515B2 (https=) |
| EP (1) | EP3042295A1 (https=) |
| JP (1) | JP2016532974A (https=) |
| KR (1) | KR20160048911A (https=) |
| CN (1) | CN105493061B (https=) |
| WO (1) | WO2015034580A1 (https=) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102408613B1 (ko) | 2015-08-27 | 2022-06-15 | 삼성전자주식회사 | 메모리 모듈의 동작 방법, 및 메모리 모듈을 제어하는 프로세서의 동작 방법, 및 사용자 시스템 |
| US10268541B2 (en) | 2016-08-15 | 2019-04-23 | Samsung Electronics Co., Ltd. | DRAM assist error correction mechanism for DDR SDRAM interface |
| KR102482896B1 (ko) | 2017-12-28 | 2022-12-30 | 삼성전자주식회사 | 이종 휘발성 메모리 칩들을 포함하는 메모리 장치 및 이를 포함하는 전자 장치 |
| US20210233585A1 (en) * | 2020-01-29 | 2021-07-29 | Micron Technology, Inc. | Multichip memory package with internal channel |
| US12475068B2 (en) * | 2022-09-15 | 2025-11-18 | Micron Technology, Inc. | Multi-interface memory |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100383774B1 (ko) | 2000-01-26 | 2003-05-12 | 삼성전자주식회사 | 공통 인터페이스 방식의 메모리 장치들을 구비한 시스템 |
| JP4049297B2 (ja) | 2001-06-11 | 2008-02-20 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
| JP4059002B2 (ja) | 2001-06-13 | 2008-03-12 | 株式会社日立製作所 | メモリ装置 |
| KR101085406B1 (ko) | 2004-02-16 | 2011-11-21 | 삼성전자주식회사 | 불 휘발성 메모리를 제어하기 위한 컨트롤러 |
| WO2006080908A1 (en) | 2005-01-25 | 2006-08-03 | Chien-Chiang Chan | A single chip having a magnetoresistive memory |
| CN101194235A (zh) | 2005-06-09 | 2008-06-04 | 松下电器产业株式会社 | 存储器控制装置及存储器控制方法 |
| US20060294295A1 (en) | 2005-06-24 | 2006-12-28 | Yukio Fukuzo | DRAM chip device well-communicated with flash memory chip and multi-chip package comprising such a device |
| US8291295B2 (en) | 2005-09-26 | 2012-10-16 | Sandisk Il Ltd. | NAND flash memory controller exporting a NAND interface |
| US7519754B2 (en) | 2005-12-28 | 2009-04-14 | Silicon Storage Technology, Inc. | Hard disk drive cache memory and playback device |
| US20070147115A1 (en) | 2005-12-28 | 2007-06-28 | Fong-Long Lin | Unified memory and controller |
| US7716411B2 (en) | 2006-06-07 | 2010-05-11 | Microsoft Corporation | Hybrid memory device with single interface |
| TWI530791B (zh) | 2007-01-10 | 2016-04-21 | 木比爾半導體股份有限公司 | 用於改善外部計算裝置效能的調適性記憶體系統 |
| US8700830B2 (en) * | 2007-11-20 | 2014-04-15 | Spansion Llc | Memory buffering system that improves read/write performance and provides low latency for mobile systems |
| CN101303885A (zh) | 2008-07-01 | 2008-11-12 | 普天信息技术研究院有限公司 | 多芯片封装存储模块 |
| US7778101B2 (en) | 2008-09-05 | 2010-08-17 | Genesys Logic, Inc. | Memory module and method of performing the same |
| JP2011070470A (ja) | 2009-09-28 | 2011-04-07 | Toshiba Corp | 半導体記憶装置 |
-
2013
- 2013-09-03 US US14/016,717 patent/US10185515B2/en active Active
-
2014
- 2014-07-09 WO PCT/US2014/045983 patent/WO2015034580A1/en not_active Ceased
- 2014-07-09 KR KR1020167008120A patent/KR20160048911A/ko not_active Withdrawn
- 2014-07-09 JP JP2016538917A patent/JP2016532974A/ja not_active Ceased
- 2014-07-09 CN CN201480048456.3A patent/CN105493061B/zh not_active Expired - Fee Related
- 2014-07-09 EP EP14748020.6A patent/EP3042295A1/en not_active Withdrawn
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