JP2016529844A - 構成可能なクロックツリー - Google Patents

構成可能なクロックツリー Download PDF

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Publication number
JP2016529844A
JP2016529844A JP2016538970A JP2016538970A JP2016529844A JP 2016529844 A JP2016529844 A JP 2016529844A JP 2016538970 A JP2016538970 A JP 2016538970A JP 2016538970 A JP2016538970 A JP 2016538970A JP 2016529844 A JP2016529844 A JP 2016529844A
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JP
Japan
Prior art keywords
clock
lanes
lane
level
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
JP2016538970A
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English (en)
Japanese (ja)
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JP2016529844A5 (https=
Inventor
ヤシン・シュウイ
Original Assignee
クアルコム，インコーポレイテッド
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Filing date
Publication date
Application filed by クアルコム，インコーポレイテッド filed Critical クアルコム，インコーポレイテッド
Publication of JP2016529844A publication Critical patent/JP2016529844A/ja
Publication of JP2016529844A5 publication Critical patent/JP2016529844A5/ja
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
    • G06F13/4273—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Information Transfer Systems (AREA)
  • Dc Digital Transmission (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2016538970A 2013-08-30 2014-08-19 構成可能なクロックツリー Ceased JP2016529844A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361872547P 2013-08-30 2013-08-30
US61/872,547 2013-08-30
US14/462,327 2014-08-18
US14/462,327 US9825755B2 (en) 2013-08-30 2014-08-18 Configurable clock tree
PCT/US2014/051756 WO2015031114A1 (en) 2013-08-30 2014-08-19 Configurable clock tree

Publications (2)

Publication Number Publication Date
JP2016529844A true JP2016529844A (ja) 2016-09-23
JP2016529844A5 JP2016529844A5 (https=) 2017-09-07

Family

ID=52583217

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016538970A Ceased JP2016529844A (ja) 2013-08-30 2014-08-19 構成可能なクロックツリー

Country Status (6)

Country Link
US (1) US9825755B2 (https=)
EP (2) EP3039559B1 (https=)
JP (1) JP2016529844A (https=)
KR (1) KR20160048818A (https=)
CN (1) CN105493062B (https=)
WO (1) WO2015031114A1 (https=)

Cited By (1)

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JP2023552731A (ja) * 2020-11-26 2023-12-19 華為技術有限公司 データ送信方法および電子デバイス

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US9841940B2 (en) * 2015-06-05 2017-12-12 Qualcomm Incorporated Power reduction through clock management
GB2542149B (en) * 2015-09-09 2019-11-27 Imagination Tech Ltd Synchronising devices
CN107306137A (zh) * 2016-04-22 2017-10-31 广州致远电子股份有限公司 一种高速采样器
US10698522B2 (en) * 2016-04-27 2020-06-30 Qualcomm Incorporated Variable rate display interfaces
US10084683B2 (en) * 2016-10-20 2018-09-25 Mediatek Inc. Unified protocol device with self functional test and associated method
US10387360B2 (en) * 2017-11-06 2019-08-20 M31 Technology Corporation Integrated circuits adaptable to interchange between clock and data lanes for use in clock forward interface receiver
US11055241B2 (en) * 2017-11-06 2021-07-06 M31 Technology Corporation Integrated circuit having lanes interchangeable between clock and data lanes in clock forward interface receiver
CN108073539A (zh) * 2017-12-27 2018-05-25 上海集成电路研发中心有限公司 一种mipi接口的d-phy电路
TWI754337B (zh) * 2019-08-01 2022-02-01 円星科技股份有限公司 時脈前送介面接收器之中具有可通用於時脈與資料通道之通道的積體電路及實體層
US11599139B1 (en) * 2021-09-03 2023-03-07 Xepic Corporation Limited Dynamic adjustment of root clock frequency in logic system design during verification
CN114116348B (zh) * 2021-11-24 2026-01-27 海光信息技术股份有限公司 一种数据采集方法、数据分析方法和相关设备
US11906585B2 (en) * 2021-12-16 2024-02-20 Samsung Electronics Co., Ltd. Methods and systems for performing built-in-self-test operations without a dedicated clock source

Citations (4)

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Publication number Priority date Publication date Assignee Title
WO1991010951A1 (en) * 1990-01-16 1991-07-25 Cray Research, Inc. Clock distribution system and method
JPH096463A (ja) * 1995-06-07 1997-01-10 Lsi Logic Corp 階層的クロック分配システム及び方法
JP2009512052A (ja) * 2005-10-11 2009-03-19 エヌエックスピー ビー ヴィ クロックスキューの小さいシリアル通信インタフェース
US8205182B1 (en) * 2007-08-22 2012-06-19 Cadence Design Systems, Inc. Automatic synthesis of clock distribution networks

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US5467464A (en) 1993-03-09 1995-11-14 Apple Computer, Inc. Adaptive clock skew and duty cycle compensation for a serial data bus
US8164368B2 (en) * 2005-04-19 2012-04-24 Micron Technology, Inc. Power savings mode for memory systems
US8081706B2 (en) 2005-08-24 2011-12-20 Altera Corporation Lane-to-lane skew reduction in multi-channel, high-speed, transceiver circuitry
US7978802B1 (en) 2007-10-12 2011-07-12 Xilinx, Inc. Method and apparatus for a mesochronous transmission system
US8467486B2 (en) * 2007-12-14 2013-06-18 Mosaid Technologies Incorporated Memory controller with flexible data alignment to clock
US8605224B2 (en) * 2008-02-27 2013-12-10 Silicon Laboratories Inc. Digital interface for tuner-demodulator communications
CN101533420A (zh) * 2008-03-11 2009-09-16 矽统科技股份有限公司 时钟树状结构中路径时间延迟量的平衡方法
US8073090B2 (en) * 2008-07-11 2011-12-06 Integrated Device Technology, Inc. Synchronous de-skew with programmable latency for multi-lane high speed serial interface
US7746142B2 (en) 2008-10-13 2010-06-29 Taiwan Semiconductor Manufacturing Company, Ltd. Circuit and method for clock skew compensation in voltage scaling
US8130019B1 (en) * 2008-10-15 2012-03-06 Octasic Inc. Clock signal propagation method for integrated circuits (ICs) and integrated circuit making use of same
EP2393845B1 (en) * 2009-02-04 2017-07-12 Rhodia Operations Method for modifying the properties of an aqueous suspension
US8411703B1 (en) 2009-07-30 2013-04-02 Xilinx, Inc. Method and apparatus for a reduced lane-lane skew, low-latency transmission system
US8258837B2 (en) * 2009-12-17 2012-09-04 Intel Corporation Controlled clock phase generation
JP5568057B2 (ja) * 2011-05-30 2014-08-06 株式会社東芝 メモリアクセス回路及びメモリシステム
US9143121B2 (en) 2012-08-29 2015-09-22 Qualcomm Incorporated System and method of adjusting a clock signal

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991010951A1 (en) * 1990-01-16 1991-07-25 Cray Research, Inc. Clock distribution system and method
JPH096463A (ja) * 1995-06-07 1997-01-10 Lsi Logic Corp 階層的クロック分配システム及び方法
JP2009512052A (ja) * 2005-10-11 2009-03-19 エヌエックスピー ビー ヴィ クロックスキューの小さいシリアル通信インタフェース
US8205182B1 (en) * 2007-08-22 2012-06-19 Cadence Design Systems, Inc. Automatic synthesis of clock distribution networks

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2023552731A (ja) * 2020-11-26 2023-12-19 華為技術有限公司 データ送信方法および電子デバイス
JP7637775B2 (ja) 2020-11-26 2025-02-28 華為技術有限公司 データ送信方法および電子デバイス

Also Published As

Publication number Publication date
US20150063377A1 (en) 2015-03-05
EP3273359A1 (en) 2018-01-24
EP3039559B1 (en) 2017-09-20
US9825755B2 (en) 2017-11-21
KR20160048818A (ko) 2016-05-04
WO2015031114A1 (en) 2015-03-05
EP3039559A1 (en) 2016-07-06
CN105493062B (zh) 2018-08-21
EP3273359B1 (en) 2020-01-15
CN105493062A (zh) 2016-04-13

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