JP2016527630A5 - - Google Patents

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Publication number
JP2016527630A5
JP2016527630A5 JP2016527135A JP2016527135A JP2016527630A5 JP 2016527630 A5 JP2016527630 A5 JP 2016527630A5 JP 2016527135 A JP2016527135 A JP 2016527135A JP 2016527135 A JP2016527135 A JP 2016527135A JP 2016527630 A5 JP2016527630 A5 JP 2016527630A5
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JP
Japan
Prior art keywords
idle state
power consumption
consumption level
total power
current total
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JP2016527135A
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English (en)
Japanese (ja)
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JP6591971B2 (ja
JP2016527630A (ja
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Priority claimed from US13/945,181 external-priority patent/US9430014B2/en
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Publication of JP2016527630A publication Critical patent/JP2016527630A/ja
Publication of JP2016527630A5 publication Critical patent/JP2016527630A5/ja
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JP2016527135A 2013-07-18 2014-07-18 チップ上のマルチプロセッサシステムにおけるアイドル状態最適化のためのシステムおよび方法 Active JP6591971B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/945,181 US9430014B2 (en) 2013-07-18 2013-07-18 System and method for idle state optimization in a multi-processor system on a chip
US13/945,181 2013-07-18
PCT/US2014/047231 WO2015010044A1 (en) 2013-07-18 2014-07-18 System and method for idle state optimization in a multi-processor system on a chip

Publications (3)

Publication Number Publication Date
JP2016527630A JP2016527630A (ja) 2016-09-08
JP2016527630A5 true JP2016527630A5 (enExample) 2017-08-17
JP6591971B2 JP6591971B2 (ja) 2019-10-16

Family

ID=51399756

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016527135A Active JP6591971B2 (ja) 2013-07-18 2014-07-18 チップ上のマルチプロセッサシステムにおけるアイドル状態最適化のためのシステムおよび方法

Country Status (5)

Country Link
US (1) US9430014B2 (enExample)
EP (1) EP3022627B1 (enExample)
JP (1) JP6591971B2 (enExample)
CN (1) CN105378590B (enExample)
WO (1) WO2015010044A1 (enExample)

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US20160091957A1 (en) * 2014-09-26 2016-03-31 Suketu R. Partiwala Power management for memory accesses in a system-on-chip
KR102325453B1 (ko) * 2014-12-04 2021-11-11 삼성전자주식회사 반도체 장치의 동작 방법
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US11844188B2 (en) * 2021-12-13 2023-12-12 Dell Products, L.P. Distribution of available power to devices in a group
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