JP2015513336A5 - - Google Patents

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Publication number
JP2015513336A5
JP2015513336A5 JP2014555788A JP2014555788A JP2015513336A5 JP 2015513336 A5 JP2015513336 A5 JP 2015513336A5 JP 2014555788 A JP2014555788 A JP 2014555788A JP 2014555788 A JP2014555788 A JP 2014555788A JP 2015513336 A5 JP2015513336 A5 JP 2015513336A5
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JP
Japan
Prior art keywords
processor
token
low power
power mode
controller
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JP2014555788A
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English (en)
Japanese (ja)
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JP2015513336A (ja
JP6125539B2 (ja
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Priority claimed from US13/363,949 external-priority patent/US8775838B2/en
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Publication of JP2015513336A5 publication Critical patent/JP2015513336A5/ja
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Publication of JP6125539B2 publication Critical patent/JP6125539B2/ja
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JP2014555788A 2012-02-01 2013-02-01 リアルタイムシステムにおける動的電力管理 Active JP6125539B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/363,949 US8775838B2 (en) 2012-02-01 2012-02-01 Limiting the number of unexpected wakeups in a computer system implementing a power-saving preemptive wakeup method from historical data
US13/363,949 2012-02-01
PCT/US2013/024474 WO2013116751A1 (en) 2012-02-01 2013-02-01 Dynamic power management in real-time systems

Publications (3)

Publication Number Publication Date
JP2015513336A JP2015513336A (ja) 2015-05-07
JP2015513336A5 true JP2015513336A5 (enExample) 2016-03-17
JP6125539B2 JP6125539B2 (ja) 2017-05-10

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JP2014555788A Active JP6125539B2 (ja) 2012-02-01 2013-02-01 リアルタイムシステムにおける動的電力管理

Country Status (4)

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US (1) US8775838B2 (enExample)
JP (1) JP6125539B2 (enExample)
CN (1) CN104094191B (enExample)
WO (1) WO2013116751A1 (enExample)

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