JP2016197678A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2016197678A
JP2016197678A JP2015077490A JP2015077490A JP2016197678A JP 2016197678 A JP2016197678 A JP 2016197678A JP 2015077490 A JP2015077490 A JP 2015077490A JP 2015077490 A JP2015077490 A JP 2015077490A JP 2016197678 A JP2016197678 A JP 2016197678A
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layer
igbt
diode
semiconductor device
semiconductor substrate
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JP6335829B2 (en
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敦司 楢崎
Atsushi Narasaki
敦司 楢崎
真也 曽根田
Shinya Soneda
真也 曽根田
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to US14/990,092 priority patent/US9799648B2/en
Priority to KR1020160035082A priority patent/KR101808411B1/en
Priority to DE102016205111.3A priority patent/DE102016205111B4/en
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which has improved diode recovery characteristics and in which an IGBT and a diode are formed in one semiconductor substrate.SOLUTION: A semiconductor device (RC-IGBT301) comprises: an IGBT including an emitter layer on a first principal surface side of a semiconductor substrate and a collector layer on a second principal surface side of the semiconductor substrate; a reflux diode including an anode layer 310 on the first principal surface side of the semiconductor substrate and a cathode layer on the second principal surface side of the semiconductor substrate; a well region 304 provided in the boundary between the IGBT and the reflux diode and for separating the IGBT and the reflux diode; a first electrode formed on a first principal surface of the semiconductor substrate so as to connect to the emitter layer, the anode layer, and the well region 304; a resistor 351 provided between the well region 304 and the first electrode; and a second electrode formed on a second principal surface of the semiconductor substrate so as to connect to the collector layer and the cathode layer.SELECTED DRAWING: Figure 1

Description

本発明は半導体装置に関し、特に還流ダイオードを内蔵した絶縁ゲート型バイポーラトランジスタに関する。   The present invention relates to a semiconductor device, and more particularly to an insulated gate bipolar transistor having a built-in free wheel diode.

電力用半導体素子であるパワーデバイスは、家電製品や電気自動車、鉄道といった分野から、「再生可能エネルギー」として注目が高まっている太陽光発電や風力発電の分野まで幅広く用いられている。これらの分野では、パワーデバイスでインバータ回路を構築し、誘導モータなどの誘導性負荷を駆動する場合が多い。その場合、誘導性負荷の逆起電力により生じる電流を還流させる為の還流ダイオード（以下、単にダイオードと表記）が必要であり、通常のインバータ回路は、絶縁ゲート型バイポーラトランジスタ（以下、ＩＧＢＴと表記）とダイオードを複数個用いて構成される。しかし、インバータ装置は、小型軽量化および低コスト化が強く望まれており、複数個の半導体素子を搭載する事は望ましくない。そこで、その解決方法の一つとして、ＩＧＢＴとダイオードを同一のチップに形成した逆導通型ＩＧＢＴ（以下、ＲＣ−ＩＧＢＴと表記）の開発が進められている（例えば特許文献１、２を参照）。これにより、半導体素子の搭載面積縮小や低コスト化が望める。   Power devices, which are power semiconductor elements, are widely used in fields such as home appliances, electric vehicles, and railways, and in the fields of solar power generation and wind power generation that are attracting attention as “renewable energy”. In these fields, an inverter circuit is often constructed with a power device to drive an inductive load such as an induction motor. In that case, a free-wheeling diode (hereinafter simply referred to as a diode) is required to recirculate the current generated by the back electromotive force of the inductive load, and an ordinary inverter circuit is an insulated gate bipolar transistor (hereinafter referred to as IGBT). ) And a plurality of diodes. However, the inverter device is strongly desired to be reduced in size, weight and cost, and it is not desirable to mount a plurality of semiconductor elements. Thus, as one of the solutions, development of a reverse conduction type IGBT (hereinafter referred to as RC-IGBT) in which an IGBT and a diode are formed on the same chip is underway (see, for example, Patent Documents 1 and 2). . As a result, it is possible to reduce the mounting area and cost of the semiconductor element.

特開２００８−５３６４８号公報JP 2008-53648 A 特開２００８−１０３５９０号公報JP 2008-103590 A

ＲＣ−ＩＧＢＴは、ＩＧＢＴとダイオードが１つの半導体基板内に形成されているが、低コスト化を実現する為に、両素子を個別にではなく同時に形成していく必要がある。一般的に、ＩＧＢＴのエミッタ電極の直下には、アノード拡散層の最表面不純物濃度を高くする必要がある。しかしながら、その背反事項としてダイオードのリカバリ特性が悪化する為、表面不純物濃度は十分に高く設定出来ない問題があった。   In the RC-IGBT, the IGBT and the diode are formed in one semiconductor substrate. However, in order to reduce the cost, it is necessary to form both elements simultaneously instead of individually. Generally, it is necessary to increase the outermost surface impurity concentration of the anode diffusion layer immediately below the IGBT emitter electrode. However, there is a problem that the surface impurity concentration cannot be set sufficiently high because the recovery characteristic of the diode deteriorates as a contradiction.

本発明は以上のような課題を解決するためになされたものであり、ＩＧＢＴとダイオードを１つの半導体基板内に形成した半導体装置において、ダイオードのリカバリ特性を向上させた半導体装置の提供を目的とする。   The present invention has been made in order to solve the above-described problems, and an object of the present invention is to provide a semiconductor device in which the recovery characteristics of the diode are improved in a semiconductor device in which the IGBT and the diode are formed in one semiconductor substrate. To do.

本発明に係る半導体装置は、半導体基板の第１主面側にエミッタ層、半導体基板の第２主面側にコレクタ層を備える絶縁ゲート型バイポーラトランジスタと、半導体基板の第１主面側にアノード層、半導体基板の第２主面側にカソード層を備える還流ダイオードと、絶縁ゲート型バイポーラトランジスタと還流ダイオードとの境界に設けられ、絶縁ゲート型バイポーラトランジスタと還流ダイオードとを分離するウェル領域と、エミッタ層、アノード層およびウェル領域に接続するように半導体基板の第１主面に形成された第１電極と、ウェル領域と第１電極との間に設けられる抵抗体と、コレクタ層およびカソード層に接続するように半導体基板の第２主面に形成された第２電極と、を備える。   The semiconductor device according to the present invention includes an insulated gate bipolar transistor having an emitter layer on the first main surface side of the semiconductor substrate and a collector layer on the second main surface side of the semiconductor substrate, and an anode on the first main surface side of the semiconductor substrate. A reflux diode having a cathode layer on the second main surface side of the semiconductor substrate, a well region provided at a boundary between the insulated gate bipolar transistor and the reflux diode, and separating the insulated gate bipolar transistor and the reflux diode; A first electrode formed on the first main surface of the semiconductor substrate so as to be connected to the emitter layer, the anode layer, and the well region, a resistor provided between the well region and the first electrode, a collector layer, and a cathode layer And a second electrode formed on the second main surface of the semiconductor substrate so as to be connected to the semiconductor substrate.

本発明に係る半導体装置は、還流ダイオードと絶縁ゲート型バイポーラトランジスタとを分離するウェル領域において、ウェルと第１電極との間に抵抗体を設ける。抵抗体を設けることにより、還流ダイオードがオン状態の際にウェル領域からのホール注入が抑制される。これにより、還流ダイオードがオフした時の逆回復電流が抑制される。よって、同一基板上に還流ダイオードと絶縁ゲート型バイポーラトランジスタとを形成した半導体装置において、リカバリ特性を向上させることが可能となる。   In the semiconductor device according to the present invention, a resistor is provided between the well and the first electrode in the well region that separates the free wheel diode and the insulated gate bipolar transistor. By providing the resistor, hole injection from the well region is suppressed when the free-wheeling diode is on. Thereby, the reverse recovery current when the return diode is turned off is suppressed. Therefore, recovery characteristics can be improved in a semiconductor device in which a free wheel diode and an insulated gate bipolar transistor are formed on the same substrate.

本発明の実施形態に係る半導体装置の平面図である。1 is a plan view of a semiconductor device according to an embodiment of the present invention. 本発明の実施形態に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on embodiment of this invention. 図１中の領域Ｌを拡大した平面図である。It is the top view to which the area | region L in FIG. 1 was expanded. 本発明の実施形態の第１変形例に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on the 1st modification of embodiment of this invention. 本発明の実施形態の第２変形例に係る半導体装置の平面図である。It is a top view of the semiconductor device concerning the 2nd modification of an embodiment of the present invention. 本発明の実施形態の第３変形例に係る半導体装置の平面図である。It is a top view of the semiconductor device concerning the 3rd modification of an embodiment of the present invention. 前提技術に係る半導体装置の平面図である。It is a top view of the semiconductor device concerning a base technology. 前提技術に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on a premise technique. 図４中の領域Ｃを拡大した平面図である。It is the top view to which the area | region C in FIG. 4 was expanded. ダイオードの逆回復時の電流波形を示す図である。It is a figure which shows the electric current waveform at the time of reverse recovery of a diode.

＜前提技術＞
本発明の実施形態を説明する前に、本発明の前提となる技術について説明する。図７は、前提技術における半導体装置（即ち、ＲＣ−ＩＧＢＴ１０１）の平面図である。図８は、図７中のダイオード１０２の領域とＩＧＢＴ１０３の領域にまたがる線分Ａ−Ｂにおける断面図である。図９は、図７中の領域Ｃを拡大した平面図である。 <Prerequisite technology>
Prior to describing the embodiments of the present invention, the technology that is the premise of the present invention will be described. FIG. 7 is a plan view of a semiconductor device (that is, RC-IGBT 101) in the base technology. FIG. 8 is a cross-sectional view taken along line A-B across the region of diode 102 and the region of IGBT 103 in FIG. FIG. 9 is an enlarged plan view of a region C in FIG.

図７に示すように、ＲＣ−ＩＧＢＴ１０１には、ダイオード１０２とＩＧＢＴ１０３が設けられている。ダイオード１０２とＩＧＢＴ１０３との間には、ウェル領域１０４が設けられる。ウェル領域１０４には、ダイオード１０２とＩＧＢＴ１０３とを分離するためのｐウェル１０９が設けられる。ＲＣ−ＩＧＢＴ１０１はさらに、ゲートパッド領域１０５、終端領域１０６、耐圧保持領域１０７を備える。   As shown in FIG. 7, the RC-IGBT 101 is provided with a diode 102 and an IGBT 103. A well region 104 is provided between the diode 102 and the IGBT 103. In the well region 104, a p-well 109 for separating the diode 102 and the IGBT 103 is provided. The RC-IGBT 101 further includes a gate pad region 105, a termination region 106, and a breakdown voltage holding region 107.

図８に示すように、半導体基板には、ダイオード１０２とＩＧＢＴ１０３とに共通のｎ−ドリフト層１０８が形成される。ｎ−ドリフト層１０８の上面側において、ダイオード１０２とＩＧＢＴ１０３とを分離するようにｐウェル１０９が形成される。また、ダイオード１０２において、ｐアノード層１１０を貫通するようにトレンチ１１１が形成されている。   As shown in FIG. 8, an n − drift layer 108 common to the diode 102 and the IGBT 103 is formed on the semiconductor substrate. On the upper surface side of n − drift layer 108, p well 109 is formed so as to separate diode 102 and IGBT 103. In the diode 102, a trench 111 is formed so as to penetrate the p anode layer 110.

トレンチ１１１内壁には酸化膜１１２を介して導電性のポリシリコン１１３が埋め込まれている。このトレンチ１１１には耐圧特性を安定させる効果がある。なお、トレンチ１１１が形成されない従来例もある。   Conductive polysilicon 113 is buried in the inner wall of the trench 111 through an oxide film 112. The trench 111 has an effect of stabilizing the breakdown voltage characteristic. There is a conventional example in which the trench 111 is not formed.

ＩＧＢＴ１０３には、ｎ−ドリフト層１０８の上面側においてｐベース層１１４が形成される。ｐベース層１１４の上面にｎ＋エミッタ層１１５およびｐ＋コンタクト層１１６が形成される。ｎ＋エミッタ層１１５とｐベース層１１４を貫通するようにトレンチ１１７が形成されている。   In the IGBT 103, a p base layer 114 is formed on the upper surface side of the n − drift layer 108. An n + emitter layer 115 and a p + contact layer 116 are formed on the upper surface of the p base layer 114. A trench 117 is formed so as to penetrate the n + emitter layer 115 and the p base layer 114.

トレンチ１１７内壁にはゲート酸化膜１１８を介して導電性のポリシリコン１１９が埋め込まれており、この導電性のポリシリコン１１９はＩＧＢＴ１０３のゲートとしての機能を有する。   Conductive polysilicon 119 is embedded in the inner wall of the trench 117 through a gate oxide film 118, and this conductive polysilicon 119 has a function as a gate of the IGBT 103.

ダイオード１０２とＩＧＢＴ１０３との境界であるウェル領域１０４は、ダイオード１０２とＩＧＢＴ１０３の電気的動作を分離する機能を有する。ウェル領域１０４には、ｐ型不純物の深い拡散層で形成されたｐウェル１０９が形成されている。また、ｐウェル上の開口部１２０にはｐ＋コンタクト層１２１が形成されている。   A well region 104 which is a boundary between the diode 102 and the IGBT 103 has a function of separating electrical operations of the diode 102 and the IGBT 103. In the well region 104, a p-well 109 formed of a deep diffusion layer of p-type impurities is formed. A p + contact layer 121 is formed in the opening 120 above the p-well.

ダイオード１０２のアノード層１１０およびトレンチ１１１、ＩＧＢＴ１０３のｎ＋エミッタ層１１５、ｐ＋コンタクト層１１６およびトレンチ１１７、ウェル領域１０４のｐウェル１０９は、絶縁膜１２２で覆われている。絶縁膜１２２には開口部１２３，１２４，１２０が設けられている。   The anode layer 110 and the trench 111 of the diode 102, the n + emitter layer 115 of the IGBT 103, the p + contact layer 116 and the trench 117, and the p well 109 of the well region 104 are covered with an insulating film 122. Openings 123, 124, and 120 are provided in the insulating film 122.

ダイオード１０２のアノード層１１０は、開口部１２３を通じてエミッタ電極１２５と接続されている。ＩＧＢＴ１０３のｐベース層１１４、ｎ＋エミッタ層１１５およびｐ＋コンタクト層１１６は、開口部１２４を通じてエミッタ電極１２５と接続されている。また、ｐウェル１０９上面側に形成されたｐ＋コンタクト層１２１は、開口部１２０を通じてエミッタ電極１２５と接続されている。   The anode layer 110 of the diode 102 is connected to the emitter electrode 125 through the opening 123. The p base layer 114, the n + emitter layer 115, and the p + contact layer 116 of the IGBT 103 are connected to the emitter electrode 125 through the opening 124. The p + contact layer 121 formed on the upper surface side of the p well 109 is connected to the emitter electrode 125 through the opening 120.

なお、ダイオード１０２のアノード層１１０とエミッタ電極１２５とのオーミック性を向上させるために、アノード層１１０とエミッタ電極１２５との間にｐ＋コンタクト領域を形成してもよい。また、同様の理由で、アノード層１１０とエミッタ電極１２５との間にバリアメタル層を形成してもよい。また、ＩＧＢＴ１０３のｎ＋エミッタ層１１５およびｐ＋コンタクト層１１６とエミッタ電極１２５との間にバリアメタル層を形成してもよい。   In order to improve the ohmic property between the anode layer 110 and the emitter electrode 125 of the diode 102, a p + contact region may be formed between the anode layer 110 and the emitter electrode 125. For the same reason, a barrier metal layer may be formed between the anode layer 110 and the emitter electrode 125. Further, a barrier metal layer may be formed between the n + emitter layer 115 and the p + contact layer 116 of the IGBT 103 and the emitter electrode 125.

ダイオード１０２の直下であるｎ−ドリフト層１０８の下面側には、ｎバッファ層１２６とｎ＋カソード層１２７が形成されている。ＩＧＢＴ１０３の直下であるｎ−ドリフト層１０８の下面側には、ダイオード１０２と共通層であるｎバッファ層１２６と、ｐ＋コレクタ層１２８が形成されている。   An n buffer layer 126 and an n + cathode layer 127 are formed on the lower surface side of the n − drift layer 108 immediately below the diode 102. An n buffer layer 126 that is a common layer with the diode 102 and a p + collector layer 128 are formed on the lower surface side of the n − drift layer 108 immediately below the IGBT 103.

ｎ＋カソード層１２７とｐ＋コレクタ層１２８は、共通電極であるコレクタ電極１２９と接続されている。ここで、コレクタ電極１２９は金属の相互拡散防止とオーミック性を向上させるため、シリコン側から順に、例えばＴｉ層、Ｎｉ層、Ａｕ層、又はＡｌＳｉ層、Ｔｉ層、Ｎｉ層、Ａｕ層が積層されて形成されている。   The n + cathode layer 127 and the p + collector layer 128 are connected to a collector electrode 129 that is a common electrode. Here, the collector electrode 129 is formed by stacking, for example, a Ti layer, a Ni layer, an Au layer, or an AlSi layer, a Ti layer, a Ni layer, and an Au layer sequentially from the silicon side in order to prevent metal mutual diffusion and improve ohmic properties. Is formed.

次に、図７および図９に示す終端領域１０６を説明する。図９において、便宜上ゲート配線パターンは省略している。図７に示すように、終端領域１０６はダイオード１０２およびＩＧＢＴ１０３の周囲を囲むように形成されている。また、ウェル領域１０４と終端領域１０６とは図７中の領域Ｃにおいて繋がっている。つまり、図９に示すように、ウェル領域１０４のｐウェル１０９が、終端領域１０６のｐウェル１３１と接続された構造となっている。終端領域１０６において、ウェル領域１０４と同様にオーミック性を向上させるためにｐ＋コンタクト層１３３が形成されている。終端領域１０６上にも絶縁膜１２２が形成されており、ｐ＋コンタクト層１３３がエミッタ電極１２５と接続するために開口部１３５が設けられている。終端領域１０６に形成されたｐウェル１３１によって、ダイオード１０２およびＩＧＢＴ１０３は耐圧保持領域１０７と分離されている。   Next, the termination region 106 shown in FIGS. 7 and 9 will be described. In FIG. 9, the gate wiring pattern is omitted for convenience. As shown in FIG. 7, the termination region 106 is formed so as to surround the periphery of the diode 102 and the IGBT 103. Further, the well region 104 and the termination region 106 are connected in a region C in FIG. That is, as shown in FIG. 9, the p-well 109 in the well region 104 is connected to the p-well 131 in the termination region 106. In the termination region 106, a p + contact layer 133 is formed in order to improve the ohmic property like the well region 104. An insulating film 122 is also formed on the termination region 106, and an opening 135 is provided for connecting the p + contact layer 133 to the emitter electrode 125. The diode 102 and the IGBT 103 are separated from the breakdown voltage holding region 107 by the p well 131 formed in the termination region 106.

ここで、ダイオードのリカバリ特性について簡単に説明する。図１０は、ダイオードをオン状態からオフ状態に切り替えた場合の逆回復時の電流波形を示す図である。ダイオードがオン状態からオフ状態になる際には、ｎ＋カソード層からｐアノード層に向かって逆方向電流が流れる。この逆方向電流のピーク値をリカバリ電流（Ｉｒｒ）と呼ぶ。この電流がエネルギーロスになるため、リカバリ電流は小さい事が要求される。   Here, the recovery characteristics of the diode will be briefly described. FIG. 10 is a diagram showing a current waveform at the time of reverse recovery when the diode is switched from the on state to the off state. When the diode changes from the on state to the off state, a reverse current flows from the n + cathode layer toward the p anode layer. This peak value of the reverse current is called a recovery current (Irr). Since this current causes energy loss, the recovery current is required to be small.

リカバリ電流を低減する手法として、ｐアノード層の不純物濃度を下げることが一般的であるが、同時にオーミック性の低下やキャリア注入効率の低下を引き起こすことで、順方向電圧Ｖｆが高くなる問題がある。   As a technique for reducing the recovery current, it is common to lower the impurity concentration of the p anode layer, but at the same time, there is a problem that the forward voltage Vf is increased by causing a decrease in ohmic property and a decrease in carrier injection efficiency. .

また、前提技術において、ダイオード１０２とＩＧＢＴ１０３とを分離する深いｐウェル１０９はダイオードのアノード層としても機能するため、この領域によってリカバリ損失が増加するという問題があった。以下で説明する本発明の実施形態は以上の問題を解決する。   Further, in the base technology, the deep p-well 109 that separates the diode 102 and the IGBT 103 also functions as an anode layer of the diode, so that there is a problem that recovery loss increases due to this region. The embodiments of the present invention described below solve the above problems.

＜本発明の実施形態＞
図１は、本発明の実施形態における半導体装置（即ち、ＲＣ−ＩＧＢＴ３０１）の平面図である。図２は、図１中のダイオード３０２の領域とＩＧＢＴ３０３の領域にまたがる線分Ｊ−Ｋにおける断面図である。図３は、図１中の領域Ｌを拡大した平面図である。図２において、基板の上面を第１主面、下面を第２主面とする。 <Embodiment of the present invention>
FIG. 1 is a plan view of a semiconductor device (that is, RC-IGBT 301) in an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line JK that spans the region of diode 302 and the region of IGBT 303 in FIG. FIG. 3 is an enlarged plan view of a region L in FIG. In FIG. 2, the upper surface of the substrate is the first main surface and the lower surface is the second main surface.

図１に示すように、ＲＣ−ＩＧＢＴ３０１は、ダイオード３０２とＩＧＢＴ３０３が設けられている。ダイオード３０２とＩＧＢＴ３０３との間には、ウェル領域３０４が設けられる。ウェル領域３０４には、ダイオード３０２とＩＧＢＴ３０３とを分離するためのｐウェル３０９が設けられる。ＲＣ−ＩＧＢＴ３０１はさらに、ゲートパッド領域３０５、終端領域３０６、耐圧保持領域３０７を備える。   As shown in FIG. 1, the RC-IGBT 301 is provided with a diode 302 and an IGBT 303. A well region 304 is provided between the diode 302 and the IGBT 303. The well region 304 is provided with a p-well 309 for separating the diode 302 and the IGBT 303. The RC-IGBT 301 further includes a gate pad region 305, a termination region 306, and a breakdown voltage holding region 307.

図２に示すように、半導体基板には、ダイオード３０２とＩＧＢＴ３０３とに共通のｎ−ドリフト層３０８が形成される。ｎ−ドリフト層３０８の上面側において、ダイオード３０２とＩＧＢＴ３０３とを分離するようにｐウェル３０９が形成される。また、ダイオード３０２において、ｐアノード層３１０を貫通するようにトレンチ３１１が形成されている。   As shown in FIG. 2, an n − drift layer 308 common to the diode 302 and the IGBT 303 is formed on the semiconductor substrate. On the upper surface side of n − drift layer 308, p well 309 is formed so as to separate diode 302 and IGBT 303. In the diode 302, a trench 311 is formed so as to penetrate the p anode layer 310.

トレンチ３１１内壁には酸化膜３１２を介して導電性のポリシリコン３１３が埋め込まれている。このトレンチ３１１には耐圧特性を安定させる効果がある。   Conductive polysilicon 313 is embedded in the inner wall of the trench 311 via an oxide film 312. The trench 311 has an effect of stabilizing the breakdown voltage characteristic.

ＩＧＢＴ３０３において、ｎ−ドリフト層３０８の上面側においてｐベース層３１４が形成される。ｐベース層３１４の上面にｎ＋エミッタ層３１５およびｐ＋コンタクト層３１６が形成される。ｎ＋エミッタ層３１５とｐベース層３１４を貫通するようにトレンチ３１７が形成されている。   In IGBT 303, p base layer 314 is formed on the upper surface side of n − drift layer 308. An n + emitter layer 315 and a p + contact layer 316 are formed on the upper surface of the p base layer 314. A trench 317 is formed so as to penetrate the n + emitter layer 315 and the p base layer 314.

トレンチ３１７内壁にはゲート酸化膜３１８を介して導電性のポリシリコン３１９が埋め込まれており、この導電性のポリシリコン３１９はＩＧＢＴ３０３のゲートとしての機能を有する。   Conductive polysilicon 319 is buried in the inner wall of the trench 317 through a gate oxide film 318, and the conductive polysilicon 319 has a function as a gate of the IGBT 303.

ダイオード３０２とＩＧＢＴ３０３との境界であるウェル領域３０４は、ダイオード３０２とＩＧＢＴ３０３の電気的動作を分離する機能を有する。ウェル領域３０４には、ｐ型不純物の深い拡散層で形成されたｐウェル３０９が形成されている。ｐウェル３０９上には導電性のポリシリコンで形成された抵抗体３５１が配置されている。ｐウェル３０９と抵抗体３５１とは電気的に接続している。   A well region 304 that is a boundary between the diode 302 and the IGBT 303 has a function of separating electrical operations of the diode 302 and the IGBT 303. In the well region 304, a p-well 309 formed of a deep diffusion layer of p-type impurities is formed. A resistor 351 made of conductive polysilicon is disposed on the p well 309. The p well 309 and the resistor 351 are electrically connected.

ダイオード３０２のアノード層３１０およびトレンチ３１１、ＩＧＢＴ３０３のｎ＋エミッタ層３１５、ｐ＋コンタクト層３１６およびトレンチ３１７、ウェル領域３０４のｐウェル３０９は、絶縁膜３２２で覆われている。絶縁膜３２２には開口部３２３，３２４，３２０が設けられている。   The anode layer 310 and the trench 311 of the diode 302, the n + emitter layer 315 of the IGBT 303, the p + contact layer 316 and the trench 317, and the p well 309 of the well region 304 are covered with an insulating film 322. Openings 323, 324, and 320 are provided in the insulating film 322.

ダイオード３０２のアノード層３１０は、開口部３２３を通じてエミッタ電極３２５と接続されている。ＩＧＢＴ３０３のｐベース層３１４、ｎ＋エミッタ層３１５およびｐ＋コンタクト層３１６は、開口部３２４を通じてエミッタ電極３２５と接続されている。また、ｐウェル３０９上面側に形成された抵抗体３５１は、開口部３２０を通じてエミッタ電極３２５と接続されている。図３に示すように、開口部３２０は連続的なスリット形状である。   The anode layer 310 of the diode 302 is connected to the emitter electrode 325 through the opening 323. The p base layer 314, the n + emitter layer 315, and the p + contact layer 316 of the IGBT 303 are connected to the emitter electrode 325 through the opening 324. The resistor 351 formed on the upper surface side of the p well 309 is connected to the emitter electrode 325 through the opening 320. As shown in FIG. 3, the opening 320 has a continuous slit shape.

なお、ダイオード３０２のアノード層３１０とエミッタ電極３２５とのオーミック性を向上させるために、アノード層３１０とエミッタ電極３２５との間にｐ＋コンタクト領域を形成してもよい。また、同様の理由で、アノード層３１０とエミッタ電極３２５との間にＴｉＮ等でバリアメタル層を形成してもよい。また、ＩＧＢＴ３０３のｎ＋エミッタ層３１５およびｐ＋コンタクト層３１６とエミッタ電極３２５との間にもＴｉＮ等でバリアメタル層を形成してもよい。   Note that a p + contact region may be formed between the anode layer 310 and the emitter electrode 325 in order to improve the ohmic property between the anode layer 310 and the emitter electrode 325 of the diode 302. For the same reason, a barrier metal layer may be formed of TiN or the like between the anode layer 310 and the emitter electrode 325. Further, a barrier metal layer may be formed of TiN or the like between the n + emitter layer 315 and the p + contact layer 316 of the IGBT 303 and the emitter electrode 325.

ダイオード３０２の直下であるｎ−ドリフト層３０８の下面側には、ｎバッファ層３２６とｎ＋カソード層３２７が形成されている。ＩＧＢＴ３０３の直下であるｎ−ドリフト層３０８の下面側には、ダイオード３０２と共通層であるｎバッファ層３２６と、ｐ＋コレクタ層３２８が形成されている。   An n buffer layer 326 and an n + cathode layer 327 are formed on the lower surface side of the n − drift layer 308 immediately below the diode 302. An n buffer layer 326 that is a common layer with the diode 302 and a p + collector layer 328 are formed on the lower surface side of the n − drift layer 308 that is directly under the IGBT 303.

ｎ＋カソード層３２７とｐ＋コレクタ層３２８は、共通電極であるコレクタ電極３２９と接続されている。ここで、コレクタ電極３２９は金属の相互拡散防止とオーミック性を向上させるため、シリコン側から順に、例えばＴｉ層、Ｎｉ層、Ａｕ層、又はＡｌＳｉ層、Ｔｉ層、Ｎｉ層、Ａｕ層が積層されて形成されている。   The n + cathode layer 327 and the p + collector layer 328 are connected to a collector electrode 329 that is a common electrode. Here, the collector electrode 329 is formed by stacking, for example, a Ti layer, a Ni layer, an Au layer, or an AlSi layer, a Ti layer, a Ni layer, and an Au layer sequentially from the silicon side in order to prevent metal mutual diffusion and improve ohmic properties. Is formed.

次に、図１および図３に示す終端領域１０６を説明する。図３において、便宜上ゲート配線パターンは省略している。図３に示すように、終端領域３０６はダイオード３０２およびＩＧＢＴ３０３の周囲を囲むように形成されている。また、ウェル領域３０４と終端領域３０６とは図１中の領域Ｌにおいて繋がっている。つまり、図３に示すように、ウェル領域３０４のｐウェル３０９が、終端領域３０６のｐウェル３３１と接続された構造となっている。終端領域３０６において、オーミック性を向上させるためにｐ＋コンタクト層３３３が形成されている。終端領域３０６上にも絶縁膜３２２が形成されており、ｐ＋コンタクト層３３３がエミッタ電極３２５と接続するために開口部３３５が設けられている。終端領域３０６に形成されたｐウェル３３１によって、ダイオード３０２およびＩＧＢＴ３０３は耐圧保持領域３０７と分離されている。   Next, the termination region 106 shown in FIGS. 1 and 3 will be described. In FIG. 3, the gate wiring pattern is omitted for convenience. As shown in FIG. 3, the termination region 306 is formed so as to surround the periphery of the diode 302 and the IGBT 303. Further, the well region 304 and the termination region 306 are connected in a region L in FIG. That is, as shown in FIG. 3, the p-well 309 in the well region 304 is connected to the p-well 331 in the termination region 306. In the termination region 306, a p + contact layer 333 is formed to improve ohmic properties. An insulating film 322 is also formed on the termination region 306, and an opening 335 is provided for connecting the p + contact layer 333 to the emitter electrode 325. The diode 302 and the IGBT 303 are separated from the breakdown voltage holding region 307 by the p-well 331 formed in the termination region 306.

なお、本実施形態においてダイオード３０２がトレンチ構造を有しているが、トレンチを有しないプレーナダイオードにおいても同様の効果を奏す。   In the present embodiment, the diode 302 has a trench structure, but the same effect can be obtained in a planar diode having no trench.

また、本実施形態におけるＩＧＢＴ３０３はキャリアストア層を有していないが、キャリアストアを有する電荷蓄積型トレンチゲートバイポーラトランジスタでも同様の効果を奏す。また、本実施形態におけるＩＧＢＴ３０３は電子注入促進型であっても同様の効果を奏す。なお、本実施形態においてＩＧＢＴ３０３はｐ＋コンタクト層３１６を有しているが、ｐ＋コンタクト層３１６が無くても同様の効果を奏す。   Moreover, although the IGBT 303 in this embodiment does not have a carrier store layer, the same effect can be obtained by a charge storage type trench gate bipolar transistor having a carrier store. Further, the IGBT 303 in this embodiment has the same effect even if it is an electron injection promoting type. In the present embodiment, the IGBT 303 has the p + contact layer 316, but the same effect can be obtained without the p + contact layer 316.

また、本実施形態では抵抗体３５１として導電性のポリシリコンを用いたが、チタン（Ｔｉ）、コバルト（Ｃｏ）などの金属でも同様の効果を奏す。   In the present embodiment, conductive polysilicon is used as the resistor 351, but the same effect can be obtained with a metal such as titanium (Ti) or cobalt (Co).

また、本実施形態では、ｎバッファ層３２６を有しているパンチスルー型ＩＧＢＴで説明したが、ｎバッファ層３２６を有しないノンパンチスルー型ＩＧＢＴでも同様の効果を奏す。   In this embodiment, the punch-through IGBT having the n buffer layer 326 has been described. However, a non-punch through IGBT having no n buffer layer 326 has the same effect.

＜効果＞
本発明の実施形態における半導体装置（ＲＣ-ＩＧＢＴ３０１）は、半導体基板の第１主面側にエミッタ層（ｎ＋エミッタ層３１５）、半導体基板の第２主面側にコレクタ層（ｐ＋コレクタ層３２８）を備える絶縁ゲート型バイポーラトランジスタ（ＩＧＢＴ３０３）と、半導体基板の第１主面側にアノード層３１０、半導体基板の第２主面側にカソード層（ｎ＋カソード層３２７）を備える還流ダイオード（ダイオード３０２）と、絶縁ゲート型バイポーラトランジスタと還流ダイオードとの境界に設けられ、絶縁ゲート型バイポーラトランジスタと還流ダイオードとを分離するウェル領域３０４と、エミッタ層、アノード層およびウェル領域３０４に接続するように半導体基板の第１主面に形成された第１電極（エミッタ電極３２５）と、ウェル領域３０４と第１電極との間に設けられる抵抗体３５１と、コレクタ層およびカソード層に接続するように半導体基板の第２主面に形成された第２電極（コレクタ電極３２９）と、を備える。 <Effect>
The semiconductor device (RC-IGBT 301) in the embodiment of the present invention has an emitter layer (n + emitter layer 315) on the first main surface side of the semiconductor substrate and a collector layer (p + collector layer 328) on the second main surface side of the semiconductor substrate. And a free-wheeling diode (diode 302) including an anode layer 310 on the first main surface side of the semiconductor substrate and a cathode layer (n + cathode layer 327) on the second main surface side of the semiconductor substrate. A well region 304 that is provided at a boundary between the insulated gate bipolar transistor and the freewheeling diode, and separates the insulated gate bipolar transistor and the freewheel diode, and is connected to the emitter layer, the anode layer, and the well region 304. A first electrode (emitter electrode 325) formed on the first main surface of A resistor 351 provided between the well region 304 and the first electrode, and a second electrode (collector electrode 329) formed on the second main surface of the semiconductor substrate so as to be connected to the collector layer and the cathode layer. Prepare.

本実施形態における半導体装置（ＲＣ-ＩＧＢＴ３０１）は、ダイオード３０２とＩＧＢＴ３０３とを分離するウェル領域３０４において、ｐウェル３０９とエミッタ電極３２５との間に抵抗体３５１を設ける。抵抗体３５１を設けることにより、ダイオード３０２がオン状態の際にｐウェル３０９からのホール注入が抑制される。これにより、ダイオード３０２がオフした時の逆回復電流が抑制される。よって、同一基板上にダイオード３０２とＩＧＢＴ３０３とを形成したＲＣ-ＩＧＢＴ３０１において、リカバリ特性を向上させることが可能となる。   In the semiconductor device (RC-IGBT 301) in this embodiment, a resistor 351 is provided between the p well 309 and the emitter electrode 325 in the well region 304 that separates the diode 302 and the IGBT 303. By providing the resistor 351, hole injection from the p-well 309 is suppressed when the diode 302 is on. Thereby, the reverse recovery current when the diode 302 is turned off is suppressed. Therefore, recovery characteristics can be improved in the RC-IGBT 301 in which the diode 302 and the IGBT 303 are formed on the same substrate.

また、本実施形態における半導体装置（ＲＣ-ＩＧＢＴ３０１）において、抵抗体３５１はポリシリコンである。   In the semiconductor device (RC-IGBT 301) in the present embodiment, the resistor 351 is polysilicon.

従って、ＩＧＢＴ３０３のゲート電極としてポリシリコンを用いているため、抵抗体３５１として同じ材料であるポリシリコンを用いることで、製造工程の複雑化を抑制することが可能である。また、ポリシリコンは電極材料として普及しているため製造コストの増大を抑制することが可能である。   Therefore, since polysilicon is used as the gate electrode of the IGBT 303, the use of polysilicon which is the same material as the resistor 351 can suppress the complexity of the manufacturing process. Further, since polysilicon is widely used as an electrode material, it is possible to suppress an increase in manufacturing cost.

また、本実施形態における半導体装置（ＲＣ-ＩＧＢＴ３０１）において、抵抗体３５１はチタンを含んでもよい。従って、抵抗体３５１をポリシリコンの代わりにチタンで形成しても同様の効果を得ることが可能である。   In the semiconductor device (RC-IGBT 301) in this embodiment, the resistor 351 may include titanium. Therefore, the same effect can be obtained even when the resistor 351 is formed of titanium instead of polysilicon.

また、本実施形態における半導体装置（ＲＣ-ＩＧＢＴ３０１）において、抵抗体３５１はコバルトを含んでもよい。従って、抵抗体３５１をポリシリコンの代わりにコバルトで形成しても同様の効果を得ることが可能である。   In the semiconductor device (RC-IGBT 301) in the present embodiment, the resistor 351 may include cobalt. Therefore, the same effect can be obtained even if the resistor 351 is formed of cobalt instead of polysilicon.

また、本実施形態における半導体装置（ＲＣ-ＩＧＢＴ３０１）において、絶縁ゲート型バイポーラトランジスタ（ＩＧＢＴ３０３）は、電子注入促進型であってもよい。従って、ＩＧＢＴ３０３がＩＥＧＴ（Ｉｎｊｅｃｔｉｏｎ Ｅｎｈａｎｃｅｄ Ｇａｔｅ Ｔｒａｎｓｉｓｔｏｒ）であっても同様の効果を得ることが可能である。   In the semiconductor device (RC-IGBT 301) in the present embodiment, the insulated gate bipolar transistor (IGBT 303) may be an electron injection promotion type. Therefore, even if the IGBT 303 is an IEGT (Injection Enhanced Gate Transistor), the same effect can be obtained.

＜本発明の実施形態の第１変形例＞
図４は、第１変形例における半導体装置（ＲＣ−ＩＧＢＴ３０１Ａ）の断面図である。図４に示すように、第１変形例においては、ＩＧＢＴ３０３のｐ＋コレクタ層３２８がダイオード３０２側に延長される。ウェル領域３０４におけるｐウェル３０９は、平面視でＩＧＢＴ３０３のｐ＋コレクタ層３２８に含まれる。その他の構成はＲＣ−ＩＧＢＴ３０１（図１から図３）と同じため説明を省略する。 <First Modification of Embodiment of the Present Invention>
FIG. 4 is a cross-sectional view of the semiconductor device (RC-IGBT 301A) in the first modification. As shown in FIG. 4, in the first modification, the p + collector layer 328 of the IGBT 303 is extended to the diode 302 side. The p well 309 in the well region 304 is included in the p + collector layer 328 of the IGBT 303 in plan view. Since other configurations are the same as those of the RC-IGBT 301 (FIGS. 1 to 3), description thereof is omitted.

＜効果＞
本発明の実施形態の第１変形例における半導体装置（ＲＣ−ＩＧＢＴ３０１Ａ）において、ウェル領域３０４は、平面視でコレクタ層（ｐ＋コレクタ層３２８）に含まれるように重なる。ｐウェル３０９は還流ダイオード（ダイオード３０２）として機能する。そのため、ダイオード３０２がオンの時にｐウェル３０９から注入されたホールが、ダイオード３０２オフ時にリカバリ電流の発生の要因となる。第１変形例では、図４に示すように、ｐウェル３０９の直下にｎ＋カソード層３２７の代わりにｐ＋コレクタ層３２８が延在して設けられる。従って、ダイオード３０２オン時に、ｎ＋カソード層３２７からの電子の注入が抑制されるため、ｐウェル３０９直下のキャリア密度が低下する。よって、ダイオード３０２オフ時のリカバリ電流を抑制することが可能である。 <Effect>
In the semiconductor device (RC-IGBT 301A) in the first modification of the embodiment of the present invention, the well region 304 overlaps so as to be included in the collector layer (p + collector layer 328) in plan view. The p-well 309 functions as a free wheel diode (diode 302). For this reason, holes injected from the p-well 309 when the diode 302 is on cause a recovery current when the diode 302 is off. In the first modification, as shown in FIG. 4, a p + collector layer 328 is provided directly below the p well 309 instead of the n + cathode layer 327. Therefore, when the diode 302 is turned on, injection of electrons from the n + cathode layer 327 is suppressed, so that the carrier density immediately below the p well 309 is lowered. Therefore, the recovery current when the diode 302 is off can be suppressed.

＜本発明の実施形態の第２変形例＞
図５は、第２変形例における半導体装置（ＲＣ−ＩＧＢＴ３０１Ｂ）の平面図である。第２の変形例においては、終端領域３０６の構造をウェル領域３０４と同様の構造とする。つまり、終端領域３０６においても、ｐウェル３３１とエミッタ電極３２５との間に抵抗体３５１を設ける。その他の構成はＲＣ−ＩＧＢＴ３０１（図１から図３）と同じため説明を省略する。 <Second Modification of Embodiment of the Present Invention>
FIG. 5 is a plan view of a semiconductor device (RC-IGBT 301B) in the second modification. In the second modification, the structure of the termination region 306 is the same as that of the well region 304. That is, also in the termination region 306, the resistor 351 is provided between the p well 331 and the emitter electrode 325. Since other configurations are the same as those of the RC-IGBT 301 (FIGS. 1 to 3), description thereof is omitted.

＜効果＞
本発明の実施形態の第２変形例における半導体装置（ＲＣ−ＩＧＢＴ３０１Ｂ）は、絶縁ゲート型バイポーラトランジスタ（ＩＧＢＴ３０３）および還流ダイオード（ダイオード３０２）を平面視で囲むように半導体基板に形成される終端領域３０６をさらに備え、第１電極（エミッタ電極３２５）は終端領域３０６にも接続しており、抵抗体３５１は、終端領域３０６と第１電極との間にも設けられる。 <Effect>
A semiconductor device (RC-IGBT 301B) according to a second modification of the embodiment of the present invention includes a termination region formed on a semiconductor substrate so as to surround the insulated gate bipolar transistor (IGBT 303) and the free wheel diode (diode 302) in plan view. The first electrode (emitter electrode 325) is also connected to the termination region 306, and the resistor 351 is also provided between the termination region 306 and the first electrode.

第２の変形例によれば、抵抗体３５１が適用されるｐウェルの面積が増えるため、リカバリ特性をより向上させることが可能である。   According to the second modification, since the area of the p-well to which the resistor 351 is applied increases, the recovery characteristics can be further improved.

＜本発明の実施形態の第３変形例＞
本発明の実施形態におけるＲＣ−ＩＧＢＴ３０１においてｐウェル３０９と抵抗体３５１とを接続する開口部３２０の形状を変形したのが、第３変形例におけるＲＣ−ＩＧＢＴ３０１Ｃである。図６は、第３変形例における半導体装置（ＲＣ−ＩＧＢＴ３０１Ｃ）の平面図である。図６に示すように、第３変形例では、開口部３２０は互いに分離した複数の開口で構成される。その他の構成はＲＣ−ＩＧＢＴ３０１（図１から図３）と同じため説明を省略する。 <Third Modification of Embodiment of the Present Invention>
In the RC-IGBT 301 according to the embodiment of the present invention, the shape of the opening 320 that connects the p-well 309 and the resistor 351 is modified in the RC-IGBT 301C in the third modified example. FIG. 6 is a plan view of a semiconductor device (RC-IGBT 301C) in the third modification. As shown in FIG. 6, in the third modification, the opening 320 is composed of a plurality of openings separated from each other. Since other configurations are the same as those of the RC-IGBT 301 (FIGS. 1 to 3), description thereof is omitted.

＜効果＞
本発明の実施形態の第３変形例における半導体装置（ＲＣ−ＩＧＢＴ３０１Ｃ）において、ウェル領域３０４と第１電極（エミッタ電極３２５）とは、互いに分離した複数の開口（開口部３２０）を通して接続されており、複数の開口のそれぞれには抵抗体３５１が設けられる。 <Effect>
In the semiconductor device (RC-IGBT 301C) in the third modification of the embodiment of the present invention, the well region 304 and the first electrode (emitter electrode 325) are connected through a plurality of openings (opening 320) separated from each other. A resistor 351 is provided in each of the plurality of openings.

従って、ＲＣ−ＩＧＢＴ３０１（図３）における開口部３２０は連続的なスリット形状であったが、第３変形例では、開口部３２０を互いに分離した複数の開口とする。この構成により、ｐウェル３０９とエミッタ電極３２５との間においてコンタクト抵抗が上昇するため、リカバリ特性をより向上させることが可能である。   Therefore, although the opening part 320 in RC-IGBT301 (FIG. 3) was a continuous slit shape, in the 3rd modification, let the opening part 320 be several opening isolate | separated from each other. With this configuration, the contact resistance increases between the p-well 309 and the emitter electrode 325, so that the recovery characteristics can be further improved.

なお、本発明は、その発明の範囲内において、実施形態および各変形例を自由に組み合わせたり、実施形態および各変形例を適宜、変形、省略することが可能である。   It should be noted that the present invention can be freely combined with the embodiment and each modification within the scope of the invention, and the embodiment and each modification can be appropriately modified and omitted.

１０１，３０１，３０１Ａ，３０１Ｂ，３０１Ｃ ＲＣ−ＩＧＢＴ、１０２，３０２ ダイオード、１０３，３０３ ＩＧＢＴ、１０４，３０４ ウェル領域、１０５，３０５ ゲートパッド領域、１０６，３０６ 終端領域、１０７，３０７ 耐圧保持領域、１０８，３０８ ｎ−ドリフト層、１０９，１３１，３０９，３３１ ｐウェル、１１０，３１０ ｐアノード層、１１１，１１７，３１１，３１７ トレンチ、１１２，３１２ 酸化膜、１１３，１１９，３１３，３１９ ポリシリコン、１１４，３１４ ｐベース層、１１５，３１５ ｎ＋エミッタ層、１１６，３１６ ｐ＋コンタクト層、１１８，３１８ ゲート酸化膜、１２０，１２３，１２４，１３４，１３５，３２０，３２４，３２３，３３５ 開口部、１２１，１３３，３３３ ｐ＋コンタクト層、１２２，３２２ 絶縁膜、１２５，３２５ エミッタ電極、１２６，３２６ ｎバッファ層、１２７，３２７ ｎ＋カソード層、１２８，３２８ ｐ＋コレクタ層、１２９，３２９ コレクタ電極、３５１ 抵抗体。   101, 301, 301A, 301B, 301C RC-IGBT, 102, 302 diode, 103, 303 IGBT, 104, 304 well region, 105, 305 gate pad region, 106, 306 termination region, 107, 307 breakdown voltage holding region, 108 , 308 n-drift layer, 109, 131, 309, 331 p well, 110, 310 p anode layer, 111, 117, 311, 317 trench, 112, 312 oxide film, 113, 119, 313, 319 polysilicon, 114 , 314 p base layer, 115, 315 n + emitter layer, 116, 316 p + contact layer, 118, 318 gate oxide film, 120, 123, 124, 134, 135, 320, 324, 323, 335 opening, 121, 133 333 + Contact layer, 122 or 322. insulating film, 125,325 emitter electrode, 126,326 n buffer layer, 127,327 n + cathode layer, 128,328 p + collector layer, 129,329 collector electrode, 351 a resistor.

Claims (8)

半導体基板の第１主面側にエミッタ層、前記半導体基板の第２主面側にコレクタ層を備える絶縁ゲート型バイポーラトランジスタと、
前記半導体基板の前記第１主面側にアノード層、前記半導体基板の前記第２主面側にカソード層を備える還流ダイオードと、
前記絶縁ゲート型バイポーラトランジスタと前記還流ダイオードとの境界に設けられ、当該絶縁ゲート型バイポーラトランジスタと当該還流ダイオードとを分離するウェル領域と、
前記エミッタ層、前記アノード層および前記ウェル領域に接続するように前記半導体基板の前記第１主面に形成された第１電極と、
前記ウェル領域と前記第１電極との間に設けられる抵抗体と、
前記コレクタ層および前記カソード層に接続するように前記半導体基板の前記第２主面に形成された第２電極と、
を備える、
半導体装置。 An insulated gate bipolar transistor comprising an emitter layer on the first main surface side of the semiconductor substrate and a collector layer on the second main surface side of the semiconductor substrate;
A free-wheeling diode comprising an anode layer on the first main surface side of the semiconductor substrate and a cathode layer on the second main surface side of the semiconductor substrate;
A well region provided at a boundary between the insulated gate bipolar transistor and the reflux diode, and separating the insulated gate bipolar transistor and the reflux diode;
A first electrode formed on the first main surface of the semiconductor substrate so as to be connected to the emitter layer, the anode layer, and the well region;
A resistor provided between the well region and the first electrode;
A second electrode formed on the second main surface of the semiconductor substrate so as to be connected to the collector layer and the cathode layer;
Comprising
Semiconductor device. 前記ウェル領域は、平面視で前記コレクタ層に含まれるように重なる、
請求項１に記載の半導体装置。 The well region overlaps to be included in the collector layer in plan view;
The semiconductor device according to claim 1. 当該絶縁ゲート型バイポーラトランジスタおよび当該還流ダイオードを平面視で囲むように前記半導体基板に形成される終端領域をさらに備え、
前記第１電極は前記終端領域にも接続しており、
前記抵抗体は、前記終端領域と前記第１電極との間にも設けられる、
請求項１または請求項２に記載の半導体装置。 A termination region formed in the semiconductor substrate so as to surround the insulated gate bipolar transistor and the free-wheeling diode in plan view;
The first electrode is also connected to the termination region;
The resistor is also provided between the termination region and the first electrode.
The semiconductor device according to claim 1 or 2. 前記ウェル領域と前記第１電極とは、互いに分離した複数の開口を通して接続されており、
前記複数の開口のそれぞれには前記抵抗体が設けられる、
請求項１から請求項３のいずれか一項に記載の半導体装置。 The well region and the first electrode are connected through a plurality of openings separated from each other,
Each of the plurality of openings is provided with the resistor.
The semiconductor device as described in any one of Claims 1-3. 前記抵抗体はポリシリコンである、
請求項１から請求項４のいずれか一項に記載の半導体装置。 The resistor is polysilicon;
The semiconductor device as described in any one of Claims 1-4. 前記抵抗体はチタンを含む、
請求項１から請求項４のいずれか一項に記載の半導体装置。 The resistor includes titanium;
The semiconductor device as described in any one of Claims 1-4. 前記抵抗体はコバルトを含む、
請求項１から請求項４のいずれか一項に記載の半導体装置。 The resistor includes cobalt;
The semiconductor device as described in any one of Claims 1-4. 前記絶縁ゲート型バイポーラトランジスタは、電子注入促進型である、
請求項１から請求項７のいずれか一項に記載の半導体装置。 The insulated gate bipolar transistor is an electron injection promoting type,
The semiconductor device according to claim 1.
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