JP2016168213A - Slot machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance interest in a game by not inhibiting an expectation of a player for being granted a privilege when derivation displays of a plurality of number of times of display results are performed.SOLUTION: In a normal time, if a replay is consecutively won in 3 games, a granting of one set of ART is established. Also, if a winning of the replay occurs at a fourth game, another one set of ART is granted. At the third game and the fourth game, by performing a presentation determination lottery by using a normal table, a precursor presentation that suggests or notifies a granting of ART is configured not to be performed until the fourth game.SELECTED DRAWING: Figure 32

Description

  The present invention includes a variable display unit capable of variably displaying a plurality of types of identification information each identifiable. After the variable display unit is variably displayed, the display result is derived by stopping the variable display of the variable display unit. The present invention relates to a slot machine capable of generating a winning according to the display result.

  A slot machine generally includes a variable display device having a plurality of (usually three) reels having a plurality of types of symbols as identification information drawn on the outer periphery, and each reel has a start lever by a player. Rotation is started by operating, and when the player operates a stop button provided corresponding to each reel, the rotation is stopped within a range of a predetermined maximum delay time from the operation timing. . A winning is generated according to the display result derived when the rotation of all reels is stopped.

  The types of winning combinations include small roles, special roles, and replaying roles. Here, in the winning of a small role, the player can obtain a profit that a predetermined number of medals are paid out for each type of small role. In the special role winning, the player can obtain a profit that the next game is shifted to a gaming state advantageous to the player, such as a regular bonus or a big bonus. In the winning of the re-gamer, it is possible to obtain a profit that the next game can be performed without consuming new medals for setting the number of bets.

  As such a slot machine, there is known a slot machine that gives a privilege when the number of consecutive winnings of a small role reaches a predetermined number (for example, 6 times) (for example, Patent Document 1).

JP 2005-166861 A (paragraph 0047 and the like)

  By the way, in the slot machine described in Patent Literature 1, when the number of consecutive winnings of a small role exceeds the predetermined number (for example, 7 times, 8 times,...) It can be considered. However, if a notice is given that a privilege will be granted when the number of consecutive winnings of the small role reaches a predetermined number, the game that the bonus will be granted after the number of consecutive winnings exceeds the predetermined number People's expectation will be hindered.

  The present invention has been made paying attention to such problems, and without detracting from the player's expectation for the provision of benefits when a plurality of display results are derived and displayed. It is an object to provide a slot machine that can improve interest.

In order to solve the above problems, the slot machine of the present invention provides:
A variable display unit capable of variably displaying a plurality of types of identification information each identifiable, and after variably displaying the variable display unit, deriving a display result by stopping the variable display of the variable display unit, In a slot machine (for example, slot machine 1) that can generate a prize according to the display result,
A display result determining means (for example, a portion indicated by Sd2 in FIG. 20) for determining a display result that allows derivation;
Derivation control means for deriving a display result based on the determination result of the display result determination means (for example, a portion indicated by Sd4 in FIG. 20);
A privilege granting means (for example, a portion shown in FIG. 29) for granting a privilege (for example, ART) when a first grant condition that can be satisfied when a plurality of games are performed is satisfied;
Informing means (for example, a portion shown in Sp6 in FIGS. 31 and 22) for notifying that a privilege is granted based on the establishment of the first grant condition,
The privilege granting unit grants a privilege even when a second grant condition that can be met after the first grant condition is met (for example, a portion shown in FIG. 29),
The notification means gives a privilege based on the fact that the first grant condition is met after the second grant condition cannot be met after the first grant condition is met. Control for notification is started (for example, a portion shown in FIG. 32).
According to this configuration, it is possible to improve the interest of the game without impairing the player's expectation for the provision of the privilege when the display result is derived a plurality of times.

The privilege giving means attaches a privilege as the first grant condition is satisfied when the number of consecutive derivations of the specific display result reaches a predetermined number, and the number of consecutive derivations of the specific display result is larger than the predetermined number of times. When the specific number of times is reached, a privilege is given as the second grant condition is satisfied (for example, a portion indicated by Sn9 and Sn12 in FIG. 29).
According to this configuration, the player pays attention to the fact that specific display results are continuously derived, so that the interest of the game can be improved.

The notifying means executes an effect of giving a privilege due to the establishment of the first granting condition over a plurality of games (for example, a portion indicated by Sr7 in FIG. 30).
According to this configuration, it is possible to attract the player's attention as to whether or not notification that a privilege is granted is performed.

Provided with a privilege grant determination means (for example, a portion shown in FIG. 29) for determining whether or not to grant a privilege by lottery when a quasi grant condition established before the first grant condition is established,
The privilege granting unit grants a privilege when the privilege granting determination unit decides to grant the privilege (for example, a portion indicated by Sn6 in FIG. 29).
According to this configuration, the player's expectation can be maintained even if the grant condition is not satisfied.

The informing means executes an effect of giving a privilege due to the establishment of the semi-grant condition when the first grant condition cannot be established when the privilege grant determining means decides to grant the privilege. (For example, the part shown in FIG. 32 (b)).
According to this configuration, it is possible to prevent the player's sense of expectation for the privilege grant when the display result is derived a plurality of times from being displayed.

A variable display unit capable of variably displaying a plurality of types of identification information each identifiable, and after variably displaying the variable display unit, deriving a display result by stopping the variable display of the variable display unit, In a slot machine (for example, slot machine 1) that can generate a prize according to the display result,
A display result determining means (for example, a portion indicated by Sd4 in FIG. 20) for determining a display result that allows derivation;
A privilege granting means (for example, a portion shown in FIG. 21) for granting a privilege when a grant condition that can be satisfied when a plurality of games are played is established;
Production execution means (for example, a portion indicated by Sp6 in FIG. 22) that produces an effect before the display result is derived based on the determination result of the display result determination means,
The effect executing means is capable of executing a specific effect (for example, a replay notification effect) suggesting that the specific display result is allowed to be derived when the specific display result is allowed to be derived. When the time execution means (for example, the part for performing the effect determination lottery using the precursor replay table indicated by Sg15 in FIG. 25) and the derivation of the specific display result are not permitted, the advantageous suggestion condition is satisfied. Non-permissible execution means (for example, a part for performing the effect determination lottery using the sign loss table shown by Sg5 in FIG. 24) capable of executing a specific effect in the case,
The non-permitted execution means restricts execution of a specific effect when a provision condition can be established by deriving a display result (for example, a portion shown in FIG. 28).
According to this configuration, it is possible to excite the interest of the game without betraying the player's expectation.

In order to solve the above problems, the gaming machine of the present invention is:
In a gaming machine (for example, slot machine 1) capable of playing a game,
Storage means for storing the program (for example, ROM 208);
A microcomputer (for example, a portion shown in FIG. 41) that executes processing according to the program stored in the storage means,
The program includes an interrupt program (for example, a portion shown in FIG. 42) that is executed in response to the occurrence of an interrupt.
The microcomputer is
Interrupt permission means (for example, the part shown in FIG. 33 and FIG. 34) for executing a process for permitting an interrupt after executing a process for performing settings relating to the interrupt;
Interrupt processing execution means (for example, the portion shown in FIG. 8 and FIG. 9) that executes processing according to the interrupt program based on the interrupt when the interrupt is permitted;
Address storage means (for example, a portion shown in FIG. 42) having a storage area capable of storing the address of the interrupt program in the storage means;
Determination means (for example, a portion shown in FIG. 43) for determining whether the address stored in the storage area of the address storage means is within a predetermined range when the microcomputer is activated;
Activation limiting means (for example, a portion shown in FIG. 43) is provided for restricting activation of the microcomputer when the determination means determines that the interrupt program address is not within a predetermined range.
According to this configuration, it is possible to prevent an unintended interrupt process from being executed in advance.

The interrupt permission means executes a setting for starting the operation of the timer for measuring the time interval from the initial value while designating the time interval for the interrupt generated at a predetermined cycle as the setting relating to the interrupt.
According to this configuration, it is possible to prevent an unintended interrupt process from being executed in advance.

The microcomputer
Setting content storage means having a storage area capable of storing settings relating to interrupts;
And an initial value setting means for setting an initial value indicating initial setting contents in at least a part of the storage area of the setting content storage means when the microcomputer is activated.
According to this configuration, it is possible to prevent the interrupt process from being executed with unintended settings in advance.

The microcomputer
Storage area setting means for setting a storage area in which a user program is stored when the microcomputer is activated;
User program execution means (for example, CPU 207) for executing processing according to the user program stored in the storage area stored by the storage area setting means;
An abnormality control execution means for executing abnormality control when the user program execution means calls a program stored in an area other than the storage area set by the storage area setting means,
The predetermined range includes at least an address of an area where the user program is stored (for example, a portion shown in FIG. 43).
According to this configuration, execution of an unauthorized program can be prevented.

The microcomputer
A startup interrupt prohibiting means for prohibiting an interrupt when the microcomputer is started (for example, a portion for performing the processing of Sa1 in FIG. 33);
User program execution means (for example, CPU 207) for executing processing according to the user program;
Pre-setting interrupt prohibiting means for executing a process for prohibiting an interrupt after the user program executing means starts executing a process in accordance with the user program and before the interrupt permitting means executes a process for setting the interrupt. (For example, the portion that performs the processing of Sa1 before Sa16a, Sa20a, and Sa26a in FIG. 33).
According to this configuration, it is possible to prevent an unintended interrupt process from being executed in advance.

The microcomputer
Data storage means having a storage area which is referred to when the microcomputer is started and which can store data for setting the function of the microcomputer;
Data setting means (for example, CPU 207) for setting the data in the storage area of the data storage means,
The storage area of the data storage means is an unused area (for example, a random number circuit operation mode setting (related symbol name: HRDMD) that the data setting means does not set any function based on a value set in the storage area. ) Includes bit 3 of HEDMD, and system settings (related symbol name: HSYSCNT) and HSYSCNT bits 5 to 7),
The activation restriction means restricts the activation of the microcomputer when a specific value is set in the unused area (for example, a portion shown in FIG. 43).
According to this configuration, an unintended setting can be prevented.

In order to solve the above problems, the gaming machine of the present invention is:
In a gaming machine (for example, slot machine 1) capable of playing a game,
Storage means for storing the program (for example, ROM 208);
A microcomputer (for example, a portion shown in FIG. 41) that executes processing according to the program stored in the storage means,
The program includes an interrupt program that is executed in response to the occurrence of an interrupt,
The microcomputer is
Numerical value updating means (for example, random number generation circuit 42) for updating and outputting numerical data;
Interrupt permitting means for executing processing for permitting an interrupt after executing processing for setting numerical data updating by the numerical value updating means (for example, a portion for performing the processing of Sa17, Sa21, and Sa27 in FIGS. 33 and 34) )When,
Interrupt processing execution means (for example, the portion shown in FIG. 8 and FIG. 9) that executes processing according to the interrupt program based on the interrupt when the interrupt is permitted;
Address storage means (for example, a portion shown in FIG. 42) having a storage area capable of storing the address of the interrupt program in the storage means;
Determination means (for example, a portion shown in FIG. 43) for determining whether the address stored in the storage area of the address storage means is within a predetermined range when the microcomputer is activated;
Activation limiting means (for example, a portion shown in FIG. 43) is provided for restricting activation of the microcomputer when the determination means determines that the interrupt program address is not within a predetermined range.
According to this configuration, it is possible to prevent an unintended interrupt process from being executed in advance.

The microcomputer includes a random number circuit (for example, a random number circuit 212) that generates numerical data to be a random value,
The random number circuit includes:
Numeric update means,
Random value storage means for capturing and storing numerical data output from the numerical value updating means based on an input of a predetermined signal as a random value;
A first setting that allows new numerical data to be taken in and stored as random number values in the random value storage means when a predetermined signal is input when the random value values are stored in the random value storage means And when a predetermined signal is input when a random value is stored in the random value storage means, new numerical data cannot be stored in the random value storage means as a random value. Random value storage setting means (for example, a portion shown in [Random number operation]) is set.
According to this configuration, it is possible to prevent an unintended random value from being taken in.

The microcomputer
A random number circuit (for example, the random number circuit 212) that generates numerical data to be a random number value;
Setting content storage means having a storage area capable of storing settings relating to the random number circuit;
And an initial value setting means for setting an initial value indicating initial setting contents in at least a part of the storage area of the setting content storage means when the microcomputer is activated.
According to this configuration, it is possible to prevent numerical data that becomes a random value from being set unintentionally.

In order to solve the above problems, the gaming machine of the present invention is:
In a gaming machine (for example, slot machine 1) capable of playing a game,
Storage means for storing the program (for example, ROM 208);
A microcomputer (for example, a portion shown in FIG. 41) that executes processing according to the program stored in the storage means,
The program includes an interrupt program that is executed in response to the occurrence of an interrupt,
The microcomputer is
Interrupt processing execution means (for example, the portion shown in FIG. 38 and FIG. 39) that executes processing according to the interrupt program based on the interrupt when the interrupt is permitted;
Fluctuating data storage means (for example, RAM 41c) for storing fluctuating data that fluctuates in accordance with execution of processing according to a program;
An initialization process execution means (for example, a part for performing the processes of FIGS. 33 and 34) for executing an initialization process for initializing at least a part of the stored contents of the variation data storage means when an initialization condition is satisfied; ,
Interrupt prohibiting means for prohibiting interrupts when executing the initialization process (for example, a part for performing the processing of Sa1 in FIG. 33);
Address storage means (for example, a portion shown in FIG. 42) having a storage area capable of storing the address of the interrupt program in the storage means;
Determination means (for example, a portion shown in FIG. 43) for determining whether the address stored in the storage area of the address storage means is within a predetermined range when the microcomputer is activated;
Activation limiting means (for example, a portion shown in FIG. 43) is provided for restricting activation of the microcomputer when the determination means determines that the interrupt program address is not within a predetermined range.
According to this configuration, it is possible to prevent an unintended interrupt process from being executed in advance.

The predetermined storage area includes an unused area,
A plurality of conditions (for example, conditions for initialization 1 to 4) are set as initialization conditions,
The data control means initializes the data in the storage area including the unused area in accordance with the type of the initialization condition that is satisfied (for example, the part indicated by “About initialization”).
According to this configuration, it is possible to prevent an unintended interrupt process from being executed in advance.

The microcomputer includes external data output processing means (for example, main control unit 41) for executing data output processing for outputting data to the outside.
The interrupt prohibiting means prohibits the interrupt when the external data output processing means is executing the data output process (for example, a part that executes the interrupt prohibition before Sm3 in FIG. 40).
According to this configuration, it is possible to prevent unintended data from being output.

In order to solve the above problems, the gaming machine of the present invention is:
In a gaming machine (for example, slot machine 1) capable of playing a game,
Storage means for storing the program (for example, ROM 208);
A microcomputer (for example, a portion shown in FIG. 41) that executes processing according to the program stored in the storage means,
The program includes an interrupt program that is executed in response to the occurrence of an interrupt,
The microcomputer is
Interrupt processing execution means (for example, the portion shown in FIG. 38 and FIG. 39) that executes processing according to the interrupt program based on the interrupt when the interrupt is permitted;
When the power supply to the gaming machine is stopped, the power supply stop processing means for executing the power supply stop processing for backing up the execution state of the processing by the microcomputer (for example, the portion shown in [Modification]) When,
A recovery means (for example, a portion shown in [Modification]) for restarting the execution of the process according to the program based on the execution state of the backed-up process;
Address storage means (for example, a portion shown in FIG. 42) having a storage area capable of storing the address of the interrupt program in the storage means;
Determination means (for example, a portion shown in FIG. 43) for determining whether the address stored in the storage area of the address storage means is within a predetermined range when the microcomputer is activated;
An activation restriction unit (for example, a portion shown in FIG. 43) that restricts activation of the microcomputer when the determination unit determines that the address of the interrupt program is not within a predetermined range;
Whether or not to allow interruption based on the backed up information when backing up information indicating whether or not interruption is permitted in the power supply stop process and restarting the process by the recovery means Is set (for example, a portion shown in [Modification]).
According to this configuration, it is possible to prevent an unintended interrupt process from being executed in advance.

The program includes a non-maskable interrupt program (for example, a portion related to an NMI interrupt) that is executed in response to the occurrence of a non-maskable interrupt that cannot be prohibited based on an input of a power supply stop signal.
When the non-maskable interrupt occurs, the microcomputer executes a process according to the non-maskable interrupt program (for example, a portion related to an NMI interrupt, a portion shown in [Modification]). With
The power supply stop process includes a process according to a non-maskable interrupt program (for example, a portion shown in [Modification]),
The storage area of the address storage means includes the address of the non-maskable interrupt program (for example, the portion shown in FIG. 42),
The determination means determines whether the address of the non-maskable interrupt program stored in the storage area of the address storage means is within a predetermined range when the microcomputer is activated (for example, as shown in [Modification] portion),
The activation restriction means restricts the activation of the microcomputer when the determination means determines that the address of the non-maskable interrupt program is not within a predetermined range (for example, a portion shown in [Modification]).
According to this configuration, it is possible to prevent an unintended interrupt process from being executed in advance.

The program includes a non-maskable interrupt program (for example, a portion related to an NMI interrupt) that is executed in response to the occurrence of a non-maskable interrupt that cannot be prohibited based on an input of a power supply stop signal.
The microcomputer includes non-maskable interrupt processing execution means (for example, a portion shown in [Modification]) that executes processing according to a non-maskable interrupt program when a non-maskable interrupt occurs.
The power supply stop process includes a process according to a non-maskable interrupt program (for example, a portion shown in [Modification]),
The period from when the non-maskable interrupt generation condition is satisfied until the non-maskable interrupt is generated is shorter than the period until the interrupt generation condition is satisfied and the interrupt is generated (for example, [Modification] Part shown in).
According to this configuration, it is possible to suitably execute the power supply stop process.

In order to solve the above problems, the gaming machine of the present invention is:
In a gaming machine (for example, slot machine 1) capable of playing a game,
Control means for performing control (for example, main control unit 41);
Storage means (for example, RAM 41c) capable of storing data stored when the power supply is stopped and capable of storing data generated when the control means performs control;
The control means includes
A storage content determination unit (for example, a part for performing the processing of Sa16 in FIG. 34) for determining whether or not the storage content stored in the storage unit is normal after power supply is started;
An initialization condition determining means (for example, a part for performing the processing of Sa15 in FIG. 34) for determining whether or not an initialization condition based on an artificial operation (for example, the setting key switch is turned on) is satisfied;
When the storage content determination unit determines that the storage content of the storage unit is normal, and the initialization condition determination unit determines that the initialization condition is not satisfied, the storage content of the storage unit is A recovery means for recovering the control based on the base (for example, a portion for performing the processing of Sa17 to Sa20 in FIG. 34);
When the initialization condition determination unit determines that the initialization condition is satisfied, the initialization unit performs initialization processing for initializing the storage contents of the storage unit (for example, the processing of Sb4 in FIG. 35). Execution part)
The initialization means initializes the storage contents of different areas in the storage area of the storage means based on the determination result of the storage content determination means (for example, if Sb2 in FIG. 35 is N, the processing of Sb3 is executed) Then, the process of Sb4 is executed, and when Sb2 is Y, the process of Sb4 is executed without executing the process of Sb3).
According to this configuration, it is possible to suitably execute initialization of data stored in the storage unit.

The initialization unit initializes the storage content of the storage unit when the storage content determination unit determines that the storage content of the storage unit is not normal, and the initialization condition determination unit determines that the initialization condition is not satisfied. (For example, a part for executing the processing of Sa23 and Sa24 in FIG. 34).
According to this configuration, it is possible to prevent the control from being performed in a state where the storage content of the storage unit is not normal.

Based on an operation of a predetermined setting operation means, an allowable stage setting means for selecting and setting one of the allowable stages from a plurality of types of allowable stages having different degrees of advantage for the player (for example, FIG. 35 and FIG. 36 parts for executing processing)
The initialization means initializes an area including at least an area storing the allowable stage set by the allowable stage setting means when the storage content determination means determines that the storage content of the storage means is not normal, When the stored content determining means determines that the stored content is normal, an area that does not include at least the area storing the allowable level set by the allowable level setting means is initialized (for example, Nb in Sb2 of FIG. 35). In the case of Sb3, the process of Sb3 is executed and the process of Sb4 is executed. In the case of Y in Sb2, the part of Sb4 is executed without executing the process of Sb3).
According to this configuration, the setting of the allowable stage can be suitably protected.

Specific information storage control means (for example, Sa25 in FIG. 34) is executed to store specific information (for example, RAM abnormality flag) in the storage means when the storage content determination means determines that the storage content of the storage means is not normal. Part)
The storage content determination means determines whether the storage content of the storage means is normal based on the specific information when the power supply is stopped after determining that the storage content of the storage means is not normal and the power supply is started again. (For example, the part which performs the process of Sa16 of FIG. 33).
According to this configuration, it is possible to prevent the control from restarting in a state where the storage content of the storage unit is not normal.

Interrupt processing means (for example, a part for executing the processing of FIG. 38 and FIG. 39) that performs interrupt processing based on the establishment of a periodic interrupt condition;
Interrupt prohibiting means (for example, a part for executing the processing of Sa1 in FIG. 33 and Sc1 in FIG. 37) for prohibiting execution of the interrupt processing when the initialization means is performing the initialization processing is provided.
According to this configuration, it is possible to prevent other processing from being performed during the initialization processing.

The control means includes external data output processing means (for example, the main control unit 41) for executing data output processing for outputting data to the outside,
Interrupt prohibiting means for prohibiting interrupts when the external data output processing means is executing data output processing (for example, a portion for executing interrupt prohibition before Sm3 in FIG. 40) is provided.
According to this configuration, unintended data can be prevented from being output.

Predetermined process execution means (for example, a part for executing the process of FIG. 37) for repeatedly executing a predetermined process including an initialization process for at least one unit of game for each unit of game;
Based on an operation of a predetermined setting operation means, an allowable stage setting means for selecting and setting one of the allowable stages from a plurality of types of allowable stages having different degrees of advantage for the player (for example, FIG. 35 and FIG. 36 parts for executing processing)
The initialization means initializes the storage contents of the storage means when the allowable stage is set (for example, a part for executing the process of Sb4 in FIG. 35),
The predetermined process execution means starts the predetermined process before performing the initialization process for each game (for example, the part for executing the process of Sc3 in FIG. 37) after the setting of the allowable stage is completed ( For example, after the setting change process is finished, the part starts execution from the process of Sc1 in FIG. 37).
According to this configuration, in addition to the initialization process when the allowable stage is set, the initialization process for each game can be executed.

Storage means for storing the program (for example, ROM 208);
A microcomputer (for example, a portion shown in FIG. 13) that executes processing according to the program stored in the storage means,
The program includes an interrupt program (for example, a portion shown in FIG. 42) that is executed in response to the occurrence of an interrupt.
The microcomputer is
Interrupt permission means (for example, the part shown in FIG. 33 and FIG. 34) for executing a process for permitting an interrupt after executing a process for performing settings relating to the interrupt;
Interrupt processing execution means (for example, the portion shown in FIG. 38 and FIG. 39) that executes processing according to the interrupt program based on the interrupt when the interrupt is permitted;
Address storage means (for example, a portion shown in FIG. 42) having a storage area capable of storing the address of the interrupt program in the storage means;
Determination means (for example, a portion shown in FIG. 43) for determining whether the address stored in the storage area of the address storage means is within a predetermined range when the microcomputer is activated;
Activation limiting means (for example, a portion shown in FIG. 43) is provided for restricting activation of the microcomputer when the determination means determines that the interrupt program address is not within a predetermined range.
According to this configuration, it is possible to prevent an unintended interrupt process from being executed in advance.

In order to solve the above problems, the gaming machine of the present invention is:
In a gaming machine (for example, slot machine 1) capable of playing a game,
Control means for controlling;
Storage means (for example, RAM 41c) capable of storing data stored when the power supply is stopped and capable of storing data generated when the control means performs control;
The control means includes
An initial setting processing means (for example, a part for executing the processing of FIGS. 33 and 34) for performing initial setting processing after power supply is started;
Game processing means (for example, a part for executing the processing of FIG. 37) that repeatedly executes at least a repeating process for each unit of game,
The initial setting processing means executes at least a first initialization process for initializing the stored contents of the storage means when the initialization condition is satisfied as the initial setting process (for example, Sb4 in FIG. 35). To execute the process)
The game processing means executes at least a second initialization process for initializing the stored contents of the storage means for each unit of game as the repetitive process (for example, executes the process of Sc3 in FIG. 37). Part), when the initial setting processing means starts executing the repetitive process after executing the first initialization process, the repetitive process is executed at least before the second initializing process is executed. Start (for example, a portion where execution is started from the processing of Sc1 in FIG. 37 after the setting change processing is completed).
According to this configuration, it is possible to suitably execute control for each game of one unit.

In the second initialization process, the game processing means initializes the storage contents in the specific area of the storage area of the storage means (for example, all areas except the used stack area (unused and unused stack areas are Part) to be initialized)),
The initial setting means initializes the storage contents of the area including the specific area among the storage areas of the storage means in the first initialization process (for example, a part for initializing the unused area and the unused stack area). .
According to this configuration, initialization can be reliably performed.

Interrupt processing means (for example, a part for executing the processing of FIG. 38 and FIG. 39) that performs interrupt processing based on the establishment of a periodic interrupt condition;
An interrupt condition may be satisfied when the initial setting process is performed (for example, a part for executing the process of Sb6 in FIG. 35).
According to this configuration, the data rewritten by the interrupt process executed during the initial setting process can be initialized by the second initialization process.

Interrupt processing means (for example, a part for executing the processing of FIG. 38 and FIG. 39) that performs interrupt processing based on the establishment of a periodic interrupt condition;
Interrupt prohibiting means for prohibiting execution of interrupt processing when the initial setting means is performing the first initialization process and when the game processing means is performing the second initialization process (for example, FIG. 33) And a part for executing the process of Sc1 of FIG. 37).
According to this configuration, it is possible to prevent other processing from being performed during the initialization processing.

In order to solve the above problems, the gaming machine of the present invention is:
In a gaming machine (for example, slot machine 1) capable of playing a game,
Provided with control means (for example, main control unit 41) for performing control,
The control means includes
Setting means for setting the control means (for example, startup processing);
After setting by the setting means, processing means for executing processing based on a control program (for example, user program) (for example, a portion for executing the processing of FIGS. 33 and 34),
Interrupt generating means (for example, IMF = 1) for generating an interrupt in response to the establishment of the interrupt condition;
Interrupt processing execution means for executing interrupt processing based on the interrupt (for example, a portion for executing the processing of FIGS. 38 and 39);
Interrupt limiting means for limiting interrupt generation by the interrupt generating means (for example, IMF = 0),
The interrupt restricting means is a first interrupt restricting means for restricting the generation of an interrupt before the processing based on the control program is started (for example, when the microcomputer is started, the PSW is cleared to 00h and the IMF is 33 and the second interrupt limiting means for limiting the generation of interrupts at the start of the process based on the control program (for example, the process of Sa1 in FIG. 33 by executing the DI command in the initial setting process) To execute).
According to this configuration, it is possible to prevent an unintended interrupt from occurring.

An interrupt permission unit (for example, a part for executing the processes of Sa20 and Sa22 in FIG. 34) is provided that executes a process for permitting the generation of an interrupt after executing the process for setting the interrupt.
According to this configuration, it is possible to prevent an unintended interrupt from occurring.

Provided with an interrupt permission means (for example, a part for executing the processes of Sa20 and Sa22 in FIG. 34) for executing a process for permitting an interrupt after executing a process for performing settings relating to the interrupt,
The interrupt permission means designates a time interval for an interrupt that occurs in a predetermined cycle as a setting related to the interrupt, and executes a setting for starting a timer that measures the time interval from an initial value (for example, CTC). If TMCNT0 to 2 are set even during the counting operation, the setting contents of CTC0 to 2 and TMCNT0 to TMCNT2 are updated, and the timer value being counted is a part that counts down again from the setting value of CTC0 to 2).
According to this configuration, it is possible to prevent an unintended interrupt from occurring.

Setting content storage means (for example, the portion shown in FIGS. 31 to 33) having a storage area capable of storing settings relating to interrupts;
In the processing based on the control program, an initial value setting unit is provided for setting an initial value indicating the initial setting content in at least a part of the storage area of the setting content storage unit.
According to this configuration, it is possible to prevent interrupt processing from being performed with unintended settings.

A storage means (for example, RAM 41c) capable of storing data generated when the control means performs control;
When the initialization condition determination unit determines that the initialization condition is satisfied, the control unit performs initialization processing for initializing the storage contents of the storage unit (Sa24, FIG. 34). 35) and a part for executing the process of Sc3 of FIG.
Further provided is an interrupt prohibiting means (for example, a part for executing the processing of Sa1 in FIG. 33 and Sc1 in FIG. 37) for prohibiting execution of the interrupt processing when the initialization means is performing the initialization processing.
According to this configuration, it is possible to prevent other processing from being performed during the initialization processing.

The microcomputer
Storage area setting means for setting a storage area in which a user program is stored when the microcomputer is activated (for example, setting of a program end address shown in FIG. 46);
User program execution means (for example, CPU 207) for executing processing according to the user program stored in the storage area stored by the storage area setting means;
An abnormality control execution means for executing abnormality control when the user program execution means calls a program stored in an area other than the storage area set by the storage area setting means,
The predetermined range includes at least an address of an area where the user program is stored (for example, a portion shown in FIG. 43).
According to this configuration, execution of an unauthorized program can be prevented.

  In addition, this invention may have only the invention specific matter described in the claim of this invention, and has a structure other than this invention specific matter with the invention specific matter described in the claim of this invention. It may be a thing.

It is a front view of the slot machine of the embodiment to which the present invention is applied. It is a perspective view which shows the internal structure of a slot machine. It is a figure which shows the symbol arrangement | sequence of a reel. It is a block diagram which shows the structure of a slot machine. It is a block diagram which shows the structure of a main control part. It is a figure for demonstrating the technical matter relevant to the kind of special combination, the symbol combination of a special combination, and a special combination. It is a figure for demonstrating the technical matter relevant to the kind of small combination, the symbol combination of a small combination, and a small combination. It is a figure for demonstrating the technical matter relevant to the kind of re-game player, the symbol combination of a re-game player, and a re-game player. It is a figure for demonstrating the technical combination relevant to the symbol combination of a transfer event, and a transfer event. It is a figure for demonstrating the transition of a gaming state. It is a figure which shows the outline | summary of a game state. It is a figure for demonstrating the combination of the lottery object combination read as a lottery object role for every game state. It is a figure for demonstrating the combination of the lottery object combination read as a lottery object role for every game state. It is a figure for demonstrating the combination of the lottery object combination read as a lottery object role for every game state. It is a figure for demonstrating the combination of the combination which a prize is permitted by a lottery object combination. It is a figure for demonstrating the combination of the combination which a prize is permitted by a lottery object combination. It is a figure for demonstrating the reel control at the time of several small part winning. It is a figure for demonstrating the reel control at the time of several re-game player winning. It is a flowchart which shows the control content of the starting process which a main control part performs. It is a flowchart which shows the control content of the game process which a main control part performs. In 1st Embodiment, it is a flowchart which shows the control content of the privilege provision process which a main control part performs. In 1st Embodiment, it is a flowchart which shows the control content of the timer interruption process (sub) which a sub control part performs. In 1st Embodiment, it is a flowchart which shows the control content of the indication production preparation process which a sub control part performs. In 1st Embodiment, it is a flowchart which shows the control content of the effect determination process which a sub-control part performs. In 1st Embodiment, it is a flowchart which shows the control content of the effect determination process which a sub-control part performs. In 1st Embodiment, it is a flowchart which shows the control content of the effect determination process which a sub-control part performs. It is a flowchart which shows the control content of the effect determination process which a sub control part performs in the modification of 1st Embodiment. In 1st Embodiment, it is a flowchart which shows the control content of the timer interruption process (sub) which a sub control part performs. In 2nd Embodiment, it is a flowchart which shows the control content of the privilege provision process which a main control part performs. In 2nd Embodiment, it is a flowchart which shows the control content of the timer interruption process (sub) which a sub control part performs. In 2nd Embodiment, it is a flowchart which shows the control content of the indication production preparation process which a sub control part performs. In 2nd Embodiment, it is a flowchart which shows the control content of the effect determination process which a sub control part performs. It is a flowchart which shows the control content of the initial setting process which a main control part performs at the time of starting. It is a flowchart which shows the control content of the initial setting process which a main control part performs at the time of starting. It is a flowchart which shows the control content of the setting change process which a main control part performs. It is a flowchart which shows the control content of the setting change process which a main control part performs. It is a flowchart which shows the control content of the main process which a main control part performs. It is a flowchart which shows the control content of the timer interruption process (main) which a main control part performs for every fixed interval. It is a flowchart which shows the control content of the timer interruption process (main) which a main control part performs for every fixed interval. It is a flowchart which shows the control content of the power interruption process (main) performed according to having detected the power interruption in the timer interruption process (main). It is a block diagram which shows the structure of a microcomputer. It is explanatory drawing which shows the conditions which a microcomputer does not start.

[First Embodiment]
[Slot machine configuration example]
An embodiment of a slot machine to which the present invention is applied will be described with reference to the drawings. As shown in FIG. 1, a slot machine 1 of the present embodiment includes a housing 1a having an open front surface and a side of the housing 1a. And a front door 1b pivotally supported at the end.

  Inside the casing 1a of the slot machine 1 of the present embodiment, as shown in FIG. 2, reels 2L, 2C, 2R (hereinafter, left reel, middle reel, right reel) in which a plurality of types of symbols are arranged on the outer periphery are arranged. ) Are juxtaposed in the horizontal direction, and as shown in FIG. 1, three consecutive symbols out of the symbols arranged on the reels 2L, 2C, 2R can be seen from the see-through window 3 provided on the front door 1b. Are arranged as follows.

  As shown in FIG. 3, “red 7”, “blue 7”, “white 7”, “BAR”, “watermelon”, “cherry a”, “cherry” are respectively provided on the outer peripheral portions of the reels 2L, 2C, 2R. A plurality of identifiable symbols such as “b”, “bell”, “replay a”, “replay b”, and “plum” are drawn in a predetermined order. The symbols drawn on the outer peripheries of the reels 2L, 2C, and 2R are displayed in upper, middle, and lower three stages in the see-through window 3 provided at the approximate center of the front door 1b. In the following, “red 7”, “blue 7” and “white 7” may be collectively referred to as “7”, and “cherry a” and “cherry b” may be simply referred to as “cherry”. is there. Hereinafter, when it is not necessary to distinguish between “replay a” and “replay b”, they may be simply referred to as “replay”.

  The reels 2L, 2C, and 2R are rotated by reel motors 32L, 32C, and 32R (see FIG. 4) provided in correspondence with each other, so that the symbols of the reels 2L, 2C, and 2R are continuous with the see-through window 3. On the other hand, when the reels 2L, 2C, and 2R are stopped from rotating, three consecutive symbols are derived and displayed on the fluoroscopic window 3 as display results.

  Inside the reels 2L, 2C, and 2R, reel sensors 33L, 33C, and 33R that detect the reel reference position for each of the reels 2L, 2C, and 2R, and a reel LED 55 that irradiates the reels 2L, 2C, and 2R from the back side. And are provided. The reel LED 55 includes 12 LEDs corresponding to three consecutive symbols of the reels 2L, 2C, and 2R, and can irradiate each symbol independently.

  A display area 51a of a liquid crystal display 51 (see FIG. 1) is disposed at a position on the front side (player side) of each reel 2L, 2C, 2R of the front door 1b. The liquid crystal display 51 has a transmissive liquid crystal panel in a state where no voltage is applied to the liquid crystal element, and the transmissive area 51b corresponding to the transmissive window 3 of the display area 51a and the transmissive window 3 are interposed. Thus, the reels 2L, 2C, and 2R can be visually recognized from the player side. In addition, a light guide plate (not shown) for irradiating the display area 51a from the back surface side is provided on the back surface of the display area 51a, and the transmissive area 51b of the display area 51a is excluded from the back surface. A concealing member (not shown) for concealing the inside is provided in the region. The liquid crystal display 51 is a display device that can change the display mode by controlling the liquid crystal element in either a state in which light irradiated by the light guide plate is allowed to pass or a state in which the light is not allowed to pass through.

  As shown in FIG. 1, on the front door 1b, there are a medal insertion portion 4 into which medals can be inserted, a medal payout exit 9 from which medals are paid out, and credits (the number of medals stored as a player's own game value). In the range, the maximum bet number among the specified number of bets determined according to the gaming state (in this embodiment, 3 is defined as the defined number of RT0 to RT4 described later, and 2 is defined as the defined number of RBs). The MAXBET switch 6 that is operated when setting the medals, and the medals stored as credits and the medals used for setting the bet amount are settled (the medals used for setting the credit and bet number are returned) Adjusting switch 10 that is operated when starting the game, start switch 7 that is operated when starting the game, and stop that is operated when stopping the rotation of the reels 2L, 2C, and 2R. Switch 8L, 8C, 8R, Produce switch 56 for use in the effect are provided operable by the player.

  In the present embodiment, among the three reels 2L, 2C, and 2R that have started to rotate, the reel that stops first is referred to as a first stop reel, and the stop is referred to as a first stop. Similarly, the reel that stops second is called the second stop reel, the stop is called second stop, the reel that stops third is called the third stop reel, and the stop is the third stop. Alternatively, it is called final stop.

  Further, as shown in FIG. 1, the front door 1b shows a credit indicator 11 for displaying the number of medals stored as credits, the number of medals paid out due to the occurrence of a winning, and the contents when an error occurs. A game auxiliary indicator 12 that displays an error code, information that can identify the stop order of reels by navigation notification described later, and the like, 1 BETLED 14 that notifies that a bet number is set, and a bet number 2BETLED 15 for informing that 2 is set by lighting, 3BETLED 16 for informing that 3 bets have been set, by lighting, an insertion request LED 17 for informing that a medal can be inserted, and a start switch 7 A start valid LED 18 for indicating that the game start operation by the operation is valid by lighting, a weight ( A waiting LED 19 that lights up to indicate that the reel has started rotating since a certain period of time has not elapsed since the start of the game, and lights up to indicate that a replay game to be described later is in progress. A game display unit 13 provided with the LED 20 during replay is provided.

  Inside the MAXBET switch 6, there is provided a BET switch valid LED 21 (see FIG. 4) for notifying that the setting operation of the bet amount by the operation of the MAXBET switch 6 is valid, and stop switches 8L, 8C, The left, middle, and right stop valid LEDs 22L, 22C, and 22R (see FIG. 4) are provided inside the 8R to notify that the reel stop operation by the corresponding stop switches 8L, 8C, and 8R is valid by lighting. It has been.

  Inside the front door 1b, as shown in FIG. 2, a reset switch 23 for detecting a reset operation for releasing an error state to be described later and a stop state to be described later by a predetermined key operation, and changing a set value to be described later A set value display 24 that displays the set value at that time during confirmation of the set value or during the confirmation of the set value, the game progresses until a reset operation is performed at a predetermined trigger (for example, at the end of BB described later) A stop switch 36a for selecting the validity / invalidity of the stop function controlled to a controlled state), automatic settlement processing (for example, at the end of the BB), a medal stored as a credit as a player Automatic settlement switch 36b for selecting whether the automatic settlement function is controlled to be settled (returned regardless of the operation) or the flow path of medals inserted from the medal insertion section 4 a flow path switching solenoid 30 for selectively switching to either a hopper tank 34a (see FIG. 2), which will be described later, or the medal payout exit 9 side, which is provided inside a, and is inserted from the medal insertion unit 4 and A medal selector 29 having an insertion medal sensor 31 for detecting medals flowing down to the tank 34a side, and a door open detection switch 25 (see FIG. 4) for detecting the open state of the front door 1b are provided.

  In the housing 1a, as shown in FIG. 2, the reel reference positions of the reels 2L, 2C, and 2R, the reel motors 32L, 32C, and 32R (see FIG. 4), and the reels 2L, 2C, and 2R are respectively shown. A reel unit 2 comprising detectable reel sensors 33L, 33C, 33R (see FIG. 4), an external output board 1000 (see FIG. 4) for outputting an external output signal, and a medal inserted from the medal insertion unit 4 are stored. Hopper tank 34a, a hopper motor 34b for paying out medals stored in the hopper tank 34a from the medal payout opening 9 (see FIG. 4), and a payout sensor 34c for detecting the medals paid out by driving the hopper motor 34b (see FIG. 4). A hopper unit 34 and a power supply box 100 are provided.

  On the side of the hopper unit 34, an overflow tank 35 is provided for storing medals overflowing from the hopper tank 34a. Inside the overflow tank 35, a full tank sensor 35a (see FIG. 4) is provided for detecting that the number of stored medals exceeds a predetermined amount, that is, the overflow tank 35 is full.

  As shown in FIG. 2, a function key switch 37 for switching to a setting change state or a setting confirmation state is provided on the front surface of the power supply box 100, and functions as a reset switch for canceling an error state or a stop state in normal times. In the setting change state, a reset / setting switch 38 that functions as a setting switch for changing a setting value of a winning probability (outtake rate) of internal lottery described later, and a power source that is operated when turning on / off the power source A switch 39 is provided.

  The power supply box 100 is provided inside the housing 1a, and the front door 1b can be opened by a predetermined key operation held by a store clerk or the like. The set key switch 37, the reset / setting switch 38, and the power switch 39 are operated only by a person such as a store clerk who has the key, and cannot be operated by the player. The same applies to the reset switch 23 detected by a predetermined key operation. In particular, since the setting key switch 37 requires further key operation after the front door 1b is opened by key operation, only the store clerk possessing the key for operating the setting key switch 37 among the game store clerk. Operation is possible.

  When a game is played in the slot machine 1 of the present embodiment, first, medals are inserted from the medal insertion unit 4 or a bet number is set using credits. To use the credit, the MAXBET switch 6 may be operated. When a predetermined number of bets determined according to the gaming state are set, the winning line LN (see FIG. 1) becomes valid, and the operation of the start switch 7 is valid, that is, the state where the game can be started. Become. In the present embodiment, three bets are defined as a specified number of bets in RT0 to 4 described later, and two bets are determined as a specified number of bets in RB described later. When the bet number is set, the winning line LN becomes valid. In addition, when a medal is inserted exceeding the maximum number out of the prescribed number corresponding to the gaming state, the amount is added to the credit.

  The winning line is a line that is set to determine whether a combination of symbols displayed on the perspective windows 3 of the reels 2L, 2C, and 2R is a winning symbol combination. In this embodiment, as shown in FIG. 1, only the winning line LN set across the symbols arranged in the horizontal direction in the middle stage of the reel 2L, the middle stage of the reel 2C, the middle stage of the reel 2R, that is, the middle stage, is used as the winning line. It has been established. In the present embodiment, only one winning line is applied, but a plurality of winning lines may be applied.

  In this embodiment, invalid lines LM1 to LM1 are set apart from the winning line LN in order to make it easy to recognize that the winning line LN has a combination of symbols constituting the winning line. The invalid lines LM1 to LM4 are not determined based on the combination of symbols arranged in the invalid lines LM1 to LM4. When the combination of symbols constituting a specific prize is arranged on the winning line LN, the invalid line is displayed. When a combination of symbols (for example, bell-bell-bell) that is awarded when the winning line LN is aligned with any of the LM1 to LM4 is arranged, the symbols constituting a specific winning in the winning line LN It is easy to recognize that the combination is complete. In the present embodiment, as shown in FIG. 1, the upper stage of the reel 2L, the upper stage of the reel 2C, the upper stage of the reel 2R, that is, the invalid line LM1 and the lower stage of the reel 2L, which are set across the symbols arranged horizontally in the upper stage. , The lower stage of the reel 2C, the lower stage of the reel 2R, that is, the invalid line LM2 set across the symbols arranged horizontally in the lower stage, the upper stage of the reel 2L, the middle stage of the reel 2C, the lower stage of the reel 2R, that is, the lower side There are four types of invalid lines LM3 set across straddling symbols LM3, lower stage of reel 2L, middle stage of reel 2C, upper stage of reel 2R, that is, invalid line LM4 set straddling to the right. It is defined as.

  In this embodiment, as a winning combination, when a predetermined symbol combination (for example, “Bell-Watermelon-Cherry b” in FIG. 7 described later) is determined as a winning combination, In addition, a combination of symbols that becomes an index that is more easily recognized than the predetermined symbol combination in any of the invalid lines LM1 to LM4 when the predetermined symbol combination is aligned (for example, “watermelon-watermelon-watermelon” in FIG. 7 described later). As a result, a combination that can be seen as having won a prize by a combination of symbols arranged in any of the invalid lines LM1 to LM4 is included. Hereinafter, a combination of symbols that is aligned with any of the invalid lines LM1 to LM4 when a predetermined symbol combination is aligned with the winning line LN is referred to as a symbol combination serving as an index, and constitutes a symbol combination serving as an index. The symbol is called an index symbol.

  When the start switch 7 is operated in a state where the game can be started, the reels 2L, 2C, and 2R rotate, and the symbols of the reels 2L, 2C, and 2R continuously vary. When any one of the stop switches 8L, 8C, 8R is operated in this state, the rotation of the corresponding reels 2L, 2C, 2R is stopped, and the display result is derived and displayed on the fluoroscopic window 3.

  Then, when all the reels 2L, 2C, 2R are stopped, one game is completed, and a predetermined symbol combination (hereinafter also referred to as a winning combination) is displayed on the reels 2L, 2C, 2R on the winning line LN. If the game stops as a result, a winning occurs, and a predetermined number of medals are given to the player and added to the credit. Further, when the credit reaches the upper limit (50 in this embodiment), medals are paid out directly from the medal payout opening 9 (see FIG. 1). In addition, when the combination of symbols accompanying the transition of the gaming state on the winning line LN is stopped as a display result of each reel 2L, 2C, 2R, the gaming state according to the combination of symbols is shifted. .

  In the present embodiment, the game starts when the operation of the start switch 7 is detected in a state where the operation of the start switch 7 is valid, and the game ends when all the reels are stopped. Further, one unit of control (game control) for executing a game starts when all the controls associated with the end of the previous game are completed, and when all the controls associated with the end of the game are completed. finish.

  Further, in this embodiment, a configuration using three reels is illustrated, but a configuration using only one reel, a configuration using two reels, a configuration using four or more reels may be used. In the configuration using two or more reels, a winning determination may be made based on a combination of display results derived for all two or more reels. In the present embodiment, the variable display device is configured by physical reels, but the variable display device may be configured by an image display device such as a liquid crystal display.

  Further, in the slot machine 1 according to the present embodiment, after the game is started and the reels 2L, 2C, and 2R are rotated and the symbols start to change, any one of the stop switches 8L, 8C, and 8R is operated. When this is done, the rotation of the reels corresponding to the stop switches 8L, 8C, 8R is stopped, and the symbols are stopped and displayed. The maximum stop delay time from the operation of the stop switches 8L, 8C, 8R to the stop of the rotation of the corresponding reels 2L, 2C, 2R is 190 ms (milliseconds).

The reels 2L, 2C and 2R rotate 80 times per minute, and 80 × 21 (the number of symbols per reel) = 1680 frames, so the maximum of 4 symbols is drawn in 190 ms. Will be able to. In other words, the symbols that can be selected as the stop symbols are the symbols that are displayed when the stop switches 8L, 8C, and 8R are operated, and the symbols that are four frames ahead of them, for a total of five symbols.

  For this reason, for example, when any one of the stop switches 8L, 8C, 8R is operated and the symbol displayed on the lower stage of the reel corresponding to the stop switch is used as a reference, the symbol from the symbol to four frames ahead is used. Since the symbols can be displayed in the lower row, in each of the reels 2L, 2C, 2R, when any one of the stop switches 8L, 8R is operated, the symbol displayed in the middle row of the reel corresponding to the stop switch. The symbols arranged within 5 frames including can be displayed on the winning line.

  Hereinafter, the reels 2L, 2C, and 2R may be simply referred to as reels unless it is necessary to distinguish between them. Further, the reel 2L may be referred to as a left reel, the reel 2C as a middle reel, and the reel 2R as a right reel. Further, an operation for stopping the reels 2L, 2C, 2R by operating the stop switches 8L, 8C, 8R may be referred to as a stop operation.

  FIG. 4 is a block diagram showing a configuration of the slot machine 1. As shown in FIG. 4, the slot machine 1 is provided with a game control board 40, an effect control board 90, and a power supply board 101. The game state is controlled by the game control board 40, and the game state is controlled by the effect control board 90. The production according to the control is controlled, and the power supply board 101 generates the drive power for the electrical components constituting the slot machine 1 and supplies them to each part.

  The power supply board 101 is supplied with AC100V power from the outside, and from this AC100V power supply, a DC voltage necessary for driving electrical components constituting the slot machine 1 is generated, and the game control board 40 and the game control board 40 are generated. It is supplied to the production control board 90 connected through the. The power supply line for supplying power to the effect control board is directly connected from the power supply board 101 to the effect control board 90 without going through the game control board 40, and the power supply board 101 directly supplies power to the effect control board 90. May be supplied.

  Further, the above-described hopper motor 34b, payout sensor 34c, full sensor 35a, setting key switch 37, reset / setting switch 38, and power switch 39 are connected to the power supply board 101.

  On the game control board 40, the above-described MAXBET switch 6, start switch 7, stop switches 8L, 8C, 8R, settlement switch 10, reset switch 23, stop switch 36a, automatic settlement switch 36b, insertion medal sensor 31, door open The detection switch 25 and reel sensors 33L, 33C, and 33R are connected, and the above-described payout sensor 34c, full sensor 35a, setting key switch 37, and reset / setting switch 38 are connected via the power supply board 101. Detection signals from these connected switches are input.

  Further, the game control board 40 includes the credit indicator 11, the game auxiliary indicator 12, 1-3 BET LEDs 14-16, the insertion request LED 17, the start valid LED 18, the waiting LED 19, the replaying LED 20, the BET switch valid LED 21, the left The middle and right stop valid LEDs 22L, 22C and 22R, the set value display 24, the flow path switching solenoid 30, the reel motors 32L, 32C and 32R are connected, and the hopper motor 34b described above is connected via the power supply board 101. These electrical components are connected, and are driven based on control of a main control unit 41 (described later) mounted on the game control board 40.

  The game control board 40 includes a main control unit 41, a control clock generation circuit 42, a random number clock generation circuit 43, a switch detection circuit 44, a motor drive circuit 45, a solenoid drive circuit 46, an LED drive circuit 47, and a power interruption detection circuit. 48 and a reset circuit 49 are mounted.

  The main control unit 41 performs processing related to the progress of the game, and directly or indirectly controls each unit of the control circuit mounted on the game control board 40.

  The control clock generation circuit 42 generates a control clock CCLK serving as an oscillation signal having a predetermined frequency outside the main control unit 41. The control clock CCLK generated by the control clock generation circuit 42 is supplied to the clock circuit 502 shown in FIG. The random number clock generation circuit 43 generates a random number clock RCLK that is an oscillation signal having a predetermined frequency different from the oscillation frequency of the control clock CCLK, outside the main control unit 41. The random number clock RCLK generated by the random number clock generation circuit 43 is supplied to the random number circuits 508a and 508b shown in FIG.

  The switch detection circuit 44 takes in detection signals input from switches connected directly to the game control board 40 or via the power supply board 101 and transmits them to the main control unit 41. The motor drive circuit 45 transmits the motor drive signal (stepping motor phase signal) output from the main control unit 41 to the reel motors 32L, 32C, and 32R. The solenoid drive circuit 46 transmits the solenoid drive signal output from the main control unit 41 to the flow path switching solenoid 30. The LED drive circuit 47 transmits the LED drive signal output from the main control unit 41 to various displays and LEDs connected to the game control board 40. The power interruption detection circuit 48 monitors the power supply voltage supplied to the slot machine 1 and outputs a voltage drop signal indicating that to the main control unit 41 when a voltage drop is detected. The reset circuit 49 provides a system reset signal to the main control unit 41 in a state where the power is unstable, such as when the power is turned on or when the power is turned off.

  FIG. 5 shows a configuration example of the main control unit 41 mounted on the game control board 40. The main control unit 41 shown in FIG. 5 is a one-chip microcomputer, and includes an external bus interface 501, a clock circuit 502, a verification block 503, a specific information storage circuit 504, an arithmetic circuit 505, and a reset / interrupt. A controller 506, a CPU (Central Processing Unit) 41a, a ROM (Read Only Memory) 41b, a RAM (Random Access Memory) 41c, a free-run counter circuit 507, random number circuits 508a and 508b, a timer circuit 509, An interrupt controller 510, a parallel input port 511, a serial communication circuit 512, a parallel output port 513, and an address decoding circuit 514 are provided.

  The reset / interrupt controller 506 is for controlling various resets and interrupt requests generated inside or outside the main control unit 41.

  The reset / interrupt controller 506 includes an out-of-designated area prohibition (IAT) circuit 506a and a watchdog timer (WDT) 506b. The IAT circuit 506a is a circuit that monitors whether the user program is correctly executed in the designated area, and has a function of outputting an IAT generation signal when it is detected that the user program is executed outside the designated area. The watchdog timer 506b has a function of generating a timeout signal for each set period.

  The external bus interface 501 is a bus interface having an interface function between an external bus and an internal bus of a chip constituting the main control unit 41, an address bus, a data bus, and a direction control function of each control signal.

  The clock circuit 502 is a circuit that generates the internal system clock SCLK by, for example, dividing the control clock CCLK by two.

  The verification block 503 is connected to an external verification machine and has a function of performing chip verification. The unique information storage circuit 504 is a circuit that stores a plurality of types of unique information that is internal information of the main control unit 41. The arithmetic circuit 505 is a circuit that performs multiplication and division.

  The CPU 41a is a control CPU that executes game control in the slot machine 1 by executing a user program (game control processing program for game control) based on the control code read from the ROM 41b. When such game control is executed, the CPU 41a reads fixed data from the ROM 41b, the CPU 41a writes various fluctuation data to the RAM 41c and temporarily stores them, and the CPU 41a is temporarily stored in the RAM 41c. A variable data reading operation for reading out various variable data being received, a receiving operation in which the CPU 41a receives input of various signals from the outside of the main control unit 41 via the external bus interface 501, the parallel input port 511, the serial communication circuit 512, etc. However, a transmission operation for outputting various signals to the outside of the main control unit 41 via the external bus interface 501, the serial communication circuit 512, the parallel output port 513, and the like is also performed.

  The ROM 41b stores a control code indicating a user program (game control processing program for game control), fixed data, and the like.

  The RAM 41c provides a work area for game control. Here, at least a part of the RAM 41c may be a backup RAM backed up by a backup power source. That is, even if the power supply to the slot machine 1 is stopped, at least a part of the contents of the RAM 41c is stored for a predetermined period.

  As the free-run counter circuit 507, four channels of 8-bit free-run counters are mounted.

  The random number circuits 508a and 508b are circuits that generate numerical data that is a random value having a predetermined update range, such as an 8-bit random number or a 16-bit random number. In this embodiment, the hardware random number generated by the 16-bit random number circuit 508b among the random number circuits 508a and 508b is used as a random number for internal lottery described later.

  The timer circuit 509 is an 8-bit programmable timer, and the main control unit 41 includes three channels of 8-bit counters as the timer circuit 509. In the present embodiment, it is possible to perform a real-time interrupt request and time measurement by using a timer circuit 509 and setting by a user program.

  The interrupt controller 510 is a circuit that controls an external interrupt request from the PI5 / XINT terminal and an interrupt request from a built-in peripheral circuit (for example, serial communication circuit 512, random number circuits 508a and 508b, timer circuit 509). is there.

  The parallel input port 511 incorporates an 8-bit wide input-only port (PIP). Further, the parallel output port 513 provided in the main control unit 41 shown in FIG. 5 incorporates an output-only port (POP) having an 11-bit width.

  The serial communication circuit 512 is a circuit that performs asynchronous serial communication in input / output with respect to the outside. The main control unit 41 includes, as the serial communication circuit 512, a 1-channel circuit for both transmission and reception and a 3-channel circuit for transmission only.

  The address decoding circuit 514 is a circuit for decoding each functional block in the main control unit 41 and a chip select signal that is a decoding signal for an external device. In response to the chip select signal, the internal circuit of the main control unit 41 or the external device serving as a peripheral device is selectively operated effectively and can be accessed from the CPU 41a.

  In the present embodiment, the main control unit 41 transmits various commands to the sub control unit 91 via the parallel output port 513. A command transmitted from the main control unit 41 to the sub control unit 91 is sent in only one direction, and no command is sent from the sub control unit 91 toward the main control unit 41. In this embodiment, the command is transmitted to the sub-control unit 91 via the parallel output port 513, that is, the command is transmitted as a parallel signal, but via the serial communication circuit 512. A configuration in which a command is transmitted to the sub control unit 91, that is, a configuration in which the command is transmitted as a serial signal may be employed.

  The main control unit 41 also receives detection states of various switches connected to the game control board 40 from the parallel input port 511. The main control unit 41 executes basic processing that shifts in stages according to the detection states of various switches input from the parallel input port 511.

  Further, the main control unit 41 can execute an interrupt process by interrupting the basic process when an interrupt occurs. In the present embodiment, a timer interrupt process (main), which will be described later, is executed at a certain time interval (about 0.56 ms in the present embodiment) when a timeout occurs in the timer circuit 509.

  The main control unit 41 is set to prohibit other interrupts during the execution of the interrupt process, and when a plurality of interrupts occur at the same time, the main control unit 41 prioritizes according to a predetermined order. An interrupt to be executed is set. If another interrupt factor occurs during the execution of the interrupt process and the interrupt factor continues even after the interrupt process is completed, a new interrupt will occur at that point. It will be.

  The main control unit 41 repeatedly loops the process according to the control state until the detection state of the various switches connected to the game control board 40 changes as a basic process, and changes the detection state of the various switches. Execute a process that moves in stages. Further, the main control unit 41 executes a timer interrupt process (main) at regular time intervals (about 0.56 ms in the present embodiment). In addition, the execution interval of the timer interrupt process (main) is set to a time longer than the sum of the time required to complete the repeated process according to the control state in the basic process and the execution time of the timer interrupt process (main) Therefore, the process that is repeated according to the control state between the current and next timer interrupt processes (main) is completed at least once.

  An effect switch 56 is connected to the game control board 40, and a detection signal of the effect switch 56 is input.

  Further, the effect control board 90 is connected with effect devices such as a liquid crystal display 51, an effect LED 52, speakers 53 and 54, and a reel LED 55. These effect devices are mounted on the effect control board 90, which will be described later. It is driven based on control by the sub-control unit 91.

  In the present embodiment, the sub-control unit 91 mounted on the effect control board 90 performs output control of effect devices such as the liquid crystal display 51, effect effect LEDs 52, speakers 53 and 54, and reel LEDs 55. However, in addition to the sub-control unit 91, an output control unit that directly controls the output of the effect device is mounted on the effect control board 90 or another board, and the sub-control unit 91 is based on a command from the main control unit 41. The output control unit may determine the output pattern of the effect device, and the output control unit may control the output of the effect device based on the output pattern determined by the sub control unit 91. In such a configuration, the sub control unit 91 and the output control may be performed. The output control of the rendering device is performed by both of the units.

  Further, in the present embodiment, the liquid crystal display 51, the effect effect LED 52, the speakers 53 and 54, and the reel LED 55 are exemplified as the effect device, but the effect device is not limited to these, for example, a mechanically driven display. A device or a mechanically driven item may be applied as the effect device.

  The effect control board 90 is composed of a microcomputer having a sub CPU 91a, ROM 91b, RAM 91c, and I / O port 91d, and a liquid crystal display connected to the effect control board 90, a sub control unit 91 for effect control. 51, a display control circuit 92 for performing display control, an LED driving circuit 93 for controlling driving of the effect LED 52 and the reel LED 55, an audio output circuit 94 for controlling audio output from the speakers 53, 54, when the power is turned on or from the sub CPU 91a The reset circuit 95 that gives a reset signal to the sub CPU 91a when the initialization command is not input for a certain period of time, the switch detection circuit 96 that detects the detection signal input from the switches connected to the effect control board 90, date information and time Clock device 97 for outputting time information including information, slot machine 1 The power supply voltage to be supplied is monitored, and when a voltage drop is detected, a power failure detection circuit 98 that outputs a voltage drop signal to that effect to the sub CPU 91a, and other circuits are mounted. In response to the command transmitted from the game control board 40, the CPU 91a performs various controls for performing an effect, and directly or indirectly controls each part of the control circuit mounted on the effect control board 90.

  The reset circuit 95 has a lower voltage for releasing the reset signal than the reset circuit 49 that gives the system reset signal to the main control unit 41 in the game control board 40. When the power is turned on, the sub control unit 91 It starts at an earlier stage than the unit 41. On the other hand, the power interruption detection circuit 98 has a voltage that outputs a voltage drop signal lower than the power interruption detection circuit 48 that outputs a voltage drop signal to the main control unit 41 in the game control board 40. The sub control unit 91 detects a power failure at a later stage than the main control unit 41, and performs a power interruption process (sub) described later.

  Similar to the main control unit 41, the sub control unit 91 has an interrupt function, generates an interrupt when receiving a command from the main control unit 41, and acquires a command transmitted from the main control unit 41. Execute command reception interrupt processing to be stored in the buffer. Further, the sub control unit 91 executes an interrupt process (sub), which will be described later, by generating an interrupt every time the input number of system clocks reaches a certain number, that is, every certain time interval (about 2 ms).

  Also, unlike the main control unit 41, the sub control unit 91 interrupts the process even when the timer interrupt process (sub) is being executed when an interrupt is generated based on the reception of the command. The command reception interrupt process is executed at the same time, and the command reception interrupt process is executed with the highest priority even if interrupts that trigger the timer interrupt process (sub) occur at the same time.

  The sub-control unit 91 is also supplied with backup power at the time of a power failure, and the data stored in the RAM 91c is held while the backup power is supplied.

  In the slot machine 1 of the present embodiment, the medal payout rate changes according to the set value. Specifically, the medal payout rate is changed by using a winning probability corresponding to the set value in a lottery that affects the advantage to the player, such as an internal lottery, a navigation stock lottery, and an extra lottery to be described later. The set value is composed of 6 levels of 1 to 6, with 6 being the highest payout rate and the payout rate being lower as the value is decreased in the order of 5, 4, 3, 2, 1. That is, when 6 is set as the set value, the advantage is highest for the player, and as the value decreases in order of 5, 4, 3, 2, 1, the advantage decreases stepwise.

  In order to change the setting value, it is necessary to turn on the power of the slot machine 1 after the setting key switch 37 is turned on. When the setting key switch 37 is turned on and the power is turned on, the setting value read from the RAM 41c is displayed as a display value on the setting value display 24, and the setting value can be changed by operating the reset / setting switch 38. Transition to the setting change state. When the reset / setting switch 38 is operated in the setting change state, the display value displayed on the set value display 24 is updated one by one (when the set value 6 is further operated, the set value 1 is set. Return). When the start switch 7 is operated, the display value is determined as the set value. When the setting key switch 37 is turned off, the determined display value (setting value) is stored in the RAM 41c of the main control unit 41, and the state shifts to a state in which the game can proceed.

  In addition, when the setting key switch 37 is turned on and the power is turned on, the configuration may be changed to the setting change state on condition that the opening of the front door 1b is detected by the door opening detection switch 25. By setting it as such a structure, it can prevent that a setting change will be carried out illegally in the state which the front door 1b is not open | released. Further, in the configuration that shifts to the setting change state on the condition that the opening of the front door 1b is detected, the door opening detection switch 25 does not detect the opening of the front door 1b after shifting to the setting change state. However, it is preferable to maintain the setting change state, so that even if the front door 1b is temporarily closed during the setting change, the operation for changing to the setting change state is not required again, and the setting change state is required. Operation is not complicated. In addition, after shifting to the setting change state, when the setting key switch 37 is turned off after the start switch 7 is operated and the set value is confirmed, the door opening detection switch 25 detects the opening of the front door 1b. On the condition that the setting change state is terminated, it may be configured to shift to a state in which the game can proceed. Even in such a configuration, the setting change is illegally performed when the front door 1b is not opened. Can be prevented.

  In order to check the set value, after the game is over, the setting key switch 37 may be turned on in a state where the bet amount is not set. When the setting key switch 37 is turned on in such a situation, the setting value read out from the RAM 41c is displayed on the setting value display 24, thereby shifting to a setting confirmation state in which the setting value can be confirmed. In the setting confirmation state, the game cannot be progressed, and by setting the setting key switch 37 to the off state, the setting confirmation state is ended and the state in which the game can proceed is returned.

  After the game, the setting is made on the condition that the opening of the front door 1b is detected by the door opening detection switch 25 when the setting key switch 37 is turned on with no betting number set. A configuration for shifting to the confirmation state may be adopted, and by adopting such a configuration, it is possible to prevent the setting value from being illegally confirmed without the front door 1b being opened. Further, in the configuration that shifts to the setting confirmation state on the condition that the opening of the front door 1b is detected, the door opening detection switch 25 does not detect the opening of the front door 1b after the transition to the setting confirmation state. However, it is preferable to maintain the setting confirmation state, so that even if the front door 1b is temporarily closed during the setting confirmation, the operation for shifting to the setting confirmation state is not required again, and the setting confirmation state is required. Operation is not complicated. In addition, after shifting to the setting confirmation state, when the set key switch 37 is turned off after the set value is confirmed by operating the start switch 7, the door opening detection switch 25 detects the opening of the front door 1b. On the condition that the setting confirmation state is terminated, it may be configured to return to a state in which the game can proceed. Even in such a configuration, the setting value is illegally set when the front door 1b is not opened. It can be prevented from being confirmed.

  In the slot machine 1 of the present embodiment, the main control unit 41 determines whether or not a voltage drop signal from the power interruption detection circuit 48 is detected every time the timer interrupt process (main) is executed. When the determination process is performed and it is determined that the voltage drop signal is detected in the power failure determination process, a power interruption process (main) for setting data for determining whether or not the data in the RAM 41c is normal at the next return is performed. Run.

  Then, the main control unit 41 returns the processing state of the main control unit 41 to the state before the power interruption based on the data stored in the RAM 41c on the condition that the data in the RAM 41c is normal at the time of activation. However, if the RAM 41c data is not normal, it is determined that the RAM is abnormal, and the RAM abnormal error code is set in the register to control the RAM abnormal error state, thereby disabling the progress of the game.

  Further, the sub control unit 91 also determines whether or not the voltage drop signal from the power interruption detection circuit 98 is detected in the timer interruption process (sub), and when it is determined that the voltage drop signal is detected, A power interruption process (sub) for setting data for determining whether or not the data in the RAM 91c is normal at the next return is executed.

  Then, the sub-control unit 91 returns the processing state of the sub-control unit 91 to the state before the power interruption based on the data stored in the RAM 91c on the condition that the data of the RAM 91c is normal at the time of activation. However, if the data in the RAM 91c is not normal, it is determined that the RAM is abnormal, and the RAM 91c is initialized. In this case, unlike the main control unit 41, only the RAM 91c is initialized, and the performance is not disabled.

  In addition, even when it is determined that the data in the RAM 91c is normal at the time of activation, the sub control unit 91 activates when receiving a setting command (described later) indicating that the setting change state has been entered from the main control unit 41. Even when a later-described return command or setting command indicating that the control state of the main control unit 41 has returned is not received even after a certain period of time has elapsed, the RAM 91c is initialized. In this case, the execution of the performance is not disabled only by initializing the RAM 91c.

[About initialization]
Next, initialization of the RAM 41c of the main control unit 41 will be described. The storage area of the RAM 41c of the main control unit 41 is divided into an important work, a non-saved work, a general work, a special work, an unused area, and a stack area.

  In this embodiment, the main control unit 41 stores data in the RAM 41c when a RAM abnormality error occurs, when the setting key switch 37 is activated with the setting key switch 37 turned on, when the BB is completed, and when the setting key switch 37 is activated with the setting key switch 37 turned off. When not being destroyed, when five initialization conditions at the end of one game are satisfied, four types of initializations that are initialized in accordance with each initialization condition are performed.

  Initialization 1 is a setting key switch 37 that is on at the time of startup, and is an initialization that is performed before the transition to the setting change state or an initialization that occurs when a RAM error occurs. In the storage area of the RAM 41c, areas other than the important work and the special work are initialized. Initialization 2 is initialization performed at the end of the BB. In initialization 2, a general work, an unused area, and an unused stack area in the storage area of the RAM 41c are initialized. Initialization 3 is an initialization performed when the setting key switch 37 is off at the time of startup and the data in the RAM 41c is not destroyed. In the initialization 3, the unsaved work, the unused area, and the The used stack area is initialized. Initialization 4 is initialization performed at the end of one game. In initialization 4, an unused area and an unused stack area in the storage area of the RAM 41c are initialized.

  In this embodiment, initialization 1 is performed before the transition to the setting change state. However, the initialization 1 is performed at the end of the setting change state, or both before the transition to the setting change state and at the end of the setting change state. Anyway.

  The special work includes a game state storage work in which a game state flag indicating a game state is stored and an internal winning flag storage work in which an internal winning flag is stored. Since the special work is not initialized, the game state and the internal winning flag before the setting change are maintained even when the setting is changed.

  In the slot machine 1 of the present embodiment, a specified number of bets that can be set according to the gaming state (RT0 to RT4, RB) (in this embodiment, 3 for RT0-4 and 2 for RB) is determined. Thus, the game can be started on condition that a prescribed number of bets determined according to the gaming state are set. In the present embodiment, the winning line LN is activated when a specified number of bets corresponding to the gaming state are set.

  In this embodiment, when all the reels 2L, 2C, 2R are stopped, the activated pay line is activated (in the case of the present embodiment, all the pay lines are always activated. A winning combination is obtained when a combination of symbols called “combinations” is arranged on the winning line. The combination may be a combination of the same symbols or a combination including different symbols.

  The type of winning combination is determined according to the game state, but it can be roughly divided into a small role with payout of medals and a replay that can start the next game without the need to set the number of bets. There are a game combination and a special combination with a transition to a game state advantageous to the player. Below, a small role and a re-playing role are collectively called a general role.

  In order for winning of each combination determined according to the gaming state to occur, it is necessary to win an internal lottery to be described later and set a winning flag of the combination in the RAM 41c.

  Of the winning flags for each of these combinations, the winning flag for the small role and the re-playing role is valid only in the game in which the flag is set, and is invalid in the next game. It is valid until a combination of combinations permitted by the flag is completed, and is invalid in a game having a combination of combinations permitted. In other words, once the special combination winning flag is won, even if the combination of the combination permitted by the flag cannot be made, the winning flag is not invalidated and is carried over to the next game. It becomes.

[About internal lottery]
Hereinafter, the internal lottery of this embodiment will be described. In the internal lottery, whether or not the main control unit 41 allows the winning of each combination described above before the display results of all the reels 2L, 2C, and 2R are derived (specifically, the start switch 7 At the time of detection). In the internal lottery, first, a random value for internal lottery (an integer from 0 to 65535) is acquired when the start switch 7 is detected. Specifically, the value generated by the random number circuit 508b and stored in the random number value register of the random number circuit 508b is set as the lottery work assigned to the RAM 41c. And, for each combination determined according to the gaming state (RT0-4, RB), each combination determined according to the numerical data stored in the lottery work, the current gaming state, the number of bets and the set value Whether or not winning is permitted is determined according to the number of determination values.

  In the internal lottery, the number of judgment values determined in accordance with the internal lottery target, the current gaming state, and the set value are sequentially assigned to the random number for internal lottery (numerical data stored in the lottery work). When the result of addition overflows, it is determined that the winning combination is won. For this reason, a winning combination will be won with a probability (number of determination values / 65536) according to the number of determination values.

  If a winning combination of any combination is determined, a winning flag corresponding to the combination determined to be winning is set in the internal winning flag storing work assigned to the RAM 41c. The internal winning flag storage work consists of a 2-byte storage area, of which the upper byte is assigned as the special role storing work in which the winning flag for the special role is set, and the lower byte is the winning of the general role It is assigned as a general role storage work for which a flag is set. Specifically, when a special combination is won, a special combination winning flag indicating that the special combination is won is set in the special combination storing work, and the winning flag set in the general combination storing work is cleared. When a general combination is won, a winning flag for the general combination indicating that the general combination is won is set in the general combination storing work. If no winning combination is selected, only the general winning combination work is cleared.

[Reel stop control]
Next, stop control of the reels 2L, 2C, 2R will be described.

  The main control unit 41 refers to the table index and table creation data stored in the ROM 41b when the reel starts to rotate and when the reel stops and the reel that is still rotating still remains. A stop control table is created for each reel that is rotating. When any of the stop switches 8L, 8C, and 8R corresponding to the rotating reel is effectively detected, the stop control table of the corresponding reel is referred to and the slip of the referred stop control table is referred to. Based on the number of frames, control is performed to stop the rotation of the reels 2L, 2C, 2R corresponding to the operated stop switches 8L, 8C, 8R.

  In the table index, index data indicating the start address of the area in which the data for table creation is stored, from the reference address when referring to the table index, according to the setting state of the winning flag by internal lottery (hereinafter referred to as the internal winning state) Differences up to the address where is stored are registered. As a result, a difference corresponding to the internal winning state is acquired, and the corresponding index data can be acquired by adding the difference to the reference address. Even when the winning combinations are different, when the same control is applied, the same address is stored as the index data. In such a case, the same table creation data is referred to. Thus, a stop control table is created.

  The table creation data includes a stop control table indicating the number of sliding frames according to the stop operation position, and an address of the stop control table to be referred to according to the reel stop status.

  The stop control table referred to according to the reel stop status is whether all reels are rotating, only the left reel is stopped, only the middle reel is stopped, only the right reel is stopped, It may vary depending on whether the middle reel is stopped, the left and right reels are stopped, the middle and right reels are stopped, and if any reel is stopped, stop Since there may be differences depending on the stop position of the reels already completed, the address of the stop control table to be referenced for each situation is registered for each rotating reel, and based on the top address of the table creation data, It is possible to specify the address of the stop control table that should be referred to according to the status of the system. And to be able to identify the Do stop control table. Even when the reel stop status and the stopped position of the stopped reel are different, when the same stop control table is applied, the same address may be registered as the address of the stop control table. In such a case, the same stop control table is referred to.

  The stop control table is data that can specify the number of sliding frames for each timing when the stop operation is performed. In the present embodiment, stepping motors that make one turn at a cycle of 336 steps (0 to 335) are used for the reel motors 32L, 32C, and 32R. That is, when the reel motors 32L, 32C, and 32R are driven in 336 steps, the reels 2L, 2C, and 2R make one round. Then, 21 areas (frames) divided every 16 steps (the number of steps that one symbol moves) are defined for one reel, and these areas are areas 0 to 20 from the reel reference position. A number is assigned. On the other hand, the number of symbols arranged on one reel is 21, and symbol numbers 0 to 20 from the reel reference position are assigned to symbols on each reel, so symbols 0 to 20 are assigned to each reel. , Area numbers 0 to 20 are assigned in order. In the stop control table, the number of sliding symbols for each area number is compressed and stored according to a predetermined rule, and the number of sliding symbols for each area number can be acquired by expanding the stop control table. Yes.

  As described above, in the stop control table created by referring to the table index and the table creation data, the region corresponding to each region number corresponds to the region number, and the stop reference position (in this embodiment, the perspective window 3 Sliding frame when an operation of the stop switches 8L, 8C, 8R is detected at a timing (a timing in which the number of steps from the reel reference position is included in the range of the number of steps of each region number). It is a table with each number set.

  Next, the procedure for creating the stop control table will be described. First, at the start of reel rotation, the top address of the table creation data corresponding to the internal winning state of the game is acquired. Specifically, the table index is first referred to, index data corresponding to the internal winning state is obtained, table creation data is identified based on the obtained index data, and all reels are identified from the identified table creation data. The address of the stop control table for each reel corresponding to the state of rotation is acquired, and the stop control table for each reel stored at the acquired address is expanded to generate a stop control table for all reels.

  Further, when any one reel stops or any two reels stop, the index data acquired at the start of reel rotation, that is, the top address of the table creation data corresponding to the internal winning state of the game The table creation data is identified based on the table creation data, and the stop control table address of the unreacted reel corresponding to the stopped reel and the area number of the stop position of the reel is obtained from the identified table creation data. The stop control table for each stored reel is expanded to create a stop control table for the unstopped reels.

  Next, when the main control unit 41 effectively detects any one of the stop switches 8L, 8C, and 8R corresponding to the rotating reel, the control when the display result is derived to the corresponding reel is described. To explain, when any operation corresponding to the rotating reel is detected effectively among the stop switches 8L, 8C, 8R, the stop operation position is based on the number of steps from the reel reference position when the stop operation is detected. The number of sliding symbols corresponding to the area number of the specified stop operation position is acquired by referring to the stop control table of the reel where the stop operation is detected. Then, control is performed to rotate and stop the reel by the number of acquired sliding frames. Specifically, from the number of steps from the reel reference position at the time when the stop operation is detected, the number of steps from the acquired number of sliding frames to the stop is calculated, and the reel is rotated and stopped by the calculated number of steps. Take control. As a result, the area corresponding to the area number that is the stop position ahead of the number of sliding frames from the area corresponding to the area number of the stop operation position where the stop operation is detected is the stop reference position (in this embodiment, the perspective window 3 It will stop in the lower symbol area).

  In the table index of this embodiment, only one address is stored as index data corresponding to one internal winning state in one gaming state, and furthermore, one table creation data contains one reel. Only one address is stored as the address of the storage area of the stop control table corresponding to the stop status (and the stop position of the stopped reel). In other words, table creation data corresponding to one internal winning state in one gaming state and stop control tables corresponding to reel stop states (and stopped positions of stopped reels) are uniquely determined. The stop control table created with reference to is unique for one internal winning state in one gaming state and the reel stop status (and the stop position of the stopped reel). Therefore, when all of the gaming state, the internal winning state, and the reel stop status (and the stop position of the stopped reel) are the same, the reel is based on the same stop control table, that is, the same control pattern. The stop control is performed.

  Further, in the present embodiment, a value of 0 to 4 is determined as the number of sliding frames, and it is possible to stop the reel by drawing in a maximum of 4 symbols after detecting a stop operation. In other words, the stop position of the symbol can be designated from a range of a maximum of 5 frames including the stop operation position where the stop operation is detected. In addition, since it is necessary to move one frame to move the reel for one symbol, it is possible to stop the reel by pulling in a maximum of four symbols after detecting the stop operation. The symbol stop position can be designated from a range of up to five symbols including the operation position.

  In the present embodiment, when any of the winning combinations is won, when the stop operation is performed, the winning combination can be stopped on the winning line in the drawing range of up to 4 frames. If possible, control is performed to align and stop, and the winning combination that has not been won is controlled to be stopped without being aligned in the drawing range of a maximum of 4 frames.

  Also, in this embodiment, when a special role and a small role are won at the same time, such as when a special role is won while the special role has been carried over from before the previous game, when a stop operation is performed In addition, if it is possible to align and stop the small roles that have been elected on the winning line in the drawing range of up to 4 frames, the control is performed to align and stop them, and the winning line can be drawn in up to 4 frames on the winning line. If the winning small role cannot be withdrawn, if the winning combination can be stopped on the winning line with a maximum of 4 draws, it will be controlled. The winning combination that is not won is controlled to be stopped without being aligned in the drawing range of 4 frames. That is, in such a case, priority is given to the control for aligning the small combination on the winning line over the special combination, and the special combination can be won only when the small combination cannot be drawn. In the case where a special combination and a small combination can be withdrawn at the same time, only the small combination is drawn, and the small combination is not aligned on the winning line at the same time as the special combination.

  Also, when a special role and a small role are elected at the same time, priority is given to the control of aligning the special role on the winning line over the small role, and only when the special role cannot be drawn, the small role is placed on the winning line. You may perform control to align.

  Further, in this embodiment, when the special combination and the replaying combination are won at the same time, such as when the replaying combination is won while the special combination has been carried over from before the previous game, the stop operation is performed. In this case, the control is performed so that the symbols of the re-gamer are aligned and stopped on the winning line within a drawing range of up to 4 frames. In this case, the symbols constituting the re-gamer or the symbols constituting the re-gamer to be simultaneously elected are arranged at intervals of 5 symbols or less, that is, within 4 frames, for any of the reels 2L, 2C, and 2R. Since it can always be stopped at any position within the 4-frame pull-in range, if the special combination and the re-playing combination are elected at the same time, the timing of the operation of the stop switches 8L, 8C, 8R by the player Without fail, the re-playing role will always be won. That is, in such a case, the control for aligning the re-games on the winning line has priority over the special game, and the re-games will always win. In the case where the special combination and the re-playing combination can be withdrawn at the same time, only the re-playing combination is drawn in and the special combination is not arranged on the winning line at the same time as the re-playing combination.

  In the present embodiment, the stop control of the reel is performed using the stop control table that can specify the number of sliding frames for each timing at which the stop operation is performed. A configuration that performs stop control by specifying the stop position from the table and stopping the reel at the specified stop position, and searching for a stop position that can be stopped when the stop operation is performed without using the stop control table or the stop position table. A configuration that performs stop control that identifies and stops the reel at the specified stop position, stop control using the stop control table, stop control using the stop position table, and can be stopped without using the stop control table or the stop position table Configuration that uses stop control together by searching and specifying the stop position, configuration that performs stop control by changing part of the stop control table and stop position table, and so on And it may be.

  In the present embodiment, the main control unit 41 rotates the reels whose stop operation has not yet been detected until the operation of the stop switches 8L, 8C, and 8R is detected after the rotation of the reels 2L, 2C, and 2R is started. Continuously, on the condition that the operation of the stop switches 8L, 8C, and 8R is detected, control is performed to stop the display result on the corresponding reel. Even if the reel rotation temporarily stops due to the occurrence of a reel rotation error, the stop operation is still detected until the operation of the stop switches 8L, 8C, and 8R is detected after the reel rotation is restarted. Control is performed to stop the display result of the corresponding reels on the condition that the rotation of the reels that have not been continued is continued and the operation of the stop switches 8L, 8C, and 8R is detected.

  In the present embodiment, the control for stopping the display result on the corresponding reel is performed on the condition that the operation of the stop switches 8L, 8C, and 8R is detected. However, the reel starts to rotate. When a predetermined automatic stop time has elapsed, even if the reel stop operation is not performed, it is assumed that the stop operation has been performed, and automatic stop control is performed to automatically stop each reel. May be. In this case, since the reels are stopped without the player's operation, it is preferable to derive a display result that does not constitute any combination even if any combination is won.

  In the present embodiment, the main control unit 41 counts the game time, which is the time elapsed from the start of reel rotation, every time the reel starts to rotate after the game starts. After a game is over, when a specified number of bets are set by inserting medals, etc., and the game start operation is enabled, the reel start of the previous game is started. If the game time that has started counting from the time is equal to or longer than the specified time (4.1 seconds in the present embodiment), that is, if the specified time has elapsed since the start of reel rotation of the previous game, no wait is generated. At that time, the reel for the game in the game is started to rotate.

  On the other hand, after the end of one game, when a predetermined number of bets are set by inserting medals, etc., and when the game start operation is enabled, the reel rotation of the previous game is started. If the game time that started timing from the time is less than the specified time, that is, if the specified time has not elapsed since the start of reel rotation of the previous game, a wait is generated and the reel starts rotating at that time. First, it waits until the game time that has started timing from the reel rotation start time of the previous game reaches the specified time, and starts rotating the reel when it reaches the specified time.

[About commands]
Next, commands that the main control unit 41 transmits to the sub control unit 91 will be described.

  In the present embodiment, the main control unit 41 sends the inserted control number command, credit command, gaming state command, ART state command, internal winning command, stop order command, freeze command, ART lottery result command to the sub-control unit 91. Reel acceleration information 1 command, reel acceleration information 2 command, stop operation command, sliding frame number command, stop command, game end command, winning number command, payout start command, payout end command, standby command, stop command, error command A plurality of types of commands including a return command, a setting command, a setting confirmation command, a door command, and an operation detection command are transmitted.

  These commands consist of 1-byte type data indicating the command type and 1-byte extension data indicating the command content, and the sub-control unit 91 can determine the command type from the type data.

  The inserted number command is a command that can specify the number of inserted medals, that is, the number of medals used for setting the number of bets, and is a state from the end of the game (after changing the setting) to the start of the game. Or, when a prescribed number of bets is not set, a medal is inserted, or when the bet number is set by operating the MAXBET switch 6. The inserted number command is transmitted when the betting number setting operation is performed, so that it is possible to specify that the betting number setting operation has been performed by receiving the inserted number command.

  The credit command is a command that can specify the number of medals stored as credits, and is a state from the end of the game (after setting change) to the start of the game, and in a state where a predetermined number of bets is set, Sent when a medal is inserted and credits are added.

  The game state command is a command that can specify the game state (RT0 to 4, RB) of the game, and is transmitted when the start switch 7 is operated to start the game.

  The ART state command is a command that can specify whether it is AT, whether it is ART, the number of remaining games until the specified number of games to be described later, the number of remaining games in the precursor period, and the number of remaining games of ART. When the game starts, it is transmitted after the game state command.

  The internal winning command is a command that can specify the internal lottery result, and is transmitted when the start switch 7 is operated to start the game and after the gaming state command is transmitted. The internal winning command is transmitted when the game is started and after the ART state command.

  Since the game state command, the ART state command, and the internal winning command are transmitted when the start switch 7 is operated and the game starts, the game is started by operating the start switch 7 by receiving these commands. Can be specified.

  In addition, the internal winning command can specify that one of the push order bells described later has been won, but which type (left bell, middle bell, right bell) has been won, that is, when the push order bell is won. The stop order for winning the middle bell cannot be specified. In addition, the internal winning command can specify that any of the replays GR1 to 6 described later has been won, but the type in which the replays GR1 to 6 are won, that is, the stop order in which the promoted replay is awarded when the replays GR1 to 6 are won. Cannot be specified. In addition, the internal winning command can specify that any of the replay GRs 11 to 13 to be described later has been won, but which type of the replays GR11 to 13 has been won, that is, when the replays GR11 to 13 are won, The stop order for winning the replay and the stop order for avoiding the falling replay win cannot be specified. In addition, the internal winning command can specify that any of the replay GRs 21 to 26 described later has been won, but the type of the replay GRs 21 to 26 that has been won, that is, when the replay GRs 21 to 26 are won, The stop order for winning the 7 replay or the blue 7 replay and the stop order for avoiding the falling replay win cannot be specified.

  Stop order command, stop order to win the middle bell at the time of winning the push order bell, stop order to win the promotion replay at the time of replay GR1-6 winning, special replay at the time of winning the replay GR11-13, winning the fall replay Stop order to avoid winning, Replay GR21-26 Red 7 or Blue 7 replay at the time of winning, win stop order to avoid fall replay win or middle order replay, stop order to avoid fall replay win Is transmitted after the internal winning command is transmitted when the game is started and the navigation notification described later is performed.

  The freeze command is a command that can specify whether the game is controlled to a freeze state that delays the progress of the game for a predetermined period of time, or if it is controlled to the freeze state, and when the game starts And transmitted after the internal winning command is transmitted.

  The ART lottery result command is a command that can specify whether or not an ART lottery to be described later has been won, and is transmitted when an internal lottery command is transmitted in the game in which the ART lottery has been started. .

  The reel acceleration information 1 command is a command that can specify that the rotation of the reel starts with the progress of the game, and is transmitted when the rotation of the reel starts with the progress of the game. Since this is also transmitted when the rotation of the reel is started with the end of the freeze state, after the start of the freeze state is specified by the freeze command, the game progresses by receiving the reel acceleration information 1 command. Accordingly, it is possible to specify not only the fact that the rotation of the reel starts but also the end of the frozen state.

  The reel acceleration information 2 command is a command that can specify the start of the reel effect performed in the freeze state, and is transmitted when the change of the reel accompanying the reel effect is started in the freeze state. Since the reel acceleration information 2 command is transmitted when the change of the reel accompanying the reel effect starts in the freeze state, the fact that the reel effect has started in the freeze state is identified by receiving the reel acceleration information 2 command. Is possible.

  The stop operation command is a command that can specify whether the reel to be stopped is the left reel, the middle reel, or the right reel, and the area number of the stop operation position of the corresponding reel. Sent every time the accompanying stop control is performed.

  The sliding frame number command is a command that can specify whether the reel to be stopped is a left reel, a middle reel, or a right reel, and the number of sliding frames to be moved from when the corresponding reel is stopped until it stops. Each time stop control associated with the stop operation of each reel is performed, the corresponding stop operation command is transmitted after being transmitted.

  The stop command is a command that can specify whether the reel to be stopped is a left reel, a middle reel, or a right reel, and the area number of the stop position of the corresponding reel. Stop control associated with the stop operation of each reel Is transmitted after the corresponding sliding frame number command is transmitted.

  With the stop operation command, the sliding frame number command, and the stop command, it is possible to specify whether the reel to be stopped is the left reel, the middle reel, or the right reel, and accompanying the stop operation of each reel Since it is transmitted every time stop control is performed, by receiving these commands, it is possible to specify that one of the reels has been stopped and the reel to be stopped.

  The game end command is a command that can specify that the game has ended, and is transmitted when the player presses the stop switch to stop the third stop reel and releases the stop switch.

  The winning number command is a command that can specify a combination of symbols arranged on the winning line LN, whether or not a winning is received, a type of winning, and a payout number of medals at the time of winning. The player stops the third stop reel. This is when the stop switch is pressed and released, and is transmitted after the game end command is transmitted.

  Both the game end command and the winning number command are transmitted when the player depresses the stop switch to release the third stop reel and releases the stop switch. It is possible to specify that all operations necessary to advance one game have been completed.

  The payout start command is a command for notifying the start of payout of medals, and is transmitted when the payout of medals is started by paying out a prize or credit (including medals used for setting the number of bets). The payout end command is a command for notifying the end of payout of medals, and is transmitted when the payout of medals by winning and winning a credit is completed.

  The stand-by command is a command indicating a transition to the stand-by state. When one game is over and no bet amount is set and the estimated end time (60 seconds in this embodiment) has passed, It is transmitted after the payout of medals by the settlement (including medals used for setting the number of bets) is completed and a payout end command is transmitted.

  The stop command is a command indicating the occurrence or release of the stop state, and after the end of the BB, the stop command indicating the occurrence of the stop state is transmitted when the ending effect waiting time has elapsed, and the reset operation is performed. When the stop state is released, a stop command indicating the release of the stop state is transmitted.

  An error command is a command that indicates the occurrence or cancellation of an error condition and the type of error condition. When an error is determined and controlled to an error condition, an error command indicating the occurrence and type of the error condition is sent and reset. When the error state is canceled after the operation is performed, an error command indicating the cancellation of the error state is transmitted.

  The return command is a command indicating that the main control unit 41 has returned to the control state before the power interruption, and is transmitted when the main control unit 41 returns to the control state before the power interruption.

  The setting command is a command indicating the start or end of the setting change state and the setting value after the setting change. At the time of transition to the setting change state, a setting command indicating the start of the setting change state is transmitted, and when the setting change state ends. A setting command indicating the end of the setting change state and the setting value after the setting change is transmitted. Further, since the control state of the main control unit 41 is initialized with the transition to the setting change state, it can be specified that the control state of the main control unit 41 has been initialized by the setting command indicating the start of setting. .

  The setting confirmation command is a command that indicates the start or end of the setting confirmation state. A setting confirmation command that indicates the start of setting confirmation is transmitted when the setting confirmation state is entered. A confirmation command is sent.

  The door command is a command indicating the detection state of the door opening detection switch 25, that is, on (open state) / off (closed state), when the power is turned on, at the end of one game (after the game is over, the bet number of the next game) Sent before the setting of ”can be started), and when the detection state of the door opening detection switch 25 changes (from on to off, from off to on).

  The operation detection command is a command indicating the detection state (on / off) of the operation switches (MAXBET switch 6, start switch 7, stop switches 8L, 8C, 8R), and is transmitted at regular intervals.

  Of these commands, commands other than the door command and the operation detection command are generated in the basic process, temporarily stored in the command queue provided in the RAM 41c, and transmitted in the subsequent command transmission process of the timer interrupt process (main). The

  On the other hand, the door command is generated in the door monitoring process of the timer interrupt process (main), temporarily stored in the command queue provided in the RAM 41c, and transmitted in the subsequent command transmission process of the timer interrupt process (main). Is done.

  The operation detection command is generated based on the detection state of the switch every time the command transmission process of the timer interrupt process (main) is executed 10 times, and is temporarily stored in the command queue provided in the RAM 41c. Then, it is transmitted in the command transmission process of the subsequent timer interrupt process (main).

  Next, the control of the effect performed by the sub-control unit 91 based on the command transmitted from the main control unit 41 to the effect control board 90 will be described.

  When the sub control unit 91 receives a command from the main control unit 41, the sub control unit 91 executes a command reception interrupt process. In the command reception interrupt process, the command acquired from the command transmission line is stored in the reception buffer provided in the RAM 91c.

  The reception buffer is provided with an area capable of storing a maximum of 16 commands so that a plurality of commands can be accumulated.

  In the timer interrupt process (sub), the sub-control unit 91 determines whether or not an unprocessed command is stored in the reception buffer. If an unprocessed command is stored, the sub-control unit 91 is the earliest. The control pattern table stored in the ROM 91b is referred to based on the command received in the stage, and the liquid crystal display 51, effect effect LED 52, speakers 53, 54, reel LED 55, etc. are controlled based on the control contents registered in the control pattern table. Performs output control of various rendering devices.

  In the control pattern table, the display pattern of the liquid crystal display 51 corresponding to the type of command, the lighting mode of the lighting effect LED 52, the output mode of the speakers 53 and 54, the lighting mode of the reel LED 55, etc. Control patterns of these effect devices are registered, and when the sub-control unit 91 receives a command, the sub-control unit 91 stores the control patterns registered corresponding to the effect patterns set in the RAM 91c in the game of the control pattern table. Among these, the control pattern corresponding to the type of the received command is referred to, and the output control of the rendering device is performed based on the control pattern. Thereby, the production according to the production pattern and the progress of the game is executed.

  If the sub-control unit 91 receives a new command during execution of an effect triggered by the reception of a certain command, the sub-control unit 91 stops the effect based on the control pattern being executed, and changes to the newly received command. An effect based on the corresponding control pattern is executed. In other words, even if the production is not finished to the end, when a new command is received, the production that was being executed is canceled and a new command is canceled unless the received new command is not a command that triggers a new production. An effect based on the command is executed.

  When the internal winning command is received, the effect pattern is selected at a selection rate corresponding to the result of the internal lottery indicated by the internal winning command, and is set in the RAM 91c. The selection rate of the effect pattern is registered in the effect table stored in the ROM 91b, and when the sub control unit 91 receives the internal winning command, the sub control unit 91 stores the effect pattern in the effect table according to the result of the internal lottery indicated by the internal winning command. With reference to the registered selection rate, one of the effect patterns is selected from a plurality of types of effect patterns according to the selection rate, and the selected effect pattern is set in the RAM 91c as the effect pattern of the game. Even if the same command is received, a different control pattern is selected depending on the effect pattern selected when the internal winning command is received. As a result, different effects may be performed depending on the effect pattern.

[About winning prizes]
FIG. 6 to FIG. 8 are diagrams for explaining the types of roles, symbol combinations, and technical matters related to the roles in the slot machine 1 of the present embodiment. FIG. 9 is a diagram for explaining the symbol combination of the transfer event and the technical matters related to the transfer event in the slot machine 1 of the present embodiment. FIG. 10 is a diagram for explaining the transition of the gaming state controlled by the main control unit 41, and FIG. 11 is a diagram showing an outline of the gaming state.

  As shown in FIG. 10, the slot machine 1 in the present embodiment is controlled to one of RT0 to RT4 and RB (including RB in BB).

  First, referring to FIG. 6, the special combination of the winning combinations includes two types of bonuses: a big bonus (hereinafter referred to as “BB”) and a regular bonus (hereinafter referred to as “RB”). It is.

  BB is won when the combination of “red 7-red 7-red 7” is aligned on the winning line LN at RT0-4. When winning the BB, the game shifts to a big bonus that is controlled every game by a regular bonus (to be referred to as RB hereinafter). The big bonus ends on condition that 316 or more medals have been paid out.

  RB is awarded when the combination of “BAR-BAR-BAR” is aligned on the winning line LN at RT0-4. When winning an RB, the game proceeds to a regular bonus (hereinafter referred to as RB). The regular bonus ends on the condition that any combination wins 6 times or 12 games have been consumed.

  As shown in FIG. 10, RT4 is controlled from winning BB or RB until winning, and after the big bonus or regular bonus (collectively called bonus) is finished, it is controlled by RT3. The Rukoto.

  In any of the reels, there are places where the symbols constituting the BB (“red 7” of each reel) and the symbols constituting the RB (“BAR” of each reel) are not arranged within 5 frames. Even if one of BB and RB is won in the lottery, the winning BB and RB will not be won if the stop operation is not performed at an appropriate timing.

  Next, with reference to FIG. 7, the small combination among the winning combinations will be described. Among the winning roles, the upper bell 1, upper bell 2, upper bell 3, upper bell 4, upper bell 5, upper bell 6, upper bell 7, upper bell 8, middle bell, lower right bell, middle watermelon , Right-down watermelon, middle cherries, square cherries are included.

  In the following description, when it is not necessary to distinguish the upper bell 1, the upper bell 2, the upper bell 3, the upper bell 4, the upper bell 5, the upper bell 6, the upper bell 7, and the upper bell 8, they are simply referred to as upper bells. .

  The upper bell 1 has “Replay a-Cherry a-Cherry a”, “Replay a-Cherry a-White 7”, “Replay a-Cherry a-BAR”, “Replay a” in the winning line LN in any gaming state. -Cherry b-Cherry a "," Replay a-Cherry b-White 7 "," Replay a-Cherry b-BAR "combination was awarded, and the top bell 1 won in any gaming state Sometimes 8 medals are paid out. The “replay a” of the left reel constituting the upper bell 1 is arranged at a position below the “bell”, and “cherry a” and “cherry b” of the middle reel are one of the “bells”. Since “Cherry a”, “White 7”, and “BAR” on the right reel are arranged one below “Bell”, “Replay a-Cherry a-” is placed on the winning line LN. "Cherry a", "Replay a-Cherry a-White 7", "Replay a-Cherry a-BAR", "Replay a-Cherry b-Cherry a", "Replay a-Cherry b-White 7", "Replay a When the combination of “Cherry b-BAR” is aligned, the combination of “Bell-Bell-Bell” is aligned on the upper stage of each reel 2L, 2C, 2R, that is, the invalid line LM1. In addition, the left reel “Replay a”, the middle reel “Cherry a”, and “Cherry b” which constitute the upper bell 1, the right reel “Cherry a”, “White 7”, “BAR” Since there is a place where any one of the symbols of “1” is not arranged within 5 frames, even if the upper bell 1 is won in the internal lottery described later, the stop operation of the left reel, the middle reel, and the right reel is appropriate. If it is not done at the right timing, the winning upper bell 1 will not win.

  The upper bell 2 is awarded when the combination of “Replay a-Cherry a-Plum” and “Replay a-Cherry b-Plum” is aligned on the winning line LN in any gaming state, and in any gaming state. When the upper bell 2 wins, 8 medals are paid out. The “replay a” of the left reel constituting the upper bell 2 is arranged at a position below the “bell”, and “cherry a” and “cherry b” of the middle reel are one of the “bells”. Since “Plum” on the right reel is located one below “Bell”, “Replay a-Cherry a-Plum” and “Replay a-Cherry b-” are placed on the winning line LN. When the “plum” combination is aligned, the “bell-bell-bell” combination is aligned to the upper stage of each reel 2L, 2C, 2R, that is, the invalid line LM1. In addition, the left reel “Replay a”, the middle reel “Cherry a” and “Cherry b” symbols and the “Plum” on the right reel are arranged within 5 frames. Because there is no place, even if you win the upper bell 2 in the internal lottery to be described later, if you do not stop the left reel, middle reel, and right reel at the right time, you will win the winning upper bell 2 Never do.

  The upper bell 3 is displayed when the combination of “Replay a-Plum-Cherry a”, “Replay a-Plum-White 7”, and “Replay a-Plum-BAR” is aligned on the winning line LN in any gaming state. Winning is won and 8 medals are paid out when the upper bell 3 wins in any gaming state. The “replay a” on the left reel that constitutes the upper bell 3 is located one position below the “bell”, and the “plum” on the middle reel is located one position below the “bell”. , “Cherry a”, “White 7”, and “BAR” on the right reel are arranged below “Bell”, so that “Replay a-Plum-Cherry a”, “Replay a” are placed on the winning line LN. When the combination of “Plum-White 7” and “Replay a-Plum-BAR” is aligned, the combination of “Bell-Bell-Bell” is aligned on the upper stage of each reel 2L, 2C, 2R, that is, the invalid line LM1. Become. Also, the left reel “Replay a”, the middle reel “Plum”, the right reel “Cherry a”, “White 7”, and “BAR” that make up the upper bell 3 have 5 frames or less. Since there is a portion that is not arranged in the above, even if the upper bell 3 is won in the internal lottery to be described later, if the stop operation of the left reel, the middle reel, and the right reel is not performed at an appropriate timing, I won't win the bell three.

  The upper bell 4 wins when the combination of “replay a-plum-plum” is aligned on the pay line LN in any gaming state, and eight medals when the upper bell 4 wins in any gaming state. Will be paid out. The “replay a” on the left reel that constitutes the upper bell 4 is located one position below the “bell”, and the “plum” on the middle reel is located one position below the “bell”. , “Plum” on the right reel is arranged one level below “Bell”. Therefore, when the combination of “Replay a-Plum-Plum” is aligned on the winning line LN, The combination is aligned to the upper stage of each reel 2L, 2C, 2R, that is, the invalid line LM1. In addition, the “replay a” for the left reel, “plum” for the middle reel, and “plum” for the right reel constituting the upper bell 4 are not arranged within 5 frames. Even if winning the bell 4, if the left reel, middle reel, and right reel are not stopped at an appropriate timing, the winning upper bell 4 is not won.

  The upper bell 5 has “Replay b-Cherry a-Cherry a”, “Replay b-Cherry a-White 7”, “Replay b-Cherry a-BAR”, “Replay b” in the winning line LN in any gaming state. -Cherry b-Cherry a "," Replay b-Cherry b-White 7 "," Replay b-Cherry b-BAR "combination was awarded, and the upper bell 5 won in any gaming state Sometimes 8 medals are paid out. “Replay b” of the left reel constituting the upper bell 5 is arranged at a position below the “bell”, and “cherry a” and “cherry b” of the middle reel are one of “bell”. Since “Cherry a”, “White 7”, and “BAR” on the right reel are arranged one below “Bell”, “Replay b-Cherry a-” is placed on the winning line LN. "Cherry a", "Replay b-Cherry a-White 7", "Replay b-Cherry a-BAR", "Replay b-Cherry b-Cherry a", "Replay b-Cherry b-White 7", "Replay b When the combination of “Cherry b-BAR” is aligned, the combination of “Bell-Bell-Bell” is aligned on the upper stage of each reel 2L, 2C, 2R, that is, the invalid line LM1. In addition, the left reel “Replay b”, the middle reel “Cherry a”, and “Cherry b” which are included in the upper bell 5, the right reel “Cherry a”, “White 7”, “BAR” Since there is a place where any one of the symbols of “1” is not arranged within 5 frames, even if the upper bell 5 is won in the internal lottery described later, the stop operation of the left reel, the middle reel, and the right reel is appropriate. If it is not done at the right timing, the winning upper bell 5 will not win.

  The upper bell 6 is awarded when the combination of “Replay b-Cherry a-Plum” and “Replay b-Cherry b-Plum” is aligned on the winning line LN in any gaming state, and in any gaming state. When the upper bell 6 wins, 8 medals are paid out. The “replay b” of the left reel constituting the upper bell 6 is arranged at a position below the “bell”, and “cherry a” and “cherry b” of the middle reel are one of the “bells”. Since “Plum” on the right reel is located one below “Bell”, “Replay b-Cherry a-Plum” and “Replay b-Cherry b-” are placed on the winning line LN. When the “plum” combination is aligned, the “bell-bell-bell” combination is aligned to the upper stage of each reel 2L, 2C, 2R, that is, the invalid line LM1. The left reel “Replay b”, the middle reel “Cherry a”, “Cherry b”, and the right reel “Plum” that constitute the upper bell 6 are arranged within 5 frames. Because there is no place, even if you win the upper bell 6 in the internal lottery to be described later, if you do not stop the left reel, middle reel, and right reel at the right time, you will win the winning upper bell 6 Never do.

  The upper bell 7 is used when the combination of “Replay b-Plum-Cherry a”, “Replay b-Plum-White 7”, and “Replay b-Plum-BAR” is aligned on the winning line LN in any gaming state. Winning is won and 8 medals are paid out when the upper bell 7 wins in any gaming state. The “replay b” on the left reel that constitutes the upper bell 7 is located one position below the “bell”, and the “plum” on the middle reel is located one position below the “bell”. , “Cherry a”, “White 7”, and “BAR” on the right reel are arranged below “Bell”, so that “Replay b-Plum-Cherry a”, “Replay b” are placed on the winning line LN. When the combination of “Plum-White 7” and “Replay b-Plum-BAR” is aligned, the combination of “Bell-Bell-Bell” is aligned on the upper stage of each reel 2L, 2C, 2R, that is, the invalid line LM1. Become. Also, the left reel “Replay b”, the middle reel “Plum”, the right reel “Cherry a”, “White 7”, and “BAR” that make up the upper bell 7 are within 5 frames. Since there is a portion that is not arranged in the above, even if the upper bell 7 is won in the internal lottery to be described later, if the stop operation of the left reel, the middle reel, and the right reel is not performed at an appropriate timing, I wo n’t win Bell 7.

  The upper bell 8 is awarded when the combination of “replay a-plum-plum” is aligned on the winning line LN in any gaming state, and eight medals are awarded when the upper bell 8 is awarded in any gaming state. Will be paid out. The “replay b” on the left reel that constitutes the upper bell 8 is located one position below the “bell”, and the “plum” on the middle reel is located one position below the “bell”. , “Plum” on the right reel is placed one level below “Bell”, so when the combination of “Replay b-Plum-Plum” is aligned on the winning line LN, The combination is aligned to the upper stage of each reel 2L, 2C, 2R, that is, the invalid line LM1. In addition, the “replay b” of the left reel, the “plum” of the middle reel, and the “plum” of the right reel constituting the upper bell 8 are not arranged within 5 frames. Even if winning the bell 8, if the stop operation of the left reel, the middle reel and the right reel is not performed at an appropriate timing, the winning upper bell 8 will not be won.

  The middle bell is awarded when the combination of “bell-bell-bell” is aligned on the winning line LN in any gaming state, and eight medals are paid out when the middle bell is won in any gaming state. . Since the “bell” of the left reel, the “bell” of the middle reel, and the “bell” of the right reel that make up the middle bell are arranged within 5 frames, when winning the middle bell in the internal lottery described below, In principle, it can be said that it can be awarded regardless of the timing of the stop operation.

  The downward-sloping bell is “Replay a-bell-red 7”, “Replay a-bell-replay a”, “Replay b-bell-red 7”, “Replay b-bell” on the winning line LN in any gaming state. -When a combination of "Replay a" is completed, a prize is awarded. In any gaming state, when the right-down bell is awarded, eight medals are paid out. The “replay a” and “replay b” of the left reel constituting the right-down bell are arranged one position below the “bell”, and “red 7” and “replay a” of the right reel are “ Since it is arranged one position above the “bell”, “Replay a-bell-red 7”, “Replay a-bell-replay a”, “Replay b-bell-red 7”, “ When the combination of “replay b-bell-replay a” is aligned, the combination of “bell-bell-bell” is lowered to the right, that is, aligned with the invalid line LM3. In addition, any one of the symbols “Replay a” and “Replay b” on the left reel constituting the lower right bell, any one of “Bell” on the middle reel, “Red 7” on the right reel, and “Replay a” Since these symbols are arranged within 5 frames, it can be said that, as a general rule, when winning the downward-sloping bell in the internal lottery described later, it can be awarded regardless of the timing of the stop operation.

  The middle stage watermelon is awarded when the combination of “Watermelon-Watermelon-Watermelon” or “Watermelon-Watermelon-Blue 7” is aligned on the winning line LN in any gaming state, and the middle stage watermelon is awarded in any gaming state. When you do, 5 medals will be paid out. Because there is a place where the design of any one of "Watermelon" of the left reel, "Watermelon" of the middle reel, "Watermelon" of the right reel, and "Blue 7" that constitutes the middle stage watermelon is not arranged within 5 frames, Even if the middle stage watermelon is won in an internal lottery described later, if the left reel, middle reel, and right reel are not stopped at an appropriate timing, the winning middle stage watermelon will not be won.

  The right-down watermelon is awarded when the combination of “Bell-Watermelon-Cherry b” or “Bell-Watermelon-White 7” is aligned on the winning line LN in any game state, and the right-down watermelon is lowered in any game state. When the watermelon wins, 5 medals are paid out. The “bell” of the left reel that constitutes the right-down watermelon is disposed at a position immediately below “watermelon” or “blue 7”, and the “cherry b”, “ Since “White 7” is arranged one position above “Watermelon”, when the combination of “Bell-Watermelon-Cherry b” or “Bell-Watermelon-White 7” is aligned on the winning line LN, “Watermelon” The combination of “-watermelon-watermelon” or “blue 7-watermelon-watermelon” is lowered to the right, that is, aligned with the invalid line LM3. The “bell” on the left reel that constitutes the right-down watermelon is arranged within 5 frames, but the “watermelon” on the middle reel that constitutes the right-down watermelon, “cherry b”, and “white 7” on the right reel. Since any one of the symbols is not placed within 5 frames, even if the right-down watermelon is won in the internal lottery to be described later, the stop operation of the middle reel and the right reel is performed at an appropriate timing. Otherwise, you won't win the winning right down watermelon.

  The middle cherries are awarded when the combination of “cherry a-bell-replay a” is aligned on the winning line LN in any gaming state, and one medal is awarded when the middle cherries wins in any gaming state. To be paid out. The middle reel “bell” and right reel “Replay a” are arranged within 5 frames, while the left reel “cherry a” constituting the middle cherry is arranged within 5 frames. Since there is no place, even if the middle cherries are won in the internal lottery described later, if the left reel is not stopped at an appropriate timing, the winning middle cherries will not be won.

  A corner cherry is awarded when the combination of “Red 7-Bell-Replay a” and “BAR-Bell-Replay a” is aligned on the winning line LN in any gaming state. When a prize is won, one medal is paid out. “Red 7” and “BAR” of the left reel constituting the corner cherry are arranged one above “Cherry”, so “Red 7-Bell-Replay a” and “BAR-Bell” are placed on the winning line LN. When the combination of “Replay a” is aligned, the combination of “Cherry a-any-any (any symbol is acceptable)” is aligned downward and to the right, that is, the invalid lines LM2 and LM4. The “bell” of the middle reel that forms the square cherry and the “replay a” of the right reel are arranged within 5 frames, but either the “red 7” or “BAR” of the left reel that constitutes the square cherry. Because there is a place where the symbol of 1 is not arranged within 5 frames, even if the corner cherry is won in the internal lottery described later, if the left reel stop operation is not performed at an appropriate timing, it will be selected I won't win the horned cherries.

  Next, with reference to FIG. 8, the re-game player among the winning combinations will be described. Among the winning combinations, the replaying role includes middle replay, right-up replay, promotion replay, special replay, fall replay, red 7 replay, and blue 7 replay.

  The middle stage replay is awarded when a combination of “Replay a-Replay a-Replay a” and “Replay b-Replay a-Replay a” is arranged on the winning line LN at RT0 to RT4, and a replay game (replay) is played. Is granted. Since the left reel's “Replay a” and “Replay b” symbols, the middle reel “Replay a”, and the right reel “Replay a” are arranged within 5 frames, In the internal lottery to be described later, when the middle stage replay is won, it can be said that, as a general rule, it can be awarded regardless of the timing of the stop operation.

  The replay that goes up to the right is awarded when a combination of “Bell-Replay a-Red 7” or “Bell-Replay a-Bell” is aligned on the winning line LN in RT1 to RT4, and a replay game (replay) is given. The The “bell” of the left reel constituting the right-up replay is arranged at a position one above “replay a” and “replay b”, and “red 7” and “bell” of the right reel are “replay”. Since it is arranged at a position one lower than “a”, when the combination of “Bell-Replay a-Red 7” or “Bell-Replay a-Bell” is aligned with the winning line LN, it goes to the right, that is, the invalid line LM4. "Replay a-Replay a-Replay a" and "Replay b-Replay a-Replay a" are combined. Also, the left reel “bell”, middle reel “replay a”, right reel “red 7”, and “bell” composing the right-up replay are arranged within 5 frames. In the internal lottery to be described later, when winning rightward replay is won, it can be said that, as a general rule, it is a role that can be awarded regardless of the timing of the stop operation.

  The promotion replay is awarded when a combination of “bell-replay a-replay a” is arranged on the winning line LN at RT1, and a replay game (replay) is given. Also, the game state shifts to RT0 due to the promotion replay winning. In addition, “bell” on the left reel, “replay a” on the middle reel, and “replay a” on the right reel that make up the promotion replay are arranged within 5 frames. In principle, it can be said that the role can be awarded regardless of the timing of the stop operation.

  The special replay is awarded when a combination of “replay a-replay a-bell” and “replay b-replay a-bell” is arranged on the winning line LN at RT0, and a replay game (replay) is given. Further, the game state shifts to RT2 due to the special replay winning. In addition, the symbol of any one of “Replay a” and “Replay b” on the left reel, “Replay a” on the middle reel, and “Bell” on the right reel constituting the special replay are arranged within 5 frames. When a special replay is won in an internal lottery to be described later, in principle, it can be said that it is a role that can be awarded regardless of the timing of the stop operation.

  The falling replays are “Bell-Red 7-Cherry a”, “Bell-Red 7-Watermelon”, “Bell-Red 7-Plum”, “Bell-Watermelon-Cherry a”, “ "Bel-Watermelon-Watermelon", "Bell-Watermelon-Plum", "Bell-Cherry a-Cherry a", "Bell-Cherry a-Watermelon", "Bell-Cherry a-Plum" Thus, a replay game (replay) is given. In addition, the gaming state shifts to RT1 due to the fall replay winning. The “bell” on the left reel that constitutes the fall replay is placed one position above “replay a” and “replay b”, and “red 7”, “watermelon”, and “cherry a” on the middle reel. Is positioned one position above “Replay a”, and “Cherry a”, “Watermelon”, and “Plum” on the right reel are positioned one position above “Replay a” or “Blue 7”. Are placed on the winning line LN, “Bell-Red 7-Cherry a”, “Bell-Red 7-Watermelon”, “Bell-Red 7-Plum”, “Bell-Watermelon-Cherry a”, “Bell -"Watermelon-Watermelon", "Bell-Watermelon-Plum", "Bell-Cherry a-Cherry a", "Bell-Cherry a-Watermelon", "Bell-Cherry a-Plum" “Replay a-Replay a-Replay” is displayed on the invalid line LM2. a "," Replay a- replay a- blue 7 "," Replay b- replay a- replay a ", so that the combination of" Replay b- replay a- Blue 7 "are aligned. In addition, the left reel “bell”, middle reel “red 7”, “watermelon”, “cherry a” design, right reel “watermelon”, “plum”, “cherry” Since any one symbol of “a” is arranged within 5 frames, as a general rule, when winning a fall replay in the internal lottery described later, it is possible to win a prize regardless of the timing of the stop operation. I can say that.

  The red 7 replay is “replay a-blue 7-replay a”, “replay a-watermelon-replay a”, “replay a-cherry a-replay a”, “replay b-blue 7-” on the winning line LN at RT2. When a combination of “Replay a”, “Replay b-Watermelon-Replay a”, and “Replay b-Cherry a-Replay a” is completed, a prize is awarded and a replay game (replay) is given. In particular, the “replay b” of the left reel that constitutes the red 7 replay is arranged one position above “red 7”, and the “blue 7” of the middle reel is one above “red 7”. Since “Replay a” on the right reel is positioned one position above “Red 7”, “Replay b-Blue 7-Replay a” is displayed on the winning line LN. When the combinations are aligned, the combination of “red 7-red 7-red 7” may be aligned in the lower stage, that is, the invalid line LM2. The left reel's “Replay a” and “Replay b” designs, the middle reel “Blue 7”, “Watermelon” and “Cherry a” designs, the right reel Since “Replay a” is arranged within 5 frames, it can be said that, in principle, when a red 7 replay is won in an internal lottery to be described later, it can be said that it can be awarded regardless of the timing of the stop operation.

  Blue 7 Replay is “Cherry a-Blue 7-Replay a”, “Cherry a-Watermelon-Replay a”, “Cherry a-Cherry a-Replay a”, “Bell-Blue 7-Replay” on the winning line LN at RT2. When a combination of “a”, “Bell-Watermelon-Replay a” or “Bell-Cherry a-Replay a” is completed, a prize is awarded and a replay game (replay) is given. In particular, “cherry a” on the left reel that constitutes the blue 7 replay is arranged one position above “blue 7”, and “replay a” on the right reel is one below “blue 7”. When the combination of “Cherry a-Blue 7-Replay a” is aligned on the winning line LN, the combination of “Blue 7-Blue 7-Blue 7” is increased to the right, that is, the invalid line LM4. Can be aligned. The left reel's “cherry a” and “bell” symbols that make up the Blue 7 replay, the middle reel “blue 7”, “watermelon”, and “cherry a” any one symbol, the right reel Since “Replay a” is arranged within 5 frames, it can be said that, in principle, when a blue 7 replay is won in an internal lottery to be described later, it can be said that it can be awarded regardless of the timing of the stop operation.

  Next, with reference to FIG. 9, the transition outcome will be described. Transitions are "Replay a-Cherry a-Bell", "Replay a-Cherry b-Bell", "Replay a-Plum-Bell", "Replay b-Cherry a-Bell", "Replay b-Cherry b" -"Bell", "replay b-plum-bell", "replay a-bell-cherry a", "replay a-bell-white 7", "replay a-bell-BAR", "replay b-bell-cherry a" ”,“ Replay b-Bell-White 7 ”,“ Replay b-Bell-BAR ”,“ Bell-Cherry a-Cherry a ”,“ Bell-Cherry a-White 7 ”,“ Bell-Cherry a-BAR ”, “Bell-Cherry b-Cherry a”, “Bell-Cherry b-White 7”, “Bell-Cherry b-BAR”, “Bell-Plum-Cherry a”, “Bell-Plum-White 7”, “Bell- Plum-BAR ” , RT0, RT2, migration outcomes in RT3 is shifted to align and RT1 to the winning line LN. In this embodiment, the left bells 1 to 4, the middle bells 1 to 4 and the right bells 1 to 4 are elected, the reels other than the reels which are the winning conditions for the middle bell are set as the first stop, and the elected upper bell is missed. In this case, the transfer outcome is aligned with the winning line LN.

[About lots eligible for lottery]
Next, with reference to FIGS. 12-16, the combination of the lottery object combination read as a lottery object role for each gaming state will be described. In the present embodiment, a role that is subject to an internal lottery or whether the gaming state is RT1, RT2, RT3, RT4, or RB (including RB in BB) or its At least one of the winning probabilities is different. As will be described later as a lottery target combination, a plurality of winning combinations can be read out simultaneously and can be won in duplicate. In FIGS. 12 to 16, “+” is written between winning combinations to indicate that they are simultaneously read out as a lottery target combination in the internal lottery.

In FIGS. 12 to 14, the lottery object combination is shown in the vertical column, and the gaming state is shown in the horizontal column. In the column where the gaming state intersects with the lottery target, a circle indicates that it is a lottery target when in the gaming state, and a cross indicates that it is not a lottery target when in the gaming state. It shows that.

  Also, the numerical values shown below the circles indicate the number of determination values of a predetermined set value (common in this embodiment regardless of the set value). An internal lottery is performed using the number of determination values. The denominator of the number of determination values is set to “65536” corresponding to a random number for internal lottery (an integer from 0 to 65535). For this reason, for example, the winning probability of the lottery subject for which “300” is set as the number of determination values is 300/65536.

  FIG. 12 shows combinations of special combinations that are read out as lottery targets for each gaming state, FIGS. 13 and 14 show combinations of small roles that are read out as lottery targets for each gaming state, and FIG. , A combination of re-playing combinations that are read out as lottery targets.

  When the gaming state is RT0, BB, BB + strong cherry, BB + weak cherry, BB + watermelon, RB, RB + weak cherry, RB + watermelon, left bell 1, left bell 2, left bell 3, left bell 4, middle bell 1, Middle bell 2, middle bell 3, middle bell 4, right bell 1, right bell 2, right bell 3, right bell 4, strong cherry, weak cherry, watermelon, common bell, replay GR11, replay GR12, replay GR13 It becomes the target role of.

  When the gaming state is RT1, BB, BB + strong cherry, BB + weak cherry, BB + watermelon, RB, RB + weak cherry, RB + watermelon, left bell 1, left bell 2, left bell 3, left bell 4, middle bell 1, Middle bell 2, middle bell 3, middle bell 4, right bell 1, right bell 2, right bell 3, right bell 4, strong cherry, weak cherry, watermelon, common bell, normal replay, replay GR1, replay GR2, replay GR3 The replay GR4, the replay GR5, and the replay GR6 are subject to internal lottery.

  When the gaming state is RT2, BB, BB + strong cherry, BB + weak cherry, BB + watermelon, RB, RB + weak cherry, RB + watermelon, left bell 1, left bell 2, left bell 3, left bell 4, middle bell 1, Middle bell 2, middle bell 3, middle bell 4, right bell 1, right bell 2, right bell 3, right bell 4, strong cherry, weak cherry, watermelon, common bell, normal replay, replay GR21, replay GR22, replay GR23 The replay GR24, the replay GR25, and the replay GR26 are subject to internal lottery.

  When the gaming state is RT3, BB, BB + strong cherry, BB + weak cherry, BB + watermelon, RB, RB + weak cherry, RB + watermelon, left bell 1, left bell 2, left bell 3, left bell 4, middle bell 1, Middle bell 2, middle bell 3, middle bell 4, right bell 1, right bell 2, right bell 3, right bell 4, strong cherries, weak cherries, watermelons, common bells, and normal replays are subject to internal lottery.

  When the gaming state is RT4, left bell 1, left bell 2, left bell 3, left bell 4, middle bell 1, middle bell 2, middle bell 3, middle bell 4, right bell 1, right bell 2, right bell 3, right bell 4, strong cherry, weak cherry, watermelon, common bell, and normal replay are the subject of internal lottery.

  When the gaming state is RB, strong cherries, weak cherries, watermelons, and common bells are targeted for internal lottery.

  As shown in FIG. 15, the left bell 1 is a combination of the middle bell + the upper bell 1 + the upper bell 8, and the left bell 2 is a combination of the middle bell + the upper bell 2 + the upper bell 7, and the left bell 3 Is a combination of middle bell + upper bell 3 + upper bell 6, and left bell 4 is a combination of middle bell + upper bell 4 + upper bell 5.

  The middle bell 1 is a combination of the middle bell + the upper bell 1 + the upper bell 6, the middle bell 2 is the combination of the middle bell + the upper bell 2 + the upper bell 5, and the middle bell 3 is the middle bell. + The upper bell 3 + the upper bell 8 and the middle bell 4 is a combination of the middle bell + the upper bell 4 + the upper bell 7.

  Further, the right bell 1 is a combination of the middle bell + the upper bell 1 + the upper bell 7, the right bell 2 is a combination of the middle bell + the upper bell 2 + the upper bell 8, and the right bell 3 is the middle bell. + The upper bell 3 + the upper bell 5 and the right bell 4 is a combination of the middle bell + the upper bell 4 + the upper bell 6.

  In the following, when it is not particularly necessary to distinguish, left bells 1 to 4 are simply referred to as left bells, middle bells 1 to 4 are simply referred to as middle bells, and right bells 1 to 4 are simply referred to as right bells. There is. Moreover, when it is not necessary to distinguish any of the left bells 1 to 4, the middle bells 1 to 4, and the right bells 1 to 4, they may be simply referred to as push order bells.

The common bell is a combination of a middle bell and a right-down bell. Strong cherries are a combination of square cherries + middle cherries, and weak cherries are single winning horn cherries. Watermelon
It is a combination of middle-stage watermelon + right-down watermelon.

  As shown in FIG. 16, the normal replay is a combination of middle stage replay + upward right replay. Replay GR1 is a combination of middle replay + promotion replay, replay GR2 is a combination of middle replay + promotion replay + upward replay, and replay GR3 is middle replay + promotion replay + red 7 replay. Replay GR4 is a combination of middle replay + promotion replay + red 7 replay + rightward replay, and replay GR5 is a combination of middle replay + promotion replay + tumbling replay, and replay GR6 , Middle stage replay + promotion replay + fall fall replay + upward right replay. The replay GR11 is a combination of middle replay + falling replay, the replay GR12 is a combination of middle replay + falling replay + rightward replay, and the replay GR13 is middle replay + falling replay + middle replay. It is a combination. Replay GR21 is a combination of middle replay + red 7 replay + falling replay, replay GR22 is a combination of middle replay + red 7 replay + falling replay + upward replay, and replay GR23 is middle. Replay + red 7 replay + fall replay + rising right replay + promoted replay. Replay GR24 is a combination of middle replay + blue 7 replay + fall replay, and replay GR25 is a middle replay + blue 7 replay. The combination of + falling replay + upward replay, and the replay GR 26 is a combination of middle stage replay + blue 7 replay + falling replay + upward right replay + promotion replay.

  In the present embodiment, when the push order bell is won, as shown in FIG. 17, the combination of the symbols to be stopped differs according to the type of the push order bell and the stop order.

  For example, if the left bell 1 (middle bell + upper bell 1 + upper bell 8) is elected and the stop operation is performed in the stop order with the left reel as the first stop, the combination of the middle bell stops at the winning line LN. When the stop operation is performed in the stop order in which the middle reel is the first stop or in the stop order in which the right reel is the first stop, either the combination of the upper bell 1 and the upper bell 4 or the transition outcome is Stop at the winning line LN.

  The same applies to the left bells 2 to 4, the middle bells 1 to 4, and the right bells 1 to 4. As shown in FIG. 17, the combination of symbols to be stopped differs depending on the type of the push order bell and the stop order.

  In this way, if any of the left bell, middle bell, and right bell, that is, the push order bell, is won, the middle bell will always win a prize by performing the stop operation according to the type of push order bell. On the other hand, by performing stop operation in a stop order other than the stop order according to the type of push order bell, the upper bell wins at a certain rate, but the upper stage bell is not aligned and the transitional outcome may stop. is there.

  For this reason, when the push order bell is won, the expected value of the number of medals to be paid out can be changed depending on whether or not the operation is performed in the stop order according to the type of the push order bell. In other words, even if one of the push order bells is won, if the type is not known, it is not possible to intentionally select the stop order according to the type, and if the stop order matches, the middle bell is definitely won By doing so, medals can be obtained with certainty, but if the stopping order does not match, medals can be obtained only at a certain rate. In particular, in RT0 and RT2, since the transition point stops when the stop order does not match, if the stop order does not match, the transition to RT1 occurs at a certain rate.

  In this embodiment, even if the stop operation is performed in any stop order, the middle bell wins at an equal rate and eight medals can be obtained, so the player performs the stop operation in any stop order. Can be prevented from becoming extremely disadvantageous.

  In this embodiment, in any game state, when the common bell is won, the middle bell or the right-down bell wins. On the other hand, when the push order bell is won, the right-down bell will not win. For this reason, the player can recognize that the common bell has been won by winning the right-down bell.

  Also, in this embodiment, when a weak cherry is won in any gaming state, if the left reel “Cherry a” is stopped at a timing at which it can be stopped at either the middle stage or the lower stage, the left reel “Cherry a” stops at the lower stage, but when a strong cherry is won, the “Cherry a” on the left reel is stopped at a timing that can be stopped at both the middle and lower stages. “Cherry a” on the left reel stops in the middle. For this reason, as a result of performing a stop operation at a timing at which the “cherry a” of the left reel can be stopped at both the middle and lower stages, the “cherry a” of the left reel stops at the middle, so that the player You can recognize that a strong cherry was won.

  In this embodiment, when the replays GR1 to GR6 are elected, as shown in FIG. 18, the combination of symbols to be stopped differs according to the type and stop order.

  For example, when replay GR1 (middle replay + promotion replay) is won and the stop operation is performed in the order of stop in the middle left and right, the combination of promotion replay stops in the winning line LN and the stop order other than the left center right When the stop operation is performed at, the middle stage replay combination stops at the winning line LN.

  The same applies to the replays GR2 to GR6, and as shown in FIG. 18, the combination of symbols to be stopped is different according to the type and stop order.

  As described above, when one of the replays GR1 to GR6 to be selected in the RT1 wins, by performing the stop operation in the stop order corresponding to the type, the promoted replay wins and moves to RT0. By performing a stop operation in a stop order other than the stop order corresponding to the type, the middle stage replay wins and RT1 is maintained.

  For this reason, when replay GR1-6 is won in RT1, the promotion replay wins by operating in the stop order corresponding to the type, but if the type is not known, intentionally select the stop order according to the type If the stop order matches, it is possible to shift to RT0 by winning the promoted replay. However, if the stop order does not match, RT1 is maintained.

  In this embodiment, even if the stop operation is performed in any stop order, the promotion replay wins at an equal rate and shifts to RT0. Therefore, no matter what stop order the player performs the stop operation, Can be prevented from becoming disadvantageous.

  In the present embodiment, when the replays GR11 to 13 are elected, as shown in FIG. 18, the combination of symbols to be stopped is different according to the type and stop order.

  For example, when the replay GR11 (special replay + falling replay) is won and the stop operation is performed in the stop order in which the left reel is the first stop, the combination of the special replay stops on the winning line LN, When the stop operation is performed in the stop order in which the right reel is the first stop, the fall replay combination stops on the winning line LN.

  The same applies to the replays GR12 and 13, and as shown in FIG. 18, the combination of symbols to be stopped is different according to the type and the stop order.

  As described above, when any of the replays GR11 to 13 to be selected at RT0 wins, the special replay wins and moves to RT2 by performing a stop operation in the stop order corresponding to the type. When the stop operation is performed in a stop order other than the stop order corresponding to the type, the fall replay wins and the process proceeds to RT1.

  For this reason, when replay GR11-13 is selected at RT0, special replay wins by operating in the stop order corresponding to the type, but if the type is not known, intentionally select the stop order according to the type If the stop order matches, it is possible to shift to RT2 by winning the special replay, but if the stop order does not match, the process shifts to RT1.

  In this embodiment, even if the stop operation is performed in any stop order, the special replay is won at an equal rate and the process proceeds to RT2. Therefore, no matter what stop order the player performs the stop operation, Can be prevented from becoming disadvantageous.

  In this embodiment, when the replays GR21 to 23 are elected, as shown in FIG. 18, the combination of symbols to be stopped is different according to the type and stop order.

  For example, when the replay GR21 (middle replay + red 7 replay + falling replay) is won and the stop operation is performed in the stop order with the left reel as the first stop, the combination of the middle replay stops on the winning line LN. When the stop operation is performed in the stop order in which the middle reel is the first stop, the combination of the falling replay is stopped on the winning line LN, and the stop operation is performed in the stop order in which the right reel is the first stop. The red 7 replay combination stops on the winning line LN.

  The same applies to the replays GR22 and 23, and as shown in FIG. 18, the combination of symbols to be stopped is different depending on the type and stop order.

  As described above, when any of the replays GR21 to 23 to be selected in the RT2 wins, the middle stage replay or red 7 replay wins by performing the stop operation in the order of stop according to the type, and the RT2 On the other hand, by performing a stop operation in a stop order other than the stop order corresponding to the type, the fall replay wins and the process proceeds to RT1.

  For this reason, when replay GR21-23 is selected in RT2, the middle stage replay or red 7 replay is won by operating in the order of stop according to the type, but if the type is not known, it was intentionally adapted to the type The stop order cannot be selected. If the stop order matches, RT2 can be maintained by winning the middle stage replay or red 7 replay, but if the stop order does not match, the process moves to RT1. It will be.

  In this embodiment, since the middle stage replay or red 7 replay wins and RT2 is maintained at an equal rate regardless of the stop order in which stop operation is performed, the player performs the stop operation in any stop order. Even if it goes, it can prevent becoming extremely disadvantageous.

  In the present embodiment, when the replays GR24 to 26 are elected, as shown in FIG. 18, the combination of symbols to be stopped differs according to the type and stop order.

  For example, when the replay GR24 (middle replay + blue 7 replay + falling replay) is won and the stop operation is performed in the stop order with the left reel as the first stop, the combination of the middle replay stops on the winning line LN. When the stop operation is performed in the stop order in which the middle reel is the first stop, the combination of the falling replay is stopped on the winning line LN, and the stop operation is performed in the stop order in which the right reel is the first stop. , The blue 7 replay combination stops on the winning line LN.

  The same applies to the replays GR25 and 26, and as shown in FIG. 18, the combination of symbols to be stopped is different according to the type and stop order.

  As described above, when one of the replay GRs 24 to 26 to be selected at RT2 wins, the middle stage replay or the blue 7 replay wins by performing a stop operation in the order of stop according to the type, and RT2 On the other hand, by performing a stop operation in a stop order other than the stop order corresponding to the type, the fall replay wins and the process proceeds to RT1.

  For this reason, when the replay GR24-26 is won in RT2, the middle stage replay or blue 7 replay is won by operating in the stop order corresponding to the type, but if the type is not known, it is intentionally adapted to the type The stop order cannot be selected. If the stop order matches, RT2 can be maintained by winning the middle stage replay or the blue 7 replay, but if the stop order does not match, the process proceeds to RT1. It will be.

  In this embodiment, since the middle stage replay or the blue 7 replay wins and RT2 is maintained at an equal rate regardless of the stop order in which stop operation is performed, the player performs the stop operation in any stop order. Even if it goes, it can prevent becoming extremely disadvantageous.

  In this embodiment, as shown in FIG. 10 and FIG. 11, the control is performed to any one of RT0 to RT4 and bonus (RB, RB in BB).

  RT0 shifts due to the promotion replay winning in RT1. Regardless of the number of games since the transition to RT0, RT0 transitions to RT1 by winning a fall replay or stopping the transition, or transitions to RT2 by winning a special replay, or a special role is won And it complete | finishes by transfering to RT4. The winning probability of the special role in RT0 is normal (about 1 / 346.8), the winning probability of the re-playing role is high (about 1 / 2.8), and the winning probability of the small role is normal (about 1 / 3.8) ), And the payout rate of medals per game is less than 100%. In RT0, only the replay GRs 11 to 13 among the re-game players are targeted for internal lottery.

  RT1 shifts at RT0, RT2, RT3 when a fall replay is won or when a transition is stopped. Then, RT1 ends by shifting to RT0 by winning a promotion replay or shifting to RT4 by winning a special role, regardless of the number of games since shifting to RT1. The winning probability of the special role in RT1 is normal (about 1 / 346.8), similar to RT0, the winning probability of the re-playing role is lower than RT0 (about 1 / 7.3), and the winning probability of the small role is RT0. Similarly, it is normal (about 1 / 3.8), and the payout rate of medals per game is less than 100%. In RT1, only normal replays and replays GR1 to GR6 among replaying players are targeted for internal lottery.

  RT2 shifts by winning a special replay at RT0. Then, regardless of the number of games after transitioning to RT2, RT2 is terminated by transitioning to RT1 by winning a fall replay or stopping the transitional outcome, or by transitioning to RT4 by winning a special role. The winning probability for special roles in RT2 is normal (about 1 / 346.8), similar to RT0, the winning probability for re-playing roles is higher than RT0 (about 1 / 1.5), and the winning probability for small roles is Like RT0, it is normal (about 1 / 3.8), and the payout rate of medals per game is 100% or more. In RT2, only the normal replay and replay GRs 21 to 26 among the re-game players are targeted for the internal lottery.

  RT3 shifts to the end of the bonus (BB, RB). Then, RT3 is terminated by transitioning to RT1 by stopping the transition or regardless of the number of games since transitioning to RT3, or by transitioning to RT4 by winning a special role. The winning probability of the special role in RT3 is normal (about 1 / 346.8), the winning probability of the re-playing role is lower than RT0 (normally 1 / 7.3), and the winning probability of the small role is normal (same as RT0) About 1 / 3.8), and the payout rate of medals per game is less than 100%. In RT3, only the normal replay among the re-game players is the target of the internal lottery.

  RT4 shifts by winning special roles (BB, RB) in RT0-3. RT4 ends when the special combination that triggered the transition to RT4 wins and shifts to a bonus (BB or RB) regardless of the number of games since the transition to RT4. In RT4, special roles are excluded from the internal lottery, and the winning probability of re-playing roles is lower than RT2, but higher than RT0, RT1, RT3 and high probability (about 1 / 2.3). The probability is normal (about 1 / 3.8), and the payout rate of medals per game is less than 100%. Further, in RT4, only the normal replay among the re-game players is the target of the internal lottery.

  RB shifts due to RB winning in RT4. Then, the RB ends when 12 games are digested or the game is won six times. In RB, special roles and re-playing roles are not subject to internal lottery, and the winning probability of small roles is higher than RT0-5 and has a high probability (about 1 / 1.1), and medals per game The payout rate is 100% or more.

  BB shifts by winning BB at RT4. The BB ends when the total number of medals paid out to the BB exceeds a specified number (316 in this embodiment) regardless of the number of games since the transition to the BB. In BB, since it is always controlled by the above-mentioned RB, the special combination and the re-playing combination are excluded from the internal lottery, and the winning probability of the small combination is higher than RT0 to 5 and a high probability (about 1/1. 1), and the payout rate of medals per game is 100% or more.

  Among RT0 to 4, RB, and BB (RB), RB and BB have the highest medal payout rate per game and are the most advantageous gaming state. RT0, RT4 of RT0-4 have a high probability of winning a re-gamer, and the payout rate of medals per game is higher than RT1, 3, especially RT0 to RT2. It can be said that it is more advantageous for the player than RT1 and 3 in that it can be transferred. RT2 out of RT0, 2 and 4 can be said to be more advantageous to the player than RT0 and 4 in that the payout rate of medals per game is higher than RT0 and 4.

  In the slot machine according to the present embodiment, when the gaming state is RT0 to 2, the main control unit 41 can execute navigation notification that notifies the player of the stop order that is advantageous to the player according to the internal lottery result. It is possible to control the assist time (hereinafter referred to as AT) that is a notification period.

  Here, the transition state of the gaming state of the present embodiment will be described. As shown in FIG. 10, when RB or BB ends, the process proceeds to RT3.

  In RT3, the process shifts to RT1 by stopping the transfer event, and shifts to RT4 by winning the special role. If the push order bell is won at RT3, the transition outcome may stop, so if the push order bell wins at RT3 that has transitioned after the end of RB or BB and the transition outcome stops, the transition to RT1 It becomes.

  In RT1, it shifts to RT0 by winning the promotion replay, and shifts to RT4 by winning the special role. Since the replays GR1 to 6 are won in RT1 and the promotion replay wins when the stop order is correct, in RT1, when the replays GR1 to 6 are selected and correct in the order of stoppage, the process proceeds to RT0. Become.

  At RT0, the game shifts to RT1 when the fall replay wins or stops the transition, shifts to RT2 when the special replay wins, and shifts to RT4 when the special role is won. Since the replay GRs 11 to 13 are won at RT0, the special replay wins when the stop order becomes correct, and the fall replay wins when the stop order becomes incorrect, so at RT0, the replays GR11 to 13 Will be transferred to RT2 if the answer is correct and the answer is correct in the order of stop, and to RT1 if the answer is not correct in the order of stop.

  Also, because the push order bell wins at RT0 and the stoppage may stop because the stop order becomes incorrect, the RT0 moves to RT1 when the push order bell wins and does not answer correctly in the stop order Will be.

  In RT2, the game shifts to RT1 by winning the fall replay or stopping the transition, and moves to RT4 by winning the special role. Replay GR21-26 wins at RT2, and the fall replay wins when the stop order becomes incorrect, so at RT2, if replay GR21-26 wins and does not answer correctly in stop order, it goes to RT1 Will be migrated.

  Also, because the push order bell wins at RT0 and the stoppage may stop because the stop order becomes incorrect, the RT0 moves to RT1 when the push order bell wins and does not answer correctly in the stop order Will be.

  RT4 shifts to RB or BB when the special combination that has triggered the transition to RT4 wins.

  When the main control unit 41 is controlled by the AT, the main control unit 41 performs navigation notification by winning the navigation target combination corresponding to the gaming state, and transmits a push order command to the sub control unit 91. In this way, the navigation effect is executed. The navigation target combination corresponding to the gaming state is replay GR1 to 6 when RT1, replay GR11 to 13 when RT0, and replay GR21 to 26 when RT2. Further, in any of RT0 to RT2, the push order bell is a common navigation target combination. Further, in the present embodiment, the main control unit 41 executes navigation notification by satisfying certain conditions even in a normal state (RT1 and non-AT state) where neither AT nor ART is controlled. It is possible to execute a navigation effect.

  The navigation notification of the present embodiment notifies the stop order that is advantageous for the player in an identifiable manner by changing the lighting mode of the game auxiliary indicator 12.

  Note that the navigation notification mode is not limited to this mode, and any mode may be used as long as the player can be distinguished according to the winning situation. In addition, the navigation notification is not limited to the game auxiliary display 12, that is, the display used for notification other than the navigation notification, and may be executed using a dedicated display.

  The navigation effect of the present embodiment notifies the stop order advantageous for the player notified by the navigation notification by displaying the navigation image from the liquid crystal display 51 and outputting the navigation sound from the speakers 53 and 54.

  For example, when informing the stop order of the left middle right stop switch 8L such as “123” (indicating that the left reel is the first stop, the middle reel is the second stop, and the right reel is the third stop), A stop order image indicating the stop order of 8C and 8R is displayed. In addition, as the navigation voice, for example, “left middle right!” (Indicating that the left reel is the first stop, the middle reel is the second stop, and the right reel is the third stop) Is output.

  When the stop order in which the left reel is first stopped is notified, the stop order of the stop switches 8L, 8C, 8R such as “1--” (indicating that the left reel is the first stop) is indicated. Display stop order images. Further, as the navigation voice, for example, “left!” (Indicating that the left reel is in the first stop) (indicating that the left reel is in the first stop) indicating the stop switch stop order is output. To do. Further, in particular, when the replay GRs 21 to 26 are elected at RT2 and the stop order in which the red 7 replay or the blue 7 replay wins is notified, in addition to the stop order image described above, red 7 and blue 7 are given to each reel. An image that prompts a stop operation at a target timing is also displayed, and a stop operation at that timing is prompted.

  In the navigation notification and the navigation effect, when any one of the replays GR1 to GR6 is won in RT1, the stop order in which the promotion replay wins is identifiable in an identifiable manner. Further, when any of the replays GR11 to GR13 wins at RT0, the stop order in which the special replay wins is notified in an identifiable manner. Further, when any of the replays GR21 to 23 is won at RT2, the stop order in which the middle stage replay or red 7 replay wins is identifiable. In addition, when any of the replays GR24 to 26 is won at RT2, the stop order in which the middle stage replay or the blue 7 replay wins is identifiable.

  In addition, the aspect of a navigation effect is not restricted to such an aspect, What kind of thing may be sufficient if a player is distinguishable according to a winning condition. Further, the navigation effect is not limited to using the liquid crystal display 51 and the speakers 53 and 54, but may be executed using the effect effect LED 52, the reel LED 55, and the like.

  As described above, in the navigation notification and the navigation effect, the stop order that is advantageous to the player is notified in an identifiable manner. For this reason, the player can intentionally win the promotion replay at RT1 and win the middle bell by performing the stop operation in the order of stop according to the navigation effect, and win the special replay at RT0. In other words, winning the middle bell, avoiding the fall replay, avoiding the stoppage of the transitional outcome, winning the middle bell in RT2, avoiding the fall replay, Eye suspension can be avoided.

  In this embodiment, the main control unit 41 controls the ART (RT2 to AT at RT2) when the number of consecutive winnings of replay (normal replay, replay GR1-6, replay GR11-13, replay 21-26) is three. ART lottery to determine whether or not to control. In the ART lottery, two types of winning probabilities are set. And when it wins a specific lottery object combination, it shifts to a high probability state in which the winning probability is high. If a winning combination for a transition to a low probability state is won in a high probability state, a transition is made to a low probability state, and the winning probability of the ART lottery becomes low.

  Then, the main control unit 41 wins the ART lottery and controls the ART when the precursor period ends.

  Also, the main control unit 41 controls the ART so that the sign period ends when the number of consecutive replay winnings is four. In the precursor period, a precursor effect that suggests whether or not to be controlled by ART is executed. When the warning effect is executed, the ART is notified as to whether or not to control as a result of the effect.

  ART is 50 games in one set. When the condition for controlling the ART is satisfied, the right to control is granted to one set of ART (hereinafter, also simply referred to as “granting ART”). Thus, for example, when the number of consecutive replay wins is 3 and the ART lottery is won, and when the number of consecutive replay wins is 4, the ART lottery wins, one set of ART is given and replay is performed. In order to give one set of ART when the number of consecutive winnings is four, a total of two sets of ART are given.

  In this embodiment, the number of games from the end of ART, BB or RB is counted, and the ART is controlled by reaching the specified number of games. However, of the end of ART, BB or RB It is good also as a structure which controls the ART by counting the number of games from any one of the above and reaching the specified number of games. The end of the ART is when the AT ends, but after the AT ends, the game is triggered when the push-out bell is missed and the transition is stopped, or the fall replay wins, that is, the end of RT2. It may be configured to start counting the number.

  When controlling to ART, first control to AT. The state from the start of the AT control to the transition to RT2 is also referred to as a preparation state.

  The main control unit 41 performs navigation notification when the target combination is won in the preparation state. At this time, in RT1, when the replays GR1 to 6 are won, navigation notification is performed, and when the replays GR1 to 6 are won, the stop order for winning the promoted replay is notified by the navigation notification, so stop according to the notified stop order. By performing the operation, it is possible to shift the promotion replay from RT1 to RT0. In addition, after shifting to the preparation state, in any gaming state of RT0 to 2, since the stop order for winning the middle bell is notified when the push order bell is won, the stop operation is performed according to the notified stop order. Thus, it is possible to reliably obtain 8 medals.

  After the promotion replay wins at RT1 and shifts to RT0, it will be the target of navigation notification when winning the replay GR11-13, and the stop order for winning the special replay when winning the replay GR11-13 will be notified by navigation notification. By performing a stop operation in accordance with the notified stop order, it is possible to win a special replay and shift from RT0 to RT2, and avoid a fall replay winning and avoid moving to RT1. In addition, as described above, when the push order bell is won, the stop order for winning the middle bell is informed, so it is possible to reliably obtain 8 medals by performing the stop operation according to the notified stop order. At the same time, it is possible to avoid the stop of the transition and avoid the transition to RT1.

  When the special replay wins at RT0 and shifts to RT2, after that, when the first replay GR21-23 is won, or when the first replay GR24-26 is won, the navigation that informs the stop order of winning the red 7 replay Navigation notification that notifies the stop order for winning the notification or the blue 7 replay is executed, and the stop operation is performed in accordance with the notified stop order, so that the red 7 replay or the blue 7 replay is won and the fall It is possible to avoid replay winning and to shift to RT1. In addition, as described above, when the push order bell is won, the stop order for winning the middle bell is informed, so it is possible to reliably obtain 8 medals by performing the stop operation according to the notified stop order. At the same time, it is possible to avoid the stop of the transition and avoid the transition to RT1.

  The main control unit 41 finishes the preparation state when the red 7 replay or the blue 7 replay wins, and starts the ART control. Accordingly, the main control unit 41 performs an ART game number lottery to determine the number of ART games, sets the number of games won in the ART game number lottery as the remaining number of ART games allocated to the RAM 91c, and Start counting remaining games.

  After the ART starts, the stop order for winning the middle bell when the push order bell is won will be notified, so it is possible to reliably acquire 8 medals by performing the stop operation according to the notified stop order. At the same time, it is possible to avoid the stop of the transition and avoid the transition to RT1. In addition, since the stop order for winning the middle stage replay is notified when the replays GR21 to 26 are won, the stop operation is performed according to the notified stop order, and the winning of the fall replay is avoided and the process proceeds to RT1. Can be avoided.

  Further, during the ART, when the lottery condition is satisfied, an extra lottery is performed to determine whether or not to add the number of ART games. Then, when the winning lottery is won, the ART game number lottery for determining the number of ART games is performed in the same manner as at the start of ART, and the number of games won in the ART game number lottery is determined as the remaining ART allocated to the RAM 91c. Add to the number of games.

  In addition, after the start of ART, every time one game is consumed, the number of remaining games is decremented by 1, and if a special role is elected before the remaining number of games reaches 0, the ART is interrupted by the end of RT2. Accordingly, the counting of the number of ART games is also interrupted. After that, the winning bonus is awarded to the corresponding bonus and the corresponding bonus is controlled. When the transition is stopped at RT3 after the bonus ends, AT control is resumed when the transition to RT1 is resumed. After passing through RT2, the ART is restarted by moving again to RT2, and the counting of the remaining number of games in the ART is also restarted.

  If the number of remaining games becomes 0 after the start of ART, the AT control is terminated. As a result, navigation notification will not be executed, so it will be impossible to avoid the stop of the transitional outcome when winning the push order bell, and it will be impossible to avoid the winning of the fall replay when winning the replay GR21-26. By shifting to RT1 by stopping the game or winning the fall replay, a series of AT and ART controls are completed.

  Further, in the present embodiment, the main control unit 41 is configured to notify the stop order in which the middle stage replay wins except for the first time by navigation notification when winning the replay GRs 21 to 26 during ART. When the stop operation is performed ignoring the order, the red 7 replay or the blue 7 replay may win and RT2 may be maintained, but the fall replay may win and move to RT1. Therefore, when the replays GR21 to 26 are elected, it is possible to prompt the stop operation in the stop order to win the middle stage replay notified by the navigation notification, and it is meaningless to prevent the red 7 replay or the blue 7 replay from winning. It can be done.

  Further, the main control unit 41 performs the ART lottery when the target combination of the ART lottery is won in the internal lottery.

  Next, processing executed by the main control unit 41 according to the user program will be described with reference to FIGS. The main control unit 41 executes a start-up process (main) at the time of start-up associated with power-on or the restart accompanying input of a reset signal.

[Startup processing (main)]
FIG. 19 is a flowchart showing the contents of the startup process (main) executed by the main control unit 41. In the start-up process (main), interrupts are first disabled (Sa1), the parallel output port 513 is initialized (Sa2), and the built-in registers are initialized (Sa3). Next, it is determined whether or not the voltage drop signal from the power interruption detection circuit 48 is detected, that is, whether or not the voltage is unstable (Sa4). If the voltage drop signal is detected, the voltage drop is detected. Wait until no signal is detected.

  If a voltage drop signal is not detected in step Sa4, the address of the program to be executed when an interrupt occurs is set in the I register (Sa5), access to the RAM 41c is permitted (Sa6), and a stack pointer is set. (Sa7).

  Next, the RAM parity of all the storage areas (including the unused area and the unused stack area) of the RAM 41c is calculated (Sa8), and it is determined whether or not the RAM parity is 0 (Sa9). As will be described later, if the power interruption interrupt process (main) is normally performed at the time of the previous power interruption, the RAM parity should be 0. If the RAM parity is not 0 in the step of Sa9, the RAM 41c. In this case, the process proceeds to step Sa13.

  On the other hand, if the RAM parity is 0 in step Sa9, it is further determined whether or not the destructive diagnosis data is normal (Sa10). As will be described later, if the power interruption interrupt process (main) is normally performed at the time of the previous power interruption, the destruction diagnosis data should be set, and the destruction diagnosis data is not normal in step Sa10. If this is the case (when the failure diagnosis data is other than 5A (H) stored at the time of power failure), the data in the RAM 41c is not normal, and the process proceeds to step Sa13.

  If it is determined in step Sa10 that the destructive diagnosis data is normal, the data in the RAM 41c is normal, so the destructive diagnosis data is cleared (Sa11), and the RAM 41c indicates that the data is normal. The normal flag is set in the RAM 41c (Sa12), and the process proceeds to step Sa13.

  In step Sa13, it is determined whether or not the setting key switch 37 is on. If the setting key switch 37 is on, the initializing process for initializing all the storage areas of the RAM 41c except the used stack area is performed. Formula 1 is executed (Sa14). After that, the interruption is permitted (Sa15), and the process proceeds to the setting change process controlled to the setting change state in which the setting value can be changed (Sa16), and the setting changing process is ended by setting a new setting value. Then, the process proceeds to game processing.

  If the setting key switch 37 is off in step Sa13, it is determined whether or not the data in the RAM 41c is normal based on whether or not the RAM normal flag is set (Sa17), and the data in the RAM 41c is determined not to be normal. The initialization 1 similar to the step of Sa14 is executed to initialize all the storage areas except the used stack area among the storage areas of the RAM 41c (Sa18), and interrupts are permitted (Sa19). Then, an error code indicating a RAM abnormality is set (Sa20), and an error process, ie, a RAM abnormality error state is entered. Unlike a normal error, the RAM abnormality error does not return to a state in which the game can proceed until a new set value is set.

  If it is determined in step Sa17 that the data in the RAM 41c is normal, initialization 3 is performed to initialize the non-saved work, the unused area, and the unused stack area in the RAM 41c (Sa21). Thereafter, the stack pointer is restored to the state before power interruption (Sa22), and an input buffer for storing the input state of detection signals such as various switches inputted to the parallel input port 511 is initialized (Sa23).

  Next, it is determined based on the data in the RAM 41c whether or not the stop operation is effective in the state before the power interruption (Sa24). In the step of Sa24, when it is determined that the stop operation was valid in the state before the power interruption, an invalidation flag for temporarily invalidating the stop operation is set in the RAM 41c (Sa25). The acceptance of the stop operation that was valid in the previous state is invalidated (Sa26). When the invalidation flag is set, when the reel reference position is detected for all the rotating reels in the reel rotation processing of FIG. 20, the stop operation corresponding to the rotating reel is validated and invalidated. Clear the enable flag.

  Then, after invalidating the acceptance of the stop operation at step Sa26 and when it is determined at step Sa24 that the stop operation was not effective in the state before the power interruption, the output state of the parallel output port 513 is It returns to the control state before the interruption (Sa27), returns each register to the state before the interruption, that is, the state stored in the stack (Sa28), enables the interrupt (Sa29), and before the interruption The process returns to the last game process. At this time, if the control for driving the reel motor is performed in the state before the power interruption, the control for driving the reel motor is resumed from the excitation pattern at the time of power interruption and the excitation state at the time of the power interruption.

  Thus, in the startup process (main), when the slot machine 1 is powered on, if the control state before power interruption can be restored, the control state before power interruption is restored. In particular, when the control for driving the reel motor is performed in the state before the power interruption, the control for driving the reel motor is resumed from the excitation pattern at the time of power interruption and the excitation state at the time of the power interruption. On the other hand, whether or not the stop operation was effective in the control state before the power interruption, and if the stop operation was effective in the control state before the power interruption, was effective in the control state before the power interruption By setting an invalidation flag for temporarily invalidating the stop operation, reception of the stop operation in which the stop operation was valid in the control state before the power interruption is invalidated.

[Game processing]
FIG. 20 is a flowchart showing the contents of the game process executed by the main control unit 41.

  In the game process, a BET process (Sd1), an internal lottery process (Sd2), a privilege grant process (Sd3), a reel rotation process (Sd4), a winning determination process (Sd5), a payout process (Sd6), and a game end process (Sd7) ) Are executed in order, and when the game end process ends, the BET process is executed again in order.

  In the BET process in the step of Sd1, the process waits in a state where a bet number can be set, and a process for starting a game when a specified number of bets is set according to the gaming state and the start switch 7 is operated is executed. .

  In the internal lottery process in the step of Sd2, a process is performed for determining whether or not winning in each of the above-mentioned winning combinations is allowed based on the internal lottery random value latched when the start switch 7 is detected in the step of Sd1. In this internal lottery process, a winning flag is set in the RAM 41c based on the respective lottery results.

  In the privilege granting process in Sd3, the right to control to the ART that is a privilege is granted according to the number of times that the replay (normal replay, replay GR1 to 6, replay GR11 to 13, replay GR21 to 26) is won (hereinafter simply referred to as “ART”). (Also referred to as “granting”). Specifically, when the number of consecutive winnings of the replay (normal replay, replay GR1 to 6, replay GR11 to 13, replay 21 to 26) is three times, the state is changed to ART (state controlled by AT in RT2). An ART lottery for determining whether to control is performed. When an ART lottery is won, an ART is awarded. An ART is also awarded when the number of consecutive replay wins is four. Therefore, if the ART lottery is won but the number of consecutive replay wins is not four, one set (50 games) of ART is awarded. Also, one set of ART is given when the ART lottery is not won but the number of consecutive replay wins is four. In addition, when the ART lottery is won and two consecutive replay wins are made, two sets of ARTs are awarded.

  In the reel rotation process in the step of Sd4, the process of rotating the reels 2L, 2C, and 2R and the operation of the corresponding reels 2L, 2C, and 2R according to the detection of the operation of the stop switches 8L, 8C, and 8R by the player are detected. A process for stopping the rotation is executed.

  In the payout process in step Sd6, when it is determined that a prize is generated in step Sd4, processing such as addition of credits and payout of medals is performed based on the number of payouts according to the win.

  In the game end process in the step of Sd7, a process for setting a gaming state in preparation for the next game is executed.

[Bonus grant processing]
Next, a privilege grant process executed by the main control unit 41 in step Sd3 of the game process will be described.

  As shown in FIG. 21, in the privilege grant process, the main control unit 41 first determines whether or not the replay is won based on the result of the internal lottery (Sj1). When the replay is won (Y in Sj1), 1 is added to the count value of the replay winning number counter for counting the number of consecutive replay winnings (Sj2). Note that when a replay is won, the replay always wins regardless of the operation timing of the stop switches 8L, 8C, and 8R. Therefore, the number of replay wins can be counted by counting the number of wins for the replay. Therefore, in this embodiment, the number of times that the replay is won is counted as the number of times that the replay has won.

  Next, it is determined whether or not the count value of the replay winning counter is 3 (Sj3). When the count value is 3 (Y in Sj3), ART lottery is executed (Sj4). Then, it is determined whether or not the ART lottery has been won (Sj5). If the ART lottery has not been won (N in Sj5), the process is terminated.

  When the ART lottery is won (Y in Sj5), an ART execution flag indicating that the ART is executed is set in the RAM 41c (Sj6). Then, 50 games for one set are set in the ART game number counter for counting the number of games at ART (Sj7).

  If the ART lottery is won, AT is started after 5 games are digested from the next game (that is, after 6 games). Then, during the precursor period until the start of AT, the sub-control unit 91 performs the precursor effect and notifies whether or not ART has been given.

  On the other hand, if it is determined in step Sj3 that the count value of the replay winning number counter is not 3 (N in Sj3), it is determined whether or not the count value is 4 (Sj8). If the count value is not 4 (N in Sj8), the process ends.

  When the count value is 4 (Y in Sj8), the ART execution flag is set (Sj9), and the number of games for one set is set in the ART game number counter (Sj10). Then, the count value of the replay winning number counter is cleared (Sj11). If the ART execution flag has already been set, the process of Sj9 is omitted.

  If it is determined in step Sj1 that the replay is not won (N in Sj1), the count value of the replay winning number counter is cleared (Sj12).

  In this embodiment, the count value of the replay winning number counter is cleared when the number of consecutive replay winnings is four, but further, the ART is given by counting the number of consecutive replay winnings. Is also possible. Further, when the ART lottery is won during the precursor period, or when the number of consecutive replay wins is four, ART may be given, or ART may not be given during the precursor period.

  As described above, when the replay is won three times in succession and the ART lottery is won, one set of ART is determined. Further, if the replay is won three times in succession, one more set of ART is confirmed.

Next, the contents of processing executed by the sub control unit 91 will be described.
[Timer interrupt processing (sub)]
Next, timer interrupt processing (sub) executed by the sub control unit 91 (CPU 91c) at intervals of 1.12 ms based on the count value of the internal clock will be described.

  As shown in FIG. 22, in the timer interrupt process (sub), the sub control unit 91 first saves the register in use to the stack area (Sp1). Next, a power failure determination process is performed (Sp2). In the power failure determination process, it is determined whether or not a voltage drop signal is input from the power failure detection circuit 48. If a voltage drop signal is input, whether or not the voltage drop signal is input in the previous power failure determination process as well. If a voltage drop signal has been input in the previous power failure determination process, it is determined that a power failure has occurred, and a power interruption flag indicating that is set.

  After the power failure determination process in the step of Sp2, it is determined whether or not the power interruption flag is set (Sp3). If the power interruption flag is set, the process proceeds to a power interruption process (sub). In the power interruption process (sub), the backup flag used in the startup process (sub) is set after the backup data is created, and the checksum is calculated by calculating the exclusive OR of the backup data.

  If the power interruption flag is not set, command analysis processing is executed (Sp4). In the command analysis process, it is determined whether or not a command is stored in the command buffer. If the command is stored in the command buffer, the command is acquired from the command buffer. And the process according to the acquired command is performed.

  Next, effect determination processing for determining the type of effect is executed (Sp5).

  Next, an effect execution process for executing the effect determined in the effect determination process is executed (Sp6).

  In the winning determination process in step Sd5, when it is determined in step Sd3 that the rotation of all the reels 2L, 2C, 2R has been stopped, a winning is determined according to the display result derived for each reel 2L, 2C, 2R. A process of determining whether or not it has occurred is executed.

  Next, an ART notification process for notifying whether or not to provide ART is executed (Sp7).

  Next, a winning history notifying process for notifying the winning history is executed (Sp8). The notification of the winning history is performed by displaying on the liquid crystal display 51. Specifically, for example, winning histories for the past five games are displayed. In the display of the winning history, not only the winning combination display but also the fact that none of the winning combinations has been won is displayed. The player can confirm the number of consecutive winnings of replay by confirming the winning history.

  Next, a precursor effect preparation process for preparing for executing the precursor effect is executed (Sp9).

[Precursor selection preparation process]
Next, the warning effect preparation process executed in Sp9 of FIG. 22 will be described.

  As shown in FIG. 23, in the indication effect preparation process, the sub-control unit 91 first determines whether or not a third stop operation has been performed (Sf1). If the third stop operation has not been performed (N in Sf1), the process ends.

  When the third stop operation is performed (Y in Sf1), it is determined whether or not the replay is won by internal lottery (Sf2). If the replay is not won (N in Sf2), the process ends.

  When the replay is won (Y in Sf2), 1 is added to the count value of the replay winning number counter for counting the number of consecutive replay winnings (Sf3).

  Next, it is determined whether or not the count value of the replay winning counter is “3” (Sf4). When the count value becomes “3”, a warning effect restriction flag for restricting execution of the warning effect is set in the RAM 91c (Sf5). Then, a precursor effect execution flag indicating execution of the precursor effect is set in the RAM 91c (Sf6). Next, the number of games is set in a precursor effect counter that counts the number of precursor effect games (Sf7).

  On the other hand, if it is determined in step Sf4 that the count value is not “3” (N in Sf4), it is determined whether the count value is “4” (Sf8). If the count value is not “4”, the process is terminated. When the count value is “4” (Y in Sf8), the count value of the replay winning number counter is cleared (Sf9), and the processes of Sf6 to Sf7 are performed. Note that the count value of the replay winning number counter is also cleared when a lottery subject other than replay is won in the internal lottery or when the player loses.

[Direction determination processing]
Next, the effect determination process executed in Sp10 of FIG. 22 will be described.

  As shown in FIG. 24, in the effect determination process, the sub-control unit 91 first determines whether or not an internal winning command has been received (Sg1). If no internal winning command has been received (N in Sg1), the process is terminated. When the internal winning command is received (Y in Sg1), it is determined whether or not the precursor effect execution flag set in Sf6 of FIG. 23 is set (Sg2). In addition, since the indication effect limit flag is set at the end of the game in which the number of consecutive winnings of replay is three (see FIG. 23), when the indication effect limit flag is set, the number of consecutive winnings of replay is 3. It is the next game after the game that became the times.

  If the indication effect execution flag is set (Y in Sg2), it is determined whether or not the internal lottery has been lost (no lottery target combination has been drawn) (Sg3). Since no winning combination is won when lost, in this step, it is determined whether or not the player loses when the reel stops.

  If it is lost (Y in Sg3), it is determined whether or not the precursor effect limit flag set in Sf5 of FIG. 23 is set (Sg4).

  When the warning effect limit flag is set (Y in Sg4), an effect determination lottery for determining the type of effect is executed (Sg5).

  At this time, the effect determination lottery is executed using a precursor loss table that determines the effect mode of the precursor effect when the internal lottery is lost. The effects selected at the sign loss table include an effect that is executed only when a loss occurs, and an effect that is executed when both a loss and a replay are won. For example, a replay notification effect that suggests that the probability of winning a replay is high as a common effect. In the sign loss table, the number of determination values is set so that the selection probability of the replay notification effect is higher than that in the normal lose table that determines the effect when the sign is lost at the normal time when the sign effect is not executed.

  The sign production is executed when the number of consecutive replay winnings reaches three times and the expectation for the provision of ART can be expected. Therefore, when the replay notification effect at the time of losing is executed, the player's expectation that ART will be given increases. Whether or not it is a replay notification effect at the time of losing can be determined when the reel is stopped. For this reason, although the replay notification effect is executed, the effect of the effect can be achieved when the reel is lost when the reel is stopped.

  Next, it is determined whether or not the replay notification effect is determined (Sg6). As a result of the effect determination lottery, when the replay notification effect is determined (Y in Sg6), the effect determination lottery is executed again (Sg5). By this process, when a game is lost after the game where the number of consecutive winnings of replay is 3, the replay notification effect at the time of the loss is not executed.

  On the other hand, when the effect other than the replay notification effect is determined (N in Sg6), the precursor effect limit flag is cleared (Sg7). Then, “1” is subtracted from the count value of the indication effect counter (Sg7a), and an effect determination flag indicating the determined effect type is set in the RAM 91c (Sg11). When the effect determination flag is set, the effect of the aspect indicated by the effect determination flag is executed in the process of Sp6 in FIG. Then, the effect determination flag is cleared after the effect is executed.

  If it is determined in step Sg4 that the warning effect limit flag is not set (N in Sg4), the count value of the warning effect counter in which the number of games is set in Sf7 of FIG. 23 is subtracted (Sg8). Then, it is determined whether or not the count value of the indication effect counter has become “0” (Sg9).

  When the count value of the sign effect counter is not 0 (Sg9), the effect determination lottery is executed using the sign loss table as in Sg5 (Sg10). Then, the effect determination flag is set in the RAM 91c (Sg11). When the effect determination flag is set, the effect of the aspect indicated by the effect determination flag is executed in the process of Sp6 in FIG. Then, the effect determination flag is cleared after the effect is executed.

  When it is determined in step Sg9 that the count value is 0 (Y in Sg9), a notification flag indicating that notification of whether or not ART has been given is set in the RAM 91c (Sg12). Then, the precursor effect execution flag is cleared (Sg13). When the notification flag is set, the notification is executed by the processing of Sp7 in FIG. Then, when the number of consecutive replay wins is four times or when the number of consecutive replay wins is three and the ART lottery is won, a notification that the ART has been awarded is given. In addition, when ART is not given, that is notified.

  As shown in FIG. 25, when it is determined in step Sg3 that it is not lost (N in Sg3), it is determined whether or not the replay is won (Sg14). If the replay is not won (N in Sg14), the process is terminated. When the replay is won (Y in Sg14), the effect determination lottery is executed (Sg15).

  At this time, the effect determination lottery is executed using the precursor replay table that determines the effect mode of the precursor effect when the replay is won in the internal lottery. The effects selected in the precursor replay table include effects that are executed only when a replay is won, and probabilities that are executed in common when both a loss and a replay are won. For example, a replay notification effect suggesting that the probability of winning a replay is high is included as a common effect. In the sign replay table, the number of determination values is set so that the selection probability of the replay notification effect is lower than the normal replay table that determines the effect when the replay is won in the normal time when the sign effect is not executed. In addition, the replay notification effect at the time of replay winning has a lower selection probability at the time of the sign effect and a higher selection probability at the normal time than the replay notification effect at the time of losing.

  Therefore, even if the replay notification effect at the time of winning the replay is executed, there is a high possibility that it is a normal time. In addition, when the replay notification effect at the time of replay win is executed, there is a higher possibility that it is a normal time than when the replay notification effect at the time of losing is executed. For this reason, the player has a higher expectation for the replay notification effect at the time of losing.

  Next, it is determined whether or not a precursor effect restriction flag is set (Sg16). When the warning effect restriction flag is set (Y in Sg16), the warning effect restriction flag is cleared (Sg17). If the warning effect restriction flag is not set (N in Sg16), the process proceeds to Sg18. In step Sg18, “1” is subtracted from the count value of the indication effect counter (Sg18). Then, it is determined whether or not the count value of the indication effect counter has become “0” (Sg19).

  If the count value of the indication effect counter is not 0 (Sg9), the effect determination flag is set in the RAM 91c (Sg20). When the effect determination flag is set, the effect of the aspect indicated by the effect determination flag is executed in the process of Sp6 in FIG. Then, the effect determination flag is cleared after the effect is executed.

  If it is determined in step Sg19 that the count value is 0 (Y in Sg19), the notification flag is set in the RAM 91c as in Sg12 (Sg21). Then, the precursor effect execution flag is cleared (Sg22).

  When the notification flag is set, the notification is executed by the processing of Sp7 in FIG. Then, when the number of consecutive replay wins is four times or when the number of consecutive replay wins is three and the ART lottery is won, a notification that the ART has been awarded is given. In addition, when ART is not given, that is notified.

  As shown in FIG. 26, when it is determined in step Sg2 that the indication effect execution flag is not set (N in Sg2), it is determined whether or not the internal lottery results in a loss (Sg23).

  When it is lost (Y in Sg23), the effect determination lottery is executed (Sg24). At this time, the effect determination lottery is executed using the normal lose table.

  The effect of the normal lose table includes an effect that is executed only when the game is lost, and an effect that is executed in common when both the game is lost and the replay is won. For example, the replay notification effect is included in the normal lose table effect, but as described above, the number of determination values is set so that the probability of determining the replay notification effect is lower than the precursor loss table. ing.

  When the effect determination lottery ends, an effect determination flag is set in the RAM 91c (Sg25). When the effect determination flag is set, the effect of the aspect indicated by the effect determination flag is executed in the process of Sp6 in FIG. Then, the effect determination flag is cleared after the effect is executed.

  If it is not lost (N in Sg23), it is determined whether or not the replay is won (Sg26). If the replay is not won (N in Sg26), the process is terminated. When the replay is won (Y in Sg26), the effect determination lottery is executed (Sg27). At this time, the effect determination lottery is executed using the normal replay table.

  The effect of the normal replay table includes an effect that is executed only when the replay is won, and an effect of the probability that the replay table is executed both when the game is lost and when the replay is won. For example, the replay table effect includes the replay notification effect, but as described above, the number of determination values is set so that the probability of determining the replay notification effect is higher than the precursor replay table. Yes.

  When the effect determination lottery ends, an effect determination flag is set in the RAM 91c (Sg28). When the effect determination flag is set, the effect of the aspect indicated by the effect determination flag is executed in the process of Sp6 in FIG. Then, the effect determination flag is cleared after the effect is executed.

[Modified example of effect determination processing in the first embodiment]
Next, a modification of the effect determination process executed in Sp10 of FIG. 22 will be described.

  As shown in FIG. 27, in the effect determination process, the sub-control unit 91 first determines whether or not an internal winning command has been received (Sh1). If the internal winning command has not been received (N in Sh1), the process ends. When the internal winning command is received (Y in Sh1), it is determined whether or not the precursor effect execution flag set in Sf6 of FIG. 23 is set (Sh2). In addition, since the indication effect limit flag is set at the end of the game in which the number of consecutive winnings of replay is three (see FIG. 23), when the indication effect limit flag is set, the number of consecutive winnings of replay is 3. It is the next game after the game that became the times. If it is determined that the warning effect execution flag is not set (N in Sh2), the process of FIG. 26 is executed. The processing in FIG. 26 is as described above.

  If the indication effect execution flag is set (Y in Sh2), it is determined whether or not the internal lottery has been lost (no lottery target combination has been drawn) (Sh3). Since no winning combination is won when lost, in this step, it is determined whether or not the player loses when the reel stops. If it is determined that it is not lost (N in Sh3), the process of FIG. 25 is executed. The processing in FIG. 25 is as described above.

  If it is lost (Y in Sh3), it is determined whether or not the precursor effect limit flag set in Sf5 of FIG. 23 is set (Sh4).

  When the warning effect limit flag is set (Y in Sh4), the effect determination lottery for determining the type of effect is executed (Sh5).

  At this time, the effect determination lottery is executed by using the sign limit time table for when the game is lost in the next game after the game where the number of consecutive winnings of the replay is three. That is, the sign limit time table is used when the number of consecutive replay winnings is 4 and the game is lost in a state where ART can be given. The effects selected on the sign limit table include an effect that is executed only when the player loses, and an effect that is executed when both the player loses and wins the replay. . However, the replay notification effect is excluded from the common effects. Thereby, even if the game is lost after the game where the number of consecutive winnings of the replay is 3, the replay notification effect at the time of the loss is not executed.

  Next, the warning effect restriction flag is cleared (Sh6). Then, “1” is subtracted from the count value of the indication effect counter (Sg6a), and an effect determination flag indicating the determined effect type is set in the RAM 91c (Sh10). When the effect determination flag is set, the effect of the aspect indicated by the effect determination flag is executed in the process of Sp6 in FIG. Then, the effect determination flag is cleared after the effect is executed.

  If it is determined in step Sh4 that the warning effect limit flag is not set (N in Sh4), the count value of the warning effect counter in which the number of games is set in Sf7 of FIG. 23 is subtracted (Sh7). Then, it is determined whether or not the count value of the precursor effect counter has become “0” (Sh8).

  When the count value of the precursor effect counter is not 0 (N in Sh8), the effect determination lottery is executed using the precursor loss table as in Sh5 (Sh9). Then, the effect determination flag is set in the RAM 91c (Sh10). When the effect determination flag is set, the effect of the aspect indicated by the effect determination flag is executed in the process of Sp6 in FIG. Then, the effect determination flag is cleared after the effect is executed.

  When it is determined in step Sg9 that the count value is 0 (Y in Sh8), a notification flag indicating that notification of whether or not ART has been given is set in the RAM 91c (Sh8). Then, the precursor effect execution flag is cleared (Sh12).

  When the notification flag is set, the notification is executed by the processing of Sp7 in FIG. Then, when the number of consecutive replay wins is four times or when the number of consecutive replay wins is three and the ART lottery is won, a notification that the ART has been awarded is given. In addition, when ART is not given, that is notified.

[Specific Example of First Embodiment]
Next, a specific example of the first embodiment will be described with reference to FIG. The game won for replay will be described as the first game.

  As shown in FIG. 28 (a), it is assumed that the replay is won continuously in the first to third games in normal time (non-AT, non-ART and when the precursor effect is not executed). If the replay is won in the fourth game, the provision of ART is confirmed, so the fourth game is in a state where the ART can be confirmed. When the game is lost in the fourth game, when the replay notification effect is determined in the effect determination lottery, the effect determination lottery is executed again to exclude the replay notification effect at the time of the loss. In the game, the player notices that replay wins. On the other hand, the replay notification effect at the time of losing is an effect that has a high probability of being executed as a precursor effect and increases the player's expectation. However, if it is executed in the game, it will be confirmed that the reel will be lost and no ART will be given, which will betray the player's expectation. Therefore, the interest of the player in the game is reduced. For this reason, by excluding the replay notification effect in the fourth game, it is possible to prevent the player's expectation from being betrayed and the player's expectation being betrayed even though the ART is not given. In addition, in this example, the replay notification effect at the time of losing is excluded by executing the effect determination lottery again, so the data amount can be reduced compared with the case where the lottery is performed using the table excluding the replay notification effect. Can do. Thereafter, a prelude effect is executed up to the fifth to seventh games, and notification is made as to whether or not ART is given in the eighth game.

  In the first embodiment, when the winning probability state of the ART lottery is in the low probability state, the sub-control unit 91 executes the effect determination lottery using the normal lose table when the internal lottery is lost. When shifting to the high probability state, when the internal lottery results in a loss, the effect determination lottery is executed using the precursor loss table. Therefore, when the winning probability state of the ART lottery is a high probability state, the sign effect is executed and the frequency of executing the replay notification effect at the time of losing is increased.

  As shown in FIG. 28 (b), it is assumed that the replay is continuously won in the first to third games in normal time (non-AT time, non-ART time, and when the warning effect is not executed). If the replay is won in the fourth game, the provision of ART is confirmed, so the fourth game is in a state where the ART can be confirmed. When the game is lost in the fourth game, the replay notification effect at the time of the loss is excluded by using the sign limit table in the effect determination lottery. In the game, the player notices that replay wins. On the other hand, the replay notification effect at the time of losing is an effect that has a high probability of being executed as a precursor effect and increases the player's expectation. However, if it is executed in the game, it will be confirmed that the reel will be lost and no ART will be given, which will betray the player's expectation. Therefore, the interest of the player in the game is reduced. For this reason, by excluding the replay notification effect in the fourth game, it is possible to prevent the player's expectation from being betrayed and the player's expectation being betrayed even though the ART is not given. Thereafter, a prelude effect is executed up to the fifth to seventh games, and notification is made as to whether or not ART is given in the eighth game.

[Second Embodiment]
Next, the second embodiment will be described. However, detailed description of parts common to the first embodiment will be omitted, and parts different from the first embodiment will be described.

[Bonus grant processing in the second embodiment]
Next, a privilege grant process executed by the main control unit 41 in step Sd3 of the game process will be described.

  As shown in FIG. 29, in the privilege grant process, the main control unit 41 first determines whether or not the replay is won based on the result of the internal lottery (Sn1). When the replay is won (Y in Sn1), the count value of the replay winning number counter for counting the number of consecutive replay winnings is incremented by 1 (Sn2). Note that when a replay is won, the replay always wins regardless of the operation timing of the stop switches 8L, 8C, and 8R. Therefore, the number of replay wins can be counted by counting the number of wins for the replay. Therefore, in this embodiment, the number of times that the replay is won is counted as the number of times that the replay has won.

  Next, it is determined whether or not the count value of the replay winning number counter has become 2 (Sn3). When the count value becomes 3 (Y at Sn3), ART lottery is executed (Sn4). Then, it is determined whether or not the ART lottery has been won (Sn5). If the ART lottery has not been won (N in Sn5), the process is terminated.

  When the ART lottery is won (Y in Sn5), an ART execution flag indicating that the ART is executed is set in the RAM 41c (Sn6). Then, 50 games for one set are set in the ART game number counter for counting the number of games at ART (Sn7).

  If the ART lottery is won, AT is started after 5 games are digested from the next game (that is, after 6 games). Then, during the precursor period until the start of AT, the sub-control unit 91 performs the precursor effect and notifies whether or not ART has been given.

  On the other hand, in the step of Sn3, when it is determined that the count value of the replay winning number counter is not 2 (N in Sn3), it is determined whether or not the count value is 3 (Sn8). If the count value is not 3 (N in Sn8), the process is terminated.

  If the count value is 3 (Y in Sj8), the ART execution flag is set (Sn9), and the number of games for one set is set in the ART game number counter (Sn10). If the ART execution flag has already been set, the Sn9 process is omitted.

  On the other hand, in the step of Sn8, if it is determined that the count value of the replay winning number counter is not 3 (N in Sn8), it is determined whether or not the count value is 4 (Sn11). If the count value is not 4 (N at Sn11), the process is terminated.

  If the count value is 4 (Y in Sj11), the ART execution flag is set (Sn12), and the number of games for one set is set in the ART game number counter (Sn13). Then, the count value of the replay winning number counter is cleared (Sn14). If the ART execution flag has already been set, the Sn12 process is omitted.

  In this embodiment, the count value of the replay winning number counter is cleared when the number of consecutive replay winnings is four, but further, the ART is given by counting the number of consecutive replay winnings. Is also possible. Further, when the ART lottery is won during the precursor period, or when the number of consecutive replay wins is four, ART may be given, or ART may not be given during the precursor period.

  As described above, when the replay is won twice in succession and the ART lottery is won, one set of ART is determined. Further, when the replay is won three times in succession, one set of ART is decided, and when the replay is won four times in succession, another set of ART is decided.

[Precursor selection preparation process in the second embodiment]
Next, the warning effect preparation process executed in Sp9 of FIG. 22 will be described.

  As shown in FIG. 30, in the indication effect preparation process, the sub-control unit 91 first determines whether or not a third stop operation has been performed (Sr1). If the third stop operation has not been performed (N in Sr1), the process ends.

  When the third stop operation is performed (Y in Sr1), it is determined whether or not the replay is won by internal lottery (Sr2). If the replay is not won (N in Sr2), the process ends.

  When the replay is won (Y in Sr2), 1 is added to the count value of the replay winning number counter for counting the number of consecutive replay winnings (Sr3).

  Next, it is determined whether or not the count value of the replay winning number counter is “2” (Sr4). When the count value becomes “2”, it is determined whether or not the ART lottery in Sn4 of FIG. 29 is won (Sr5). If the ART lottery is not won (N in Sr5), the process ends.

  When the ART lottery is won (Y in Sr5), a warning effect restriction flag for restricting the execution of the warning effect is set in the RAM 91c (Sr6). Then, a precursor effect execution flag indicating execution of the precursor effect is set in the RAM 91c (Sr7). Next, the number of games is set in a precursor effect counter that counts the number of precursor effect games (Sr8).

  On the other hand, if it is determined in step Sr4 that the count value is not “2” (N in Sr4), it is determined whether the count value is “3” (Sr9). When the count value is “3” (Y in Sr9), the processing of Sr6 to Sr8 is performed.

  When the count value is not “3” (N in Sr9), it is determined whether or not the count value is “4” (Sr10). When the count value is “4” (Y in Sr10), the count value of the replay winning number counter is cleared (Sr11), and the processes of Sr7 to Sr8 are performed. If the count value is not “4” (N in Sr10), the process ends. Note that the count value of the replay winning number counter is also cleared when a lottery subject other than replay is won in the internal lottery or when the player loses.

[Direction determination processing]
Next, the effect determination process executed in Sp10 of FIG. 22 will be described.

  As shown in FIG. 31, in the effect determination process, the sub-control unit 91 first determines whether or not an internal winning command has been received (Se1). If the internal winning command has not been received (N at Se1), the process is terminated. When the internal winning command is received (Y in Se1), it is determined whether or not the precursor effect execution flag set in Sr7 of FIG. 30 is set (Se2). The sign effect restriction flag is set at the end of the game when the number of consecutive winnings of replay is 2 and the ART lottery is won, or when the number of consecutive winnings of replay is 3 (see FIG. 30). (Refer to the previous game) When the sign production restriction flag is set, the number of consecutive replay wins is 2 and the game after the game that has won the ART lottery, or the number of consecutive replay wins is 3 The next game.

  If the indication effect execution flag is not set (N in Se2), the process proceeds to se5. When the warning effect execution flag is set (Y in Se2), it is determined whether or not the warning effect restriction flag set in Sr6 or Sr12 of FIG. 30 is set (Se3).

  If it is determined in step Se2 that the precursor effect execution flag is not set (N in Se2), or if the precursor effect restriction flag is set (Y in Se3), the type of effect is determined. An effect determination lottery is executed (Se5).

  At this time, the effect determination lottery is executed using the normal table for determining the effect mode at the normal time (non-AT time, non-ART time, and when the warning effect is not executed). The effects selected in the normal table include effects only in the normal time and effects common to the warning effect, but the effects that suggest or notify that the ART at the time of the warning effect is given are excluded.

  Next, an effect determination flag indicating the determined effect type is set in the RAM 91c (Se6), and the sign effect limit flag is cleared (Se7). When the effect determination flag is set, the effect of the aspect indicated by the effect determination flag is executed in the process of Sp6 in FIG. Then, the effect determination flag is cleared after the effect is executed.

  If it is determined in step Se3 that the warning effect restriction flag is not set (N in Se3), the warning effect restriction flag is cleared (Se8), and the warning effect counter in which the number of games is set in Sr8 in FIG. The count value is subtracted by “1” (Se9). Then, it is determined whether or not the count value of the indication effect counter has become “0” (Se10).

  If the count value of the indication effect counter is not 0 (N in Se10), an effect determination lottery is executed (Se11).

  At this time, the effect determination lottery is executed using the precursor table that determines the effect mode at the time of executing the precursor effect. The production selected in the sign table includes production only during the sign production and production common to the normal production, but suggests or notifies that the ART is given as the production only during the sign production. Production is included.

  Then, the effect determination flag is set in the RAM 91c (Se12). When the effect determination flag is set, the effect of the aspect indicated by the effect determination flag is executed in the process of Sp6 in FIG. Then, the effect determination flag is cleared after the effect is executed.

  When it is determined in step Sg9 that the count value is 0 (Y in Se10), a notification flag indicating that notification of whether or not ART has been given is set in the RAM 91c (Se13). Then, the precursor effect execution flag is cleared (Se14). When the notification flag is set, the notification is executed by the processing of Sp7 in FIG. When the number of consecutive replay wins is 3 or 4, or when the number of consecutive replay wins is 2 and the ART lottery is won, a notification that the ART has been awarded is given. In addition, when ART is not given, that is notified.

[Specific Example of Second Embodiment]
Next, a specific example of the second embodiment will be described with reference to FIG. The game won for replay will be described as the first game.

  As shown in FIG. 32 (a), it is assumed that the replay is won continuously in the first to third games in the normal time (non-AT, non-ART, and the indication effect is not executed). Assume that the ART lottery of the second game was not won. Since replay has been won continuously up to the third game, the grant of one set of ART is confirmed at this point. In this case, in the third game and the fourth game, by performing the effect determination lottery using the normal table, the sign effect that suggests or notifies that the ART is given up to the fourth game is not executed. ing. In the second embodiment, when a replay is won in the fourth game, one set of ART is given. However, if a warning effect that notifies that an ART is given in the third game is executed, if the same effect is executed when an ART is given in the fourth game, an ART notification is given in the fourth game. Because it will be two games in a row, it creates a sense of incongruity. In addition, if an indication effect that suggests or notifies that the ART is given in the third game is executed, the provision of the ART is already determined at the time before the start of the fourth game, so the replay is performed in the fourth game. As a result, the degree of attention to winning a prize will be reduced, and the expectation for continuous winning of replay will be diminished. For this reason, a normal table is used in the third game and the fourth game so that the suggestion and notification that the ART has been given is not performed until the fourth game, and the warning effect is executed from the fifth game onward. By suggesting or notifying that the ART has been given in the third game or the fourth game, the expectation that a replay will be won in the fourth game is not hindered, and the interest of the game can be improved. it can. Thereafter, a prelude effect is executed up to the fifth to seventh games, and notification is made as to whether or not ART is given in the eighth game.

  As shown in FIG. 32 (b), it is assumed that the replay is won continuously in the first and second games in normal time (non-AT time, non-ART time, and when the warning effect is not executed). Assume that the ART lottery of the second game is won. Since the ART lottery has been won, the grant of one set of ART is confirmed at this point. It is also assumed that the third game and the fourth game are lost in the internal lottery. In this case, in the second game and the third game, the effect determination lottery is executed using the normal table so that the warning effect that suggests or notifies that the ART is given is not executed until the third game. ing. In the second embodiment, when a replay is won in the third game, one set of ART is given. However, if a precursor effect that informs that the ART is given in the second game is executed, a similar effect is executed when the ART is given in the third game, and an ART notice is given in the third game. Because it will be two games in a row, it creates a sense of incongruity. In addition, if an indication effect that suggests or notifies that the ART is given in the second game is executed, the giving of the ART is already determined before the start of the second game, so the replay is done in the third game. As a result, the degree of attention to winning a prize will be reduced, and the expectation for continuous winning of replay will be diminished. For this reason, a normal table is used in the second game and the third game, so that no suggestion or notification is given that the ART has been given until the third game, and the warning effect is executed from the fourth game onward. By suggesting or notifying that the ART has been granted in the second game or the third game, the expectation that a replay will be won in the third game is not hindered, and the interest of the game can be improved. it can. Thereafter, a prelude effect is executed for the 4th to 6th games, and a notification is made as to whether or not ART is given in the 7th game.

  In the second embodiment, the normal table is set in the next game after the game in which the number of consecutive winnings of replay is two and the ART lottery is won, or the game after the number of consecutive winnings of replay is three. Although an example of using is given, when a precursor effect that suggests or notifies that ART is given using the precursor table is selected in the game, the precursor effect may be excluded by performing lottery again. Is possible. In addition, in the game, the sign effect that suggests or notifies that the ART is given is excluded, but a table common to the sign effect table can be used for other effects.

[Modifications of First Embodiment and Second Embodiment]
Below, the modification of 1st Embodiment and 2nd Embodiment is demonstrated based on FIGS. In practicing the present invention, in the slot machine 1 of the first and second embodiments, it is possible to execute the initial setting process of FIGS. 33 and 34 instead of the startup process (main) of FIG. . It is also possible to execute various processes shown in FIGS. Further, the microcomputer used in the slot machine 1 can be configured as shown in FIGS.

  Then, in the slot machine shown in this modification, in the fourth game when the number of consecutive replay wins is 3, the first implementation is performed by restricting the execution of the replay notification effect by the method shown in FIG. The effect produced in the form can be obtained. In addition, when the number of consecutive replay wins is 3, the effect produced in the second embodiment can be obtained by executing the precursor effect by the method shown in FIG. 32 after the fifth game.

  Below, the various control content which the main control part 41 in this modification performs is demonstrated.

[Initial setting processing]
First, an initial setting process executed by the main control unit 41 will be described. When power is supplied and a reset signal is input from the reset circuit 49, the main control unit 41 performs a system reset and executes a startup process. Then, by executing the startup process, IMF described later becomes 0, and an interrupt prohibited state is set. In addition, an initial value is set in an internal function register (such as a CTC control register or a register related to a random number circuit) by the activation process. Thereafter, the initial setting process shown in the flowcharts of FIGS. 33 and 34 is performed according to the program stored in the ROM 41b as the user program.

  As shown in FIGS. 33 and 34, the main control unit 41 first sets an interrupt master permission flag (IMF) = 0 by executing a DI instruction described later, and prohibits the interrupt (Sa1). The interrupt process is a process that occurs by interrupting the basic process when an interrupt factor occurs. The main control unit 41 described with reference to FIGS. 38 and 39 prohibits the interruption of the timer interrupt process (main) executed at regular intervals (interval of 0.56 ms) (Sa1). Next, initialization data is set (Sa2), and each output port is initialized (Sa3). Next, the built-in register is set (Sa4).

  In the setting of the internal register, for example, the random number circuits 508a and 508b are set. Specifically, in the setting of the random number circuit, the main control unit 41 writes the random number maximum value setting data for specifying the random number maximum value preset by the user in the built-in register. In addition, the main control unit 41 checks whether the maximum random number set in the built-in register is not less than a predetermined lower limit value. If the random number maximum value is less than the lower limit value, the main control unit 41 is set in the random number maximum value setting register. Execute random number maximum value reset processing to reset the random number maximum value.

  Further, the main control unit 41 executes an initial value changing process for changing the initial value of the count value updated by the counters of the random number circuits 508a and 508b. Further, the main control unit 41 writes the random number update method selection data in the random number update method selection register. Further, the main control unit 41 writes period setting data (data for setting how many times the reference clock signal is to be divided) for designating the period of the random number generating clock signal preset by the user. Further, the main control unit 41 sets whether or not to update the initial value input to the counter when the count value is updated to a predetermined final value by the counters of the random number circuits 508a and 508b. Further, the main control unit 41 sets whether or not to change the permutation of the count values updated by the counter when the count values are updated to a predetermined final value by the counters of the random number circuits 508a and 508b. Then, the main control unit 41 writes random circuit activation data. By doing so, the main control unit 41 activates the random number circuits 508a and 508b.

  Next, it is determined whether or not the power supply voltage is normal (Sa5). If the power supply voltage is not normal (N in Sa5), the determination is repeated until normal. If the power supply voltage is normal (Y in Sa5), the higher address of the interrupt vector is set (Sa6). Then, access to the RAM is permitted (Sa7), and the stack pointer is initialized (Sa8).

  Next, the RAM parity is calculated (Sa10). Then, it is determined whether or not the calculated RAM parity becomes 0 (Sa11). If the RAM parity does not become 0 (N in Sa11), the process proceeds to Sa14.

  When the RAM parity becomes 0 (Y in Sa11), RAM destruction diagnosis fixed data is acquired from the RAM 41c (Sa12). Then, it is determined whether or not the acquired RAM destruction diagnosis fixed data is correct (Sa13). Next, in step Sa14, RAM destruction diagnosis fixed data is cleared (Sa14).

  Next, it is determined whether or not the setting key switch is turned on (Sa15). When the setting key switch is on (Y in Sa15), the main control unit 41 sets a timer interrupt (Sa22). Specifically, a register of a timer circuit built in the main control unit 41 is set so that a timer interrupt is periodically generated every predetermined time. For example, a value corresponding to 0.56 ms is set in a predetermined register (time constant register). In this embodiment, it is assumed that a timer interrupt is periodically taken every 0.56 ms. In the timer circuit, the timer is initialized by setting the register, and time measurement is started from the initial value. Then, when the timer interrupt setting is completed, the process proceeds to a setting change process shown in FIGS.

  On the other hand, if the setting key switch is OFF (Y in Sa15), whether or not the stored content of the RAM 41c has been destroyed based on the determination of Sa11, the determination of Sa13, and whether or not a RAM abnormality flag described later is set. That is, it is determined whether or not the stored contents of the RAM 41c are normal (Sa16). When the stored contents of the RAM 41c are not destroyed (N in Sa16), a power failure recovery command (power failure recovery commands 1 to 4) is transmitted to the sub-control unit 91 (Sa17), and the hot start command is sub-controlled. It transmits to the part 91 (Sa18). The case where the storage contents of the RAM 41c are not destroyed is a case where it is determined that the fixed data for RAM destruction diagnosis is correct in Sa11 and Y and the RAM abnormality flag is not set.

  Then, all the registers are restored (Sa19), and the timer interrupt setting similar to Sa22 is performed (Sa20). And it returns to the process of Sk26 of the timer interruption process (main) shown in FIG.

  If the stored contents of the RAM 41c are destroyed (Y in Sa16), the RAM start address to be initialized is set in the register (Sa23), and the RAM area indicated by the designated address is cleared (hereinafter, “ (Also referred to as “initialization”) (Sa24). The case where the stored contents of the RAM 41c are destroyed is either the case where it is determined that the fixed data for RAM destruction diagnosis is not correct in N or Sa13 in Sa11, or the case where the RAM abnormality flag is set. .

  Here, the storage area of the RAM 41c is divided into a set value work, a special work, an important work, a general work, an unused area, and a stack area.

  The set value work (0000H to in this embodiment) is an area in which data such as set values and random number values that are inconvenient when initialized at the time of normal setting change is stored.

  The special work (0003H in this embodiment) stores data that is initialized only before the start of setting change, such as input / output data of the I / O port 41d and data for transmitting a command to the effect control board 90. It is an area to be done.

  An important work (0014H in this embodiment) is an area in which a counter indicating the number of credits, display data of various indicators and LEDs, a time counter of game time, and data that is inconvenient when initialized at the end of the game are stored. is there.

  General work (0045H in this embodiment) is data necessary for one game (one game) such as a winning flag that does not carry over, a stop control table, a stop symbol, the number of medals to be paid out, and the game is over It is an area where data that can sometimes be initialized is stored.

  The unused area (0173H˜ in this embodiment) is an unused area in the storage area of the RAM 41c.

  The stack area (01CCH˜ in this embodiment) is an area in which data saved from the register of the main control unit 41 is stored.

  When an address is specified in Sa23, all the above-described areas in the storage area of the RAM 41c are initialized. Next, a RAM abnormality flag indicating that the storage contents of the RAM 41c are not normal is set in the RAM 41c (Sa25), and the process proceeds to error processing. In error processing, it becomes an error state and it becomes impossible to play a game. The error state can be canceled by turning on the setting key switch 37 and turning on the power switch 39, thereby determining Y in Sa15 and shifting to the setting change process (see FIGS. 35 and 36). . Therefore, when the power switch 39 is turned on without turning on the setting key switch 37, Sa15 becomes N, and Sa16 becomes Y, so that an error state occurs again.

  In the present embodiment, initialization is performed by setting the data to “00h”, that is, by clearing the data. However, for example, initialization can be performed by setting the data to “FFh” or inputting a predetermined value for each data.

[Setting change processing]
Next, the setting change process which the main control part 41 performs is demonstrated.

  As shown in FIGS. 35 and 36, the main control unit 41 first sets the start address of the RAM 41c to be initialized in the register (Sb1). The RAM 41c is divided into areas according to the purpose of use by 16-bit memory space addresses. In the process of Sb1, the start address for initialization is set in the register among the memory space addresses. Next, based on the RAM parity calculation in Sa10 in FIG. 33 or the RAM destruction diagnosis fixed data acquired in Sa12 in FIG. 33, it is determined whether or not the contents of the RAM are abnormal (Sb2). If the contents of the RAM are abnormal (Y in Sb2), the process proceeds to Sb3 processing. If the contents of the RAM are not abnormal (N in Sb2), the start address of the initialization target RAM at the start of setting change is set in the register (Sb3).

  Next, the RAM area indicated by the address designated by Sb1 or Sb3 is cleared (Sb4). When the address is set at Sb1, all the above-described areas in the storage area of the RAM 41c are initialized. When an address is specified in Sb2, special work, important work, general work, unused area, and stack area are initialized in the storage area of the RAM 41c. When the processing of Sb4 is completed, a setting change start command to be described later is transmitted to the sub-control unit 91 (Sb5), and the main control unit 41 described with reference to FIGS. 38 and 39 executes at a constant interval (0.56 ms interval). The timer interrupt process (main) interrupt is permitted (Sb6).

  Next, it is determined whether or not the setting / reset switch 38 is on (Sb7). When the setting / reset switch 38 is on (Y in Sb7), the setting value is set in the register (Sb8). If the setting / reset switch 38 is off (N in Sb7), it is determined whether the start switch 7 is on (Sb9).

  If the start switch 7 is not turned on (N in Sb9), the process returns to Sb7. When the start switch 7 is turned on (Y in Sb9), it is determined whether or not the setting key switch is turned off (Sb10). If the setting key switch is not turned off (N in Sb10), the determination is repeated until the setting key switch is turned on. When the setting key switch is OFF (Y in Sb10), the setting value data set in the register is stored in the RAM 41c (Sb11).

  Next, a setting change end command is transmitted to the sub-control unit 91 (Sb12). Then, the initial address of the initialization target RAM at the end of the setting change is set in the register (Sb13), and the process proceeds to the main process in FIG.

[Main processing]
Next, main processing executed by the main control unit 41 will be described. The main process is repeatedly executed for each unit of game. One period of the main process corresponds to one unit of the game.

  As shown in FIG. 37, the main control unit 41 first interrupts a timer interrupt process (main) executed by the main control unit 41 described with reference to FIGS. 38 and 39 at a constant interval (0.56 ms interval). Is prohibited (Sc1). Next, the final address of the initialization target RAM is set (Sc2).

  Next, the RAM area indicated by the designated address is cleared (Sc3). At this time, when the main process is started after the setting change process, the addresses from Sb13 to Sc2 in FIG. 36 are initialized. Thereby, the important work and the general work are initialized in the storage area of the RAM 41c. Also, at the end of one unit of game, the address specified in Sc9 to the address specified in Sc2 are initialized. As a result, the general work in the storage area of the RAM 41c is initialized. Then, the main control unit 41 described in FIG. 38 and FIG. 39 permits the interruption of the timer interruption process (main) executed at a constant interval (0.56 ms interval) (Sc4).

  Next, a game start waiting process is executed (Sc5). In the game start waiting process, the process waits in a state where a bet number can be set, and a process for starting a game is executed when a specified number of bets are set according to the game state and the start switch 7 is operated.

  Next, an internal lottery process is executed (Sc6). In the internal lottery process, whether or not to win the above-mentioned winning combination based on the internal lottery random value latched simultaneously with the start of the game by the detection of the start switch 7 in the step of Sc5 (that is, the display result is derived). The process of determining whether or not to allow) is performed. In this internal lottery process, a winning flag is set in the RAM 41c based on the respective lottery results. When a special combination (BB or RB) is won by internal lottery, a special combination carry-over flag is set. Then, as described above, the presence / absence of the special role carry-over flag is determined to determine whether or not the special role has been carried over. A determination process is performed for the (excluded).

  Next, a reel control process is executed (Sc7). In the reel control process, the process of rotating the reels 2L, 2C, 2R in response to the operation of the start switch 7, the result of the internal lottery in the step of Sd2, and the operation of the stop switches 8L, 8C, 8R by the player are detected. In response to this, processing for stopping the rotation of the corresponding reels 2L, 2C, 2R is executed.

  Next, a game end time setting process is executed (Sc8). In the game end setting process, when it is determined that the rotation of all the reels 2L, 2C, and 2R is stopped in the process of Sc7, a winning occurs according to the display result derived for each reel 2L, 2C, and 2R. The process which determines whether or not is executed. If the special combination wins, the special combination carry-over flag is cleared in this process. When it is determined that a winning has occurred, processing such as credit addition and medal payout is performed based on the number of payouts according to the winning. When a winning occurs, a process for setting a gaming state for the next game is executed after the medal payout is completed. Further, when no winning occurs, after the reels are stopped, processing for setting a gaming state for the next game is executed.

  When the game end time setting process ends, the head address of the initial target RAM at the end of each game is set, and the process returns to Sc1. When returning to Sc1, the initialization target RAM final address is set in the register in Sc2, and the RAM in the area designated in Sc3 is cleared. Thereby, RAM is cleared for every game.

  In the main process, a command is generated according to the game progress control, set in the command buffer, and transmitted to the sub-control unit 91.

[Timer interrupt processing (main)]
38 and 39 are flowcharts showing the control contents of the timer interrupt process (main) executed by the main control unit 41 by interrupting and executing the initial setting process and the game process at regular intervals (0.56 ms interval). The timer interrupt process (main) is a process executed by an interrupt (also referred to as a timer interrupt) generated according to a counter timer (CTC) described later. The stored address is set as a value corresponding to the timer interrupt (CTC0) of the interrupt processing vector table. When a timer interrupt occurs, processing from the address is executed. The timer interrupt processing (main) interval (0.56 ms) is set by setting 0.56 ms as an arbitrary value for the CTC timer value. Other interrupts are automatically prohibited during the execution of the timer interrupt process (main).

  As shown in FIGS. 38 and 39, in the timer interrupt process (main), first, the register in use is saved in the stack area (Sk1).

  Next, a power failure determination process is performed (Sk2). In the power failure determination process, it is determined whether or not a voltage drop signal is input from the power failure detection circuit 48. If a voltage drop signal is input, whether or not the voltage drop signal is input in the previous power failure determination process as well. If a voltage drop signal has been input in the previous power failure determination process, it is determined that a power failure has occurred, and a power interruption flag indicating that is set.

  After the power failure determination process in the step of Sk2, it is determined whether or not the power interruption flag is set (Sk3). If the power interruption flag is not set, the process proceeds to Sk4 and the power interruption flag is set In this case, the process proceeds to a power interruption process (main).

  In step Sk4, port input processing for inputting detection data of various switches from the input port is performed.

  Next, the branch counter for identifying the timer interrupt to be executed in the timer interrupt process (main) is advanced by 1 from the four types of timer interrupts 1 to 4 (Sk5). In this embodiment, the timer interrupt 1 is a branch process during a timer interrupt that controls the motor to control the start of the reel. Specifically, the processes from Sk9 to Sk11, such as a reel start process described later. Is done. Timer interrupt 2 is branch processing during timer interrupt that performs LED display control, time counter update, door open / close status monitoring, control signal output control, command and external output signal update, etc. Specifically, the processes of Sk12 to Sk17 such as the LED dynamic display process described later are performed. The timer interrupt 3 is a branching process during timer interrupt that detects the origin passage of the reel, monitors the switch input, and reads out the random number value. Processing of Sk20 to Sk22 such as time processing is performed. The timer interrupt 4 is a branching process during a timer interrupt that detects the input of a stop switch and performs reel stop control. Specifically, the processes of Sk23 to Sk25, such as a stop switch process described later. Is done. In the step of Sk5, 1 is added when the branch counter value is 0 to 2, and is updated to 0 when the counter value is 3. That is, the branch counter value loops in the order of 0 → 1 → 2 → 3 → 0... Each time the timer interrupt process (main) is executed.

  Next, the branch counter value is referenced to determine whether it is 2 or 3, that is, timer interrupt 3 or timer interrupt 4 (Sk6). If it is not timer interrupt 3 or timer interrupt 4, that is, timer interrupt In the case of 1 or timer interrupt 2, it is checked whether the reel motors 32L, 32C, 32R are started or whether they are rotating at a constant speed, and whether the reel motors 32L, 32C, 32R are started or are rotating at a constant speed. For example, the motor phase signal output process for outputting the phase signal data changed in the motor step process of Sk10 described later and the phase signal data changed in the final stop process of Sk24 described later is executed (Sk7).

  Next, referring to the counter value for branching, it is determined whether it is 1 or not, that is, timer interrupt 2 (Sk8). Reel start processing (Sk9) for controlling the step time interval when starting 32L, 32C, 32R, motor step processing (Sk10) for changing phase signal data of the reel motors 32L, 32C, 32R, reel motors 32L, 32C After the stop of 32R, motor phase signal standby processing (Sk11) for changing the phase signal to one-phase excitation after a predetermined time has been sequentially executed, and then the process proceeds to step Sk25.

  In the case of timer interrupt 2 in the step of Sk8, LED dynamic display processing (Sk12) for dynamically lighting various indicators, and output processing of control signals and the like for outputting data such as lighting signals of various LEDs to the output port (Sk13), a time counter update process (Sk14) for updating various time counters, a door monitoring process (Sk15) for monitoring the detection state of the door open detection switch 25, a door command transmission request, etc., set in the command buffer A command transmission process (Sk16) for transmitting various commands such as a setting change command, a return command, and an error command to the sub-control unit 91 and an external output signal update process (Sk17) for updating the external output signal are sequentially executed, and then Sk25. Go to step.

  If it is timer interrupt 3 or timer interrupt 4 in the step of Sk6, it is further determined by referring to the counter value for branching whether it is 3, that is, timer interrupt 4 (Sk18). If it is not interrupt 4, that is, if it is timer interrupt 3, the passing of the origin of the rotating reels 2L, 2C, 2R (pass of the reel reference position) is checked, and the occurrence of a reel rotation error is detected and stopped. Check if the preparation is complete (whether the stop preparation completion code is set). If the stop preparation is complete and the motor is rotating at a constant speed, operate the stop switch corresponding to the rotating reel. Whether or not there has been a change in the detection state of switches such as pass-through origin processing (Sk20) to be validated, MAXBET switch 6, start switch 7, stop switches 8L, 8C, 8R First, switch input determination processing (Sk21) for making a transmission request for an operation detection command, etc., and random number reading processing (Sk22) for reading numerical data from the random value register R1D and storing it in the random value storage work are sequentially executed. Go to step.

  If the timer interrupt is 4 in the step of Sk18, the stop stored in the work on the stop reel is stored when the stop operation position is stored in the work on the stop reel in accordance with the detection of the stop switches 8L, 8C, 8R. The stop position is determined from the operation position, the stop switch process (Sk23) for calculating the number of steps after which the stop should be performed, and the number of steps until the stop calculated in the stop switch process is counted. A stop process (Sk24) for starting braking by two-phase excitation and a final stop process (Sk25) for three-phase excitation after a certain time from the start of braking in the stop process are sequentially executed, and then the process proceeds to step Sk26.

  In the step of Sk26, the register saved in the stack area in Sk1 is restored, the prohibited interrupt is permitted, and the process returns to the process before the interrupt.

[Power interruption (main)]
FIG. 40 is a flowchart showing the control content of the power interruption process (main) executed when the main control unit 41 determines that the power interruption flag is set in the timer interrupt process (main) described above.

  In the power interruption process (main), first, all registers that may be in use are saved in the stack area (Sm1). Although the values of the I register and IY register described above are used, they are not saved here because the same fixed value is always set with the initialization at the time of startup.

  Next, fixed data for destructive diagnosis (in this embodiment, 5A (H)) is set (Sm2). Then, the main control unit 41 described in FIG. 38 and FIG. 39 prohibits the interruption of the timer interrupt process (main) executed at a constant interval (0.56 ms interval), and initializes all output ports ( Sm3). Next, RAM parity adjustment data is calculated and set so that the exclusive OR of all storage areas (including unused areas and unused stack areas) of the RAM 41c becomes 0 (Sm4), and access to the RAM 41c is performed. Prohibited (Sm5).

  Thereafter, the voltage decreases, and the CPU 41a of the main control unit 41 stops and shifts to a standby state. And if a voltage falls in this standby state, it will be in an operation stop state internally. Therefore, the main control unit 41 reliably stops operation when power is interrupted.

  In this embodiment, interrupts are disabled before the output port is initialized. However, the sub-control board 90, the external output board 1000, and the output port for outputting data to the reel motor and reel sensor. Interrupt writing may be set before data is written or data is written to the serial communication circuit.

[About microcomputer configuration]
As shown in FIG. 41, the microcomputer used as the main control unit 41 or the sub control unit 91 includes a clock generation circuit 200, a reset controller 201, an interrupt controller 202, a WDT (watchdog timer) 203, a CTC (counter timer). ) 204, arithmetic circuit 205, address decoder 206, CPU 207 used as main CPU 41a and sub CPU 91a, ROM 208 used as ROM 41b and ROM 91b, RAM 209 used as ROM 41c and RAM 91c, M1 counter 210, inspection port 211, random number circuits 508a and 508b Random number circuit 212, general-purpose initial value random number circuit 212, serial communication circuit 214, PWM (pulse width modulation) output circuit 215, interrupt / general-purpose output circuit 2 6, and a random number external latch input circuit 217.

  The microcomputer shown in FIG. 41 includes an individual ID, ROM read restriction, 64-pin SZIP encapsulation, and an inspection port 211 as security functions.

  The CPU 207 operates at a frequency of 10 MHz (minimum instruction execution time: 100 msec).

  The ROM 208 has a capacity of 10,240 bytes, and the RAM 209 has a capacity of 512 bytes.

  In addition, the reset function has four functions of system reset, WDT (watchdog timer) reset, periodic reset, and illegal access reset.

  In addition, as an interrupt function, two functions of an external terminal interrupt (INT / NMI) and a CTC interrupt (CTC0, CTC1, CTC2) are provided.

  Further, 16 chip select terminals are used in the CS mode and 23 chips in the ECS mode. The CTC 204 has 16 bits × 3 channels.

  The random number circuit 212 includes a total of 16 channels of 8 bits fixed length random number × 8 channels, 16 bits fixed length random number × 2 channels, 8 bits variable length random number × 4 channels, and 16 variable length random numbers × 2 channels. Further, the general-purpose initial value random number circuit 212 has one channel.

  The serial communication circuit 214 includes transmission × 3 channels and reception × 1 channel.

  The arithmetic circuit 205 calculates CRC16, checksum, and horizontal parity.

  The PWM output circuit 217 includes four channels. The general purpose external latch input circuit has three inputs.

  Also, four general-purpose input / output terminals are provided on the input side and three on the output side. The address decoder 207 is used for the output of CS0 to CS15.

[Address map of memory space]
Next, an address map of the memory space in the ROM 208 and RAM 209 of the microcomputer shown in FIG. 41 will be described. The memory space is a memory space accessed with a 16-bit address. The memory space is accessed with a memory instruction. 0000h to 7FFFh is a RAM memory space, and 8000h to FFFFh is a ROM memory space.

  The memory space of the RAM 209 is a usable area where the memory space addresses 0000h to 01FFh can be accessed. Memory space addresses 0200h to 0FFFh are unused areas where access is prohibited. Internal registers are allocated to memory space addresses 1000h to 1080h. Memory space addresses 1081h to 7FFFh are unused areas where access is prohibited. ROM is allocated to memory space addresses 8000h to A7FFh. Memory space addresses A800h to FFFFh are unused areas where access is prohibited.

  In the memory space of the ROM 208, programs / data are allocated to addresses 8000h to A6FFh. A ROM comment is assigned to addresses A700h to A7FFh. A vector table is assigned to addresses A780h to A7A7h. Also, HW parameters are assigned to addresses A7A8h to A7FFh.

  As described above, the 512-byte RAM is arranged in 0000h to 01FFh. When a system reset or WDT reset occurs, the RAM protection state is entered. In the RAM protected state, the RAM can be read but not written. To release the RAM protection state, 00h or 80h is set in the RAM protection register (RAMPT).

  The internal function registers are a group of registers for controlling each function installed in the microcomputer of FIG. If 1 is set in the internal function register arrangement (HRGACS) in the system setting (HSYSCNT) of the HW parameter, the I / O space can be arranged.

  A 10,240-byte ROM is arranged in 8000h to A7FFh. In the ROM area, programs / data, ROM comments, vector tables, and HW parameters are arranged.

  The microcomputer executes the program from 8000h after the system reset, WDT reset, periodic reset, and illegal access reset. The program cannot be executed outside this area.

  The ROM comment is an area for setting the title, version, etc. of the program, and arbitrary data can be set. The data set here can be read from the inspection ports (TXD, RXD, STB, DIR).

  The vector table is a table for setting the start address of the subroutine of the CALLV instruction and the start address of the interrupt process. 0000h is set for the unused vector table. If the values set in the vector table are other than 0000h and 8000h to HPRGEND, the microcomputer does not start. HPRGEND is set by the program end address of the HW parameter.

  The HW parameter is a parameter for setting the internal function of the microcomputer by hardware. The setting is described as a constant table. It cannot be written by a program.

[Vector table address map]
Next, an address map of the vector table in the memory space of the ROM 208 will be described.

  In the vector table, memory space addresses A780h to A79Fh are vector tables for CALLV instructions, and memory space addresses A7A0h to A7A7h are vector tables for interrupt processing.

  In the memory space addresses A780h to A781h of the CALLV instruction vector table, (lower) and (upper) values of CALLV0 are set. In the memory space addresses A782h to A783h, (lower) and (upper) values of CALLV1 are set. In the memory space addresses A784h to A785h, (lower) and (upper) values of CALLV2 are set. In the memory space addresses A786h to A787h, (lower) and (upper) values of CALLV3 are set. In the memory space addresses A788h to A789h, (lower) and (upper) values of CALLV4 are set. In the memory space addresses A78Ah to A78Bh, (lower) and (upper) values of CALLV5 are set. In the memory space addresses A78Ch to A78Dh, (lower) and (upper) values of CALLV6 are set. In memory space addresses A78Eh to A78Fh, (lower) and (upper) values of CALLV7 are set. In the memory space addresses A790h to A791h, (lower) and (upper) values of CALLV8 are set. In the memory space addresses A792h to A793h, (lower) and (upper) values of CALLV9 are set. In the memory space addresses A794h to A795h, (lower) and (upper) values of CALLV10 are set. In the memory space addresses A796h to A797h, (lower) and (upper) values of CALLV11 are set. In the memory space addresses A798h to A799h, (lower) and (upper) values of CALLV12 are set. In the memory space addresses A79Ah to A79Bh, (lower) and (upper) values of CALLV13 are set. In the memory space addresses A79Ch to A79Dh, (lower) and (upper) values of CALLV14 are set. In the memory space addresses A79Eh to A79Fh, (lower) and (upper) values of CALLV15 are set.

  INT / NMI (lower) and (upper) values are set in the memory space addresses A7A0h to A7A1h of the interrupt processing vector table. In memory space addresses A7A2h to A7A3h, (lower) and (upper) values of CTC0 are set. In memory space addresses A7A4h to A7A5h, (lower) and (upper) values of CTC1 are set. In memory space addresses A7A6h to A7A7h, (lower) and (upper) values of CTC2 are set.

[HW parameter list]
Next, HW parameters in the memory space of the ROM 208 will be described.

  The memory space address A7A8h is associated with the symbol HCSATRO and is used for CS / PWM setting. The memory space address A7A9h is associated with the symbol HCSATR1 and is used for CS / PWM setting. The memory space address A7AAh is associated with the symbol HCSATR2 and is used for CS / PWM setting. The memory space address A7ABh is associated with the symbol HCSATR3 and is used for CS / PWM setting. The memory space address A7ACh is associated with the symbol HCSATR4 and used for CS / PWM setting. The memory space address A7ADh is associated with the symbol HCSATR5 and is used for CS / PWM setting. The memory space address A7AEh is associated with the symbol HCSATRD and used for CS / PWM setting.

  The memory space address A7AFh is associated with the symbol HPRST and is used for periodic reset setting.

  The memory space address A7B0h is associated with the symbol HRDMD and is used for setting the random number circuit operation mode.

  The memory space address A7B1h is associated with the symbol HSYSCNT and is used for system setting.

  The memory space address A7B2h is associated with the symbol HSYSCNT and is used for setting the reset period / INP terminal.

  The memory space addresses A7B3h to A7B4h are associated with a symbol HRPGEND and are used for setting a program end address.

  The memory space addresses A7B5h to A7B6h are associated with the symbol HRAMSTAT and are used for setting a RAM access prohibited address.

  The memory space addresses A7B7h to A7B8h are associated with the symbol HRAMEND and are used as RAM access prohibited addresses.

  The memory space addresses A7B9h to A7CCh are associated with the symbol HSWSTS and are used for setting the SW status.

  Memory space addresses A7CDh to A7CFh are used for setting a manufacturer code.

  Memory space addresses A7D0h to A7D7h are used for setting a product code.

  Memory space addresses A7D8h to A7FFh are used for setting a security code.

[Reset period / INP pin setting]
Next, the reset period / INP terminal setting in the HW parameter will be described.

  Symbol HPORTEN is associated with bit 7 of memory space address A7B2h. In HPPORTEN, the INP terminal function setting is set. When it is set to 0, it is not used as an interrupt input terminal, and when it is set to 1, it is set to be used as an interrupt input terminal.

  Further, the symbol HPARTMD is associated with bit 6 of the memory space address A7B2h. In HPPORTMD, interrupt input settings and automatic mutual authentication settings are performed. When it is set to 0, it is set to be an INT interrupt input, and when it is set to 1, it is set to be an NMI interrupt input.

  Further, symbol HRTMEN is associated with bit 5 of memory space address A7B2h. In HRTMEN, a reset period extension setting is set. Then, the setting is made so as not to extend when set to 0, but to extend when set to 1. The extension time is fixed time + fluctuation time.

  Further, symbol HRRDEN is associated with bit 4 of memory space address A7B2h. In HRRDEN, the reset period extension setting is set. When bit 0 of A7B2h is set to 0, it always does not fluctuate at 0 msec. When MCLK (system clock) = 20 MHz, when it is set to 1, it is 0 to 1275 msec (5 msec, 256 types). Set to vary. Each time the system is reset, the time is different from the previous time.

  Further, the symbol HRSTM is associated with bits 3 to 0 of the memory space address A7B2h. In HRSTM, a fixed time is set. And in the case of MCLK = 20 MHz, it is set to be 1.0 sec when set to 0h. When set to 1h, it is set to 2.0 sec. Thereafter, the length is increased by 1.0 sec according to the set value, and is set to 30.0 sec at the maximum.

  As described above, whether or not to start interrupt processing when an L level signal is input to the interrupt input / general-purpose input terminal (INP) with the settings of HPPORTEN and HPARTMD, and whether the interrupt request is INT Interrupt or NMI interrupt can be selected.

  In addition, since the input level of the INP terminal can be read from the external signal input / reset factor register (PINSTS) regardless of the setting state of HORTEN, it can also be used as a general-purpose input.

  If HETMEN is set to 0, the reset period is not extended regardless of the settings of HRRDEN and HRSTM.

  When HRTMEN is set to 1, it is possible to extend the period after the system reset period of 400.5 msec (when MCLK = 20 MHz) until the program is started. The extended time is the sum of the fixed time set by HRSTM and the variable time set by HRRDEN.

For example, the system reset time when HRTMEN = 1, HRRDEN = 1, and HRSTM4h is set is as follows.
400.5 msec + 5.0 msec + (0-1275 msec) = 5.4005 sec-6.6755 sec (when MCLK = 20 MHz)

[Program end address]
Next, the program end address in the HW parameter will be described.

  “8000h to A6FFh” in the memory space address is defined as an area for storing “program / data”. However, the capacity of the “program / data” varies depending on the content of control of the gaming machine and is not stored in all of these areas. In this microcomputer, by setting the program end address, the range of the area where “program / data” is stored is set. If an area where “program / data” is not stored is accessed, illegal It can be set to generate an access reset. In addition, although the setting is performed by designating the end address (final address) for the range of the area where “program / data” is stored, the start address (start address) may be designated. Further, a plurality of separated areas may be set.

  Symbol HPRGEND (lower order) is associated with bits 7-0 of memory space address A7B3h, and symbol HPRGEND (upper order) is associated with bits 7-0 of memory space address A7B4h. In HPRGEND, a program end address is set. Then, the final address of the ROM area used in 8000h to A6FFh is set.

  If HPRGEND is set to a value other than 8000h to A6FFh, an error occurs and the microcomputer does not start. The last address is set in HPRGEND. If the entire ROM area is accessible, HPRGEND = A6FFh is set. When an area from address +1 set by HPRGEND to A6FFh is accessed, an illegal access reset occurs.

  For example, if HPRGEND = 8852h is set, an illegal access reset occurs when accessing 8852h.

[RAM access prohibited address]
Next, the RAM access prohibition address in the HW parameter will be described.

  The symbol HRAMSTAT (lower order) is associated with bits 7-0 of the memory space address A7B5h, and the symbol HRAMSTAT (upper order) is associated with bits 7-0 of the memory space address A7B5h. In HRAMSTAT, a RAM access prohibited start address is set. Then, the start address of the RAM area for which access is prohibited is set to 0000h to 01FFh.

  Symbols HRAMEND (lower) are associated with bits 7-0 of memory space address A7B7h, and symbols HRAMEND (upper) are associated with bits 7-0 of memory space address A7B8h. In HRAMEND, a RAM access prohibited end address is set. Then, the final address of the RAM area for which access is prohibited is set to 0000h to 01FFh.

If the values set in HRAMSTAT and HRAMEND do not satisfy the following relationship, the microcomputer does not start as an error state.
0000h ≦ HRAMSTAT ≦ HRAMEND ≦ 01FFh

  Further, the start address of the RAM area for which access is prohibited is set to HRAMSTAT, and the final address of the RAM area for which access is prohibited is set to HRAMEND.

  When accessing the entire RAM area, HRAMSTAT = 0000h and HRAMEND = 0000h are set.

  In addition, when an access prohibited area set by HRAMSTAT and HRAMEND is accessed, an illegal access reset occurs.

  For example, when HRAMSTAT = 00F2h and HRAMEND = 01A7h are set, an illegal access reset occurs when accessing 002Fh to 01A7h. Also, the settings of HRAMSTAT and HRAMEND can be invalidated by setting the RAM protect register (RAMPT).

[SW status]
Next, the SW status in the HW parameter will be described.

  Symbols HSWSTS0 (lower) is associated with bits 7-0 of memory space address A7B9h, and symbols HSWSTS0 (upper) are associated with bits 7-0 of memory space address A7B8h. The same applies to HSWSTS1-9. In HSWSTS0 to 9, settings of SW status 0 to 9 are performed. The address of the RAM monitored by the inspection apparatus is set to 0000h to 01FFh.

  Note that if a value other than 0000h to 01FFh is set in HSWSTS0 to 9, the microcomputer does not start as an error state.

  If the address of the RAM access prohibition area set by the RAM access prohibition address (HRAMSTAT, HRAMEND) of the HW parameter is set in HSWSTS0 to 9, the microcomputer does not start as an error state.

  In addition, addresses to be monitored by the inspection apparatus are set to HSWSTS 0 to 9.

  If the SW status is not used, 0000h is set. However, if 0000h is set in the RAM access prohibited area, the microcomputer does not start as an error state, so it is preferable not to include 0000h in the RAM access prohibited area.

[Conditions for illegal access reset]
Next, conditions for causing an illegal access reset in the microcomputer shown in FIG. 41 will be described. An illegal access reset occurs due to an unauthorized access. When an illegal access reset occurs, only the CPU core is reset and the internal functions are not reset.

  In the CS / PWM setting (symbol name: HCSATR0 to HCSATR5), when the setting content is HCSRW0 = 00; CS function is invalid (the same applies to HCSRW1 to HCSRW23), access to CS0 (C0h in the I / O space) (CS1 to CS1) The same applies to CS23), which is the condition for the illegal access reset.

  In CS / PWM setting (symbol name: HCSATR0 to HCSATR5), when the setting content is HCSRW0 = 01; synchronized with the R0 signal (the same applies to HCSRW1 to HCSRW23), writing to CS0 (C0h in the I / O space) (The same applies to CS1 to CS23) is a condition for generating an illegal access reset.

  In CS / PWM setting (symbol name: HCSATR0 to HCSATR5), when the setting contents are HCSRW0 = 10; synchronized with the W0 signal (the same applies to HCSRW1 to HCSRW23), reading from CS0 (C0h in the I / O space) is performed. (The same applies to CS1 to CS23) is a condition for generating an illegal access reset.

  In CS / PWM setting (symbol name: HSMMOD), when the setting content is HCSMD = 0; CS mode, the access to the ECS area (D0h to D7h in the I / O space) has been illegally reset. It becomes the generation condition of.

  In CS / PWM setting (symbol name: HSMMOD), when the setting content is HCSMD = 1; in the ECS mode, the access condition to CS15 (CFh in the I / O space) is an occurrence condition of the illegal access reset. It becomes.

  Next, in the system setting (symbol name: HSYSCNT), when the setting content is HRGACS = 0; memory space, an I / O access to the internal register is a condition for generating an illegal access reset.

  Next, in the system setting (symbol name: HSYSCNT), when the setting content is HRGACS = 1; I / O space, the occurrence of the illegal access reset is that the memory has been accessed to the internal register.

  Next, in the system setting (symbol name: HSYSCNT), when the setting content is HRGACS = 1; I / O space, the occurrence of the illegal access reset is that the memory has been accessed to the internal register.

  Next, regarding the setting of the program end address (symbol name: HPRGEND), the access condition to the area between the address next to the address set as the program end address and A6FFh is an illegal access reset generation condition. .

  Next, regarding the RAM access prohibition address (symbol name: HRAMSTAT, HRAMEND), an illegal access reset occurs because there is an access to the area between the start address and the final address of the RAM area set as the RAM access prohibition address It becomes a condition.

  Next, regarding the internal function register (symbol name: MKCODE), writing to MKCODE is a condition for generating an illegal access reset.

  Next, regarding the internal function register (symbol name: PRCODE), writing to PRCODE is a condition for generating an illegal access reset.

  Next, regarding the internal function register (symbol name: CPCODE), writing to CPCODE is a condition for generating an illegal access reset.

  Next, there was a write to the area (8000h to A7FFh) set as the ROM area, an access to the ROM comment area (A700h to A77Fh), and the access to the HW parameter area (A7A8h to A77Fh) The occurrence of an illegal access reset is an access condition.

  Next, an access condition to an unused area (200h to FFFh, 10B1h to 7FFFh, A800h to FFFh) in the memory space is a condition for generating an illegal access reset.

  Next, the occurrence condition of the illegal access reset is that the unused area (B1h to BFh) in the I / O space is accessed.

  Next, the occurrence condition of the illegal access reset is that the CPU core fetches the undefined instruction.

[Condition that does not start]
Next, the conditions under which the microcomputer shown in FIG. 41 does not start will be described with reference to FIG. When the condition shown in FIG. 42 is satisfied, the microcomputer is determined not to be in an error state and started up.

  As shown in FIG. 42, in the setting of the vector table (related symbol name: HPRGEND), if values other than 0000h and 8000h to HPRGEND are set, the condition that the microcomputer does not start is satisfied.

  In the CS / PWM setting (related symbol names: HCSMD, HCSRW16 to HCSRW23), the microcomputer does not start when the value set in the CS / PWM setting is HCSMD = 0 and the HCSRW16 is set to a value other than 00. Is satisfied. The same applies to HCSRW17 to HCSRW23.

  In the CS / PWM setting (related symbol names: HCSMD, HCSRW15), if HCSMD = 1 and HSCRW15 is set to a value other than 00, the condition that the microcomputer does not start is satisfied.

  In the CS / PWM setting (related symbol names: HPW0MD to HPW3MD, HCSRW11 to HCSRW14), the condition that the microcomputer does not start is satisfied when HPW0MD = 1 and a value other than 00 is set for HCSRW11. If HPW1MD = 1 and HCSRW12 is set to a value other than 00, the condition that the microcomputer does not start is satisfied. When HPW2MD = 1 and HCSRW13 is set to a value other than 00, the condition that the microcomputer does not start is satisfied. When HPW3MD = 1 and HCSRW 14 is set to a value other than 00, the condition that the microcomputer does not start is satisfied.

  In the CS / PWM setting (related symbol name: HSMMOD), when bit 4 = 1 of HCSMOD is set, the condition that the microcomputer does not start is satisfied. When bit 5 = 1 of HSMMOD is set, the condition that the microcomputer does not start is satisfied. When bit 6 = 1 of HSMMOD is set, the condition that the microcomputer does not start is satisfied.

  In the random number circuit operation mode setting (related symbol name: HRDMD), when bit 3 = 1 of HEDMD is set, the condition that the microcomputer does not start is satisfied.

  In the random number circuit operation mode setting (related symbol name: HFRCLK), the condition that the microcomputer does not start when HFRCLK = 1 is set and no random number external clock (EXCLK) is input is satisfied.

  In the random number circuit operation mode setting (relevant symbol name: HRDMYE), the condition that the microcomputer does not start when HRDMYE = 1 is satisfied.

  In the system setting (related symbol name: HSYSCNT), when bit 5 = 1 of HSYSCNT is set, the condition that the microcomputer does not start is satisfied. When bit 6 = 1 of HSYSCNT is set, the condition that the microcomputer does not start is satisfied. Further, when bit 7 = 1 of HSYSCNT is set, the condition that the microcomputer does not start is satisfied. Note that bits 5 to 7 of HSYSCNT are unused bits that are not used for setting any function, and are normally set to 0.

  In the system setting (related symbol names: HLNKMD, HAUTLK), when HLNKMD = 0 and HAUTLK = 1 are set, the condition that the microcomputer does not start is satisfied.

  In the program end address (related symbol name: HPRGEND), if a value other than 8000h to A6FF is set in HPRGEND, the condition that the microcomputer does not start is satisfied.

  In the RAM access prohibition address (related symbol names: HRAMSTAT, HRAMEND), if 0000h ≦ HRAMSTAT ≦ HRAMEND ≦ 01FFh is not satisfied, the condition that the microcomputer does not start is satisfied.

  In the SW status (related symbol names: HSWSTS0 to HSWSTS9), if HSWSTS0 is set to a value other than 0000h to 01FFh, the condition that the microcomputer does not start is satisfied. The same applies to HSWSTS1 to HSWSTS9.

  In the SW status (related symbol names: HSWSTS0 to HSWSTS9, HRAMSTAT, HRAMEND), the condition that the microcomputer is not started is satisfied when the value of the access prohibition right area set by HRAMSTAT and HRAMEND is set in HSWSTS0. The same applies to HSWSTS1 to HSWSTS9.

[Change in operation due to reset factor]
Next, a change in operation due to a reset factor in the microcomputer shown in FIG. 41 will be described. The operation varies depending on four types of reset factors.

  When the system reset is performed, the system reset period is set. When the reset factor is any of WDT reset, periodic reset, and illegal access reset, the system reset period is not set.

  If the reset period is extended by a system reset, the reset period extension is set when the reset period extension is set to be effective by the HW parameter, and it is set by any of WDT reset, periodic reset, and illegal access reset. If the reset period is not extended, no extension of the reset period is set.

  When any one of system reset, WDT reset, periodic reset, and illegal access reset is performed, the CPU core is initialized.

  Also, the input / output terminals are initialized when a system reset is performed, and the input / output terminals are not initialized when any of WDT reset, periodic reset, and illegal access reset is performed.

  Further, the contents of the RAM do not change even when any one of system reset, WDT reset, periodic reset, and illegal access reset is performed.

  The RAM is set in the protected state when either a system reset or a WDT reset is performed, and the RAM is not set in a protected state when either a periodic reset or illegal access reset is performed.

  The CTC is initialized when either a system reset or WDT reset is performed, and the CTC is not initialized when either a periodic reset or illegal access reset is performed.

  Further, WDT is initialized when a system reset is performed, and WDT is not initialized when any of WDT reset, periodic reset, and illegal access reset is performed.

  In addition, the order of clear values in the WDT cyclic clear mode is initialized when a system reset is performed, and the WDT cyclic clear mode is cleared when any of WDT reset, periodic reset, and illegal access reset is performed. The order of values is not initialized.

  In addition, serial communication is initialized by interrupting transmission / reception when a system reset is performed, and is not initialized when any of WDT reset, periodic reset, and illegal access reset is performed.

  Further, the interrupt controller is initialized when either system reset or WDT reset is performed, and the interrupt controller is not initialized when either periodic reset or illegal access reset is performed.

  In addition, when a system reset is performed, external signal input / reset factors, register reset factors, and bits 5 to 7 of PINSTS are initialized, and any of WDT reset, periodic reset, and illegal access reset is performed. It will not be initialized if

  Further, the random number circuit is initialized when either the system reset or the WDT reset is performed, and the random number circuit is not initialized when either the periodic reset or the illegal access reset is performed.

  In addition, the initial value of the random number is different each time when either system reset or WDT reset is performed, and the initial value of random number is the start before resetting when either periodic reset or illegal access reset is performed. Set to a value.

  Further, the random number error status register is initialized when the system reset is performed, and is not initialized when any of the WDT reset, the periodic reset, and the illegal access reset is performed.

  Further, when the system reset is performed, the general-purpose initial value random number is different every time. When any of the WDT reset, the periodic reset, and the illegal access reset is performed, the general-purpose initial value random number does not change.

  Further, the M1 counter is initialized when either system reset or WDT reset is performed, and the M1 counter is not initialized when either periodic reset or illegal access reset is performed.

  Further, the periodic reset monitor is initialized when either the system reset or the WDT reset is performed, and the periodic reset monitor is not initialized when either the periodic reset or the illegal access reset is performed.

  The arithmetic function is initialized when either a system reset or a WDT reset is performed, and the arithmetic function is not initialized when either a periodic reset or illegal access reset is performed.

  Also, the PWM output is initialized when either system reset or WDT reset is performed, and the PWM output is not initialized when either periodic reset or illegal access reset is performed.

[Internal function register]
Next, the internal function register will be specifically described. In the figure, S indicates “system reset” and W indicates “WDT reset”. Further, R / W (Read / Write) indicates that R / W can read and write, R can only read, and W can only write. In addition, a description will be given with some functions omitted.

  The functions not shown in the figure include a random number maximum value register that determines the maximum value of the random number value to be updated by the random number circuit, an external latch signal permission register that determines the operation when acquiring the random value, an external latch signal mode register, etc. The registers related to the random number circuit are included, and these initialization factors are a system reset and a WDT reset.

  A RAM protect register (RAMPT) is assigned to the I / O space address 00h and the memory space address 1000h. R / W is R / W, and initialization factors are S and W.

  A CTC control register (TMCNT0) is assigned to the I / O space address 01h and the memory space address 1001h. R / W is R / W, and initialization factors are S and W.

  A CTC control register (TMCNT1) is assigned to the I / O space address 02h and the memory space address 1002h. R / W is R / W, and initialization factors are S and W.

  A CTC control register (TMCNT2) is assigned to the I / O space address 03h and the memory space address 1003h. R / W is R / W, and initialization factors are S and W.

  A CTC data register (CTC0) is allocated to the I / O space addresses 04h and 05h and the memory space addresses 1004h and 1005h. R / W is R / W, and initialization factors are S and W.

  A CTC data register (CTC1) is allocated to the I / O space addresses 06h and 07h and the memory space addresses 1006h and 1007h. R / W is R / W, and initialization factors are S and W.

  A CTC data register (CTC2) is allocated to the I / O space addresses 08h and 09h and the memory space addresses 1008h and 1009h. R / W is R / W, and initialization factors are S and W.

  A WDT control register (WDTCNT) is assigned to the I / O space address 0Ah and the memory space address 100Ah. R / W is R / W, and initialization factors are S and W.

  A WDT clear register (WDTCLLR0) is assigned to the I / O space address 0Bh and the memory space address 100Bh. R / W is W. There is no initialization factor.

  A WDT clear register (WDTCLR1) is assigned to the I / O space address 0Ch and the memory space address 100Ch. R / W is W. There is no initialization factor.

  A WDT clear register (WDTCLR2) is assigned to the I / O space address 0Dh and the memory space address 100Dh. R / W is W. There is no initialization factor.

  A WDT clear register (WDTCLR3) is assigned to the I / O space address 0Eh and the memory space address 100Eh. R / W is W. There is no initialization factor.

  An interrupt request register (IRR) is assigned to the I / O space address 23h and the memory space address 1023h. R / W is R / W, and initialization factors are S and W.

  An interrupt permission register (IRR) is assigned to the I / O space address 24h and the memory space address 1024h. R / W is R / W, and initialization factors are S and W.

  An interrupt priority register (IPR) is assigned to the I / O space address 25h and the memory space address 1025h. R / W is R / W, and initialization factors are S and W.

  An external signal input / reset factor register (PINSTS) is assigned to the I / O space address 26h and the memory space address 1026h. R / W is R / W, and the initialization factor is S.

  A periodic reset monitor register (ITRMN) is assigned to the I / O space address 94h and the memory space address 1094h. R / W is R, and initialization factors are S and W.

  An arithmetic data register (CDAT) is assigned to the I / O space address 95h and the memory space address 1095h. R / W is R / W, and initialization factors are S and W.

  A horizontal parity calculation result register (CPTY) is assigned to the I / O space address 96h and the memory space address 1096h. R / W is R / W, and initialization factors are S and W.

  A checksum operation result register (CSUM) is allocated to the I / O space addresses 97h and 98h and the memory space addresses 1097h and 1098h. R / W is R / W, and initialization factors are S and W.

  A CRC16 operation result register (CCRC) is assigned to the I / O space addresses 99h and 9Ah and the memory space addresses 1099h and 109Ah. R / W is R / W, and initialization factors are S and W.

  A PWM control register (PWMC0) is assigned to the I / O space address 9Bh and the memory space address 109Bh. R / W is R / W, and initialization factors are S and W.

  A PWM control register (PWMC1) is assigned to the I / O space address 9Ch and the memory space address 109Ch. R / W is R / W, and initialization factors are S and W.

  A PWM control register (PWMC2) is assigned to the I / O space address 9Dh and the memory space address 109Dh. R / W is R / W, and initialization factors are S and W.

  A PWM control register (PWMC3) is assigned to the I / O space address 9Eh and the memory space address 109Eh. R / W is R / W, and initialization factors are S and W.

  A manufacturer code register (MKCODE) is assigned to the I / O space addresses A2h, A3h, and A4h and the memory space addresses 10A2h, 10A3h, and 10A4h. R / W is R. There is no initialization factor.

  Product code registers (PRCODE) are assigned to the I / O space addresses A5h to ACh and the memory space addresses 10A5h to 10ACh. R / W is R. There is no initialization factor.

  A chip code register (CPCODE) is assigned to the I / O space addresses ADh to B0h and the memory space addresses 10ADh to 10B0h. R / W is R. There is no initialization factor.

[RAM protection]
Next, RAM protection will be described. The RAM protect is a function for preventing the RAM from being rewritten by an incorrect operation.

  The operation of RAM protection is as follows. After a system reset or WDT reset occurs, the RAM is protected. In the RAM protected state, data can be read from the RAM, but data cannot be written to the RAM. When writing data to the RAM, the RAM protection is set to invalid in the RAM protection register (RAMPT). If the RAM access prohibition area setting of the RAMPT is set to invalid, the RAM access prohibition area exists if HRAMSTAT = 0000h and HRAMEND = 0000h are set even if the RAM access prohibition area of the HW parameter is enabled. No illegal access reset occurs.

[RAM protect register]
Next, the RAM protector register in the internal function register will be described.

  In the RAM protect register, the symbol RAMPT is associated with bits 7 to 0 of the memory space address 1000h (I / O space address 00h). In RAMPT, RAM protection is set and RAM access prohibited area is controlled. At 00h, the RAM access prohibition area is set to invalid, and RAM protection is set to invalid. In 01h, the RAM access prohibited area is set to be invalid, and the RAM protect is set to be valid. In 80h, the RAM access prohibition area is set to be valid, and the RAM protect is set to be invalid. In 81h, the RAM access prohibition area is set valid, and the RAM protect is set valid. Other than these values, the state is retained. Note that R / W is R / W, and the initial value is 81h.

[Counter timer (CTC)]
Next, CTC will be described. The microcomputer shown in FIG. 41 has 3 channels of 16-bit CTC.

  The operation of CTC is as follows. The CTC counts down the set timer value, and outputs an interrupt request signal to the interrupt controller when it reaches 0000h. 0000h at this time is referred to as a terminal count. Since each CTC channel (CTC0-2) can be operated independently, an interrupt can be generated at three different time intervals.

  Since CTC0 and CTC1 can use the terminal count of CTC2 as a clock source, a long time interval can be easily created. For example, when the terminal count of CTC2 is set to the clock source of CTC0, the timer value of CTC2 is set to 2 msec, and CTC0 is set to 65,000 count, 2 msec × 65,000 = 130 sec can be counted. The CTC is initialized when a system reset or a WDT reset occurs.

The operation mode of CTC is as follows. The CTC has two operation modes: a one-shot timer mode that operates only once and an interval timer mode that operates repeatedly. In the one-shot timer mode, down-counting starts from the set timer value and stops when the terminal count is reached. An interrupt request is generated once when the terminal count is reached.
When the timer value is set to 5: 5 → 4 → 3 → 2 → 1 → 0 (stop)

In the interval timer mode, the countdown is performed from the set timer value, and when the terminal count is reached, the countdown is performed again from the set timer value. Each time the terminal count is reached, an interrupt request is repeatedly generated.
When the timer value is set to 5: 5 → 4 → 3 → 2 → 1 → 5 → 4 → ・ ・ ・ (repeated)

  Regarding the setting of the timer value, an arbitrary value or four types of fixed values (1 msec, 2 msec, 4 msec, and 1.4890 msec) can be set as the CTC timer value.

As an arbitrary value setting method, a timer value is set in the CTC data registers (CTC0 to CTC2), a timer value setting method, an operation mode, a clock frequency division, and a clock source in the CTC control registers (TMCNT0 to TMCNT2) are set.
Setting example for generating an interrupt every 3 msec in CTC0 1. CTC0 = 012 Ch Timer value = 300
2. TMCNT = 02h Timer value setting method = arbitrary value, operation mode = interval timer mode, clock division = 10 μsec, clock source = MLCK division

The fixed value setting method sets the timer value setting method, operation mode, and fixed value of the CTC control registers (TMCNT0 to TMCNT2).
Setting example for generating an interrupt every 4 msec in CTC0 1. TMCNT = 0Bh Timer value setting method = fixed value, operation mode = interval timer mode, fixed value setting = 4 msec
Setting of CTC0 (CTC0 data register) is unnecessary.

In CTC activation, the CTC count operation is stopped after the system reset and the WDT reset.
The activation of CTC is set in the following order.
1. A timer value is set in the CTC data registers (CTC0 to CTC2).
2. Set the CTC control registers (TMCNT0 to TMCNT2).
When setting a fixed value to the timer value setting method, The CTC data registers (CTC0 to CTC2) need not be set. Just set TMCNT0-2 to start. Even if CTC is counting, if TMCNT0-2 is set, it is updated with the setting contents of CTC0-2 and TMCNT0-2. The timer value being counted is counted down again from the set value of CTC0-2.

[CTC control register]
Next, the CTC control register in the internal function register will be described.

  In the CTC control register, bit 7 of the memory space address 1001h (I / O space address 01h) is not used and is always 0. Note that R / W is R and the initial value is 0.

  Symbol C0CKCEL is associated with bit 6 of memory space address 1001h (I / O space address 01h), and symbol C1CKCEL is associated with bit 6 of memory space address 1002h (I / O space address 02h). In C0CKCEL and C1CKCEL, the clock sources CTC0 to CTC1 are set. Then, 0 is set to the frequency division of MCLK, and 1 is set to the terminal count of CTC2. Note that R / W is R / W, and the initial value is 0.

  When C0CKCEL is set to 0, CTC0 is counted down with the clock set to C0CKCEL. When C0CKCEL is set to 1, CTC0 is counted down with the terminal count of CTC2. When C1CKCEL is set to 0, CTC1 is counted down with the clock set to C1CKCEL. When C1CKCEL is set to 1, CTC1 is counted down with the terminal count of CTC2.

  Symbols C0CLK are associated with bits 4-5 of memory space address 1001h (I / O space address 01h), and symbols C1CLK are associated with bits 5-4 of memory space address 1002h (I / O space address 02h). The symbols C2CLK are associated with bits 4 to 5 of the memory space address 1003h (I / O space address 03h). In C0CLK, C1CLK, and C2CLK, clock division setting of CTC0 to CTC2 is performed. When MLCK = 20 MHz, 00 is set to 10 μsec, 01 is set to 1 μsec, 10 is set to 5 μsec, and 11 is set to 20 μsec. Note that R / W is R / W, and the initial value is 0.

  CTC2 counts down with the clock set to C2CLK.

  Symbols TMCEL0 are associated with bits 3 to 2 of memory space address 1001h (I / O space address 01h), and symbols TMCEL1 are associated with bits 2 to 3 of memory space address 1002h (I / O space address 02h). Thus, the symbol TMCEL2 is associated with bits 2 to 3 of the memory space address 1003h (I / O space address 03h). In TMCEL0, TMCEL1, and TMCEL2, the fixed values of CTC0 to CTC2 are set. Then, 00 is set to 1 msec (timer value = 03E8h), 01 is set to 2 msec (timer value = 07D0h), 10 is set to 4 msec (timer value = 0FA0h), and 11 is set to 1.490 msec (timer value = 05D1h). Note that R / W is R / W, and the initial value is 0.

  The set time of TMCEL0 to 2 is a predetermined time when the MCLK frequency setting (HSYSCLK) of the system setting (HSYSCNT) of the HW parameter is set to the same frequency as the system clock (MCLK).

  Symbol TMMOD0 is associated with bit 1 of memory space address 1001h (I / O space address 01h), and symbol TMMOD1 is associated with bit 1 of memory space address 1002h (I / O space address 02h). Symbol TMMOD2 is associated with bit 1 of address 1003h (I / O space address 03h). In TMMOD0, TMMOD1, and TMMOD2, the operation modes of CTC0 to CTC2 are set. At 0, the one-shot timer mode is set, and at 1, the interval timer mode is set. Note that R / W is R / W, and the initial value is 0.

  Bit 0 of memory space address 1001h (I / O space address 01h) is associated with symbol TMFVM0, and bit 0 of memory space address 1002h (I / O space address 02h) is associated with symbol TMFVM1 and memory space. Bit 1 of address 1003h (I / O space address 03h) is associated with symbol TMFVM2. In TMFVM0, TMFVM1, and TMFVM2, the timer value setting method of CTC0 to CTC2 is set. Then, 0 is set to an arbitrary value, and 1 is set to a fixed value. Note that R / W is R / W, and the initial value is 0.

  When 0 is set in TMFVM0-2, the settings of TMCEL0-2 are invalid. When 1 is set in TMFVM0 to 2, settings of C0CKSEL, C1CKSEL, C0CLK, C1CLK, and C2CLK are invalid. At this time, the timer value of CTC0-2 is set to any one of 03E8h, 07D0h, 0FA0h, 05D1h and the clock frequency is 1 μsec depending on the setting value of TMSEL0-2. Note that the set values of the C0CLK, C1CLK, C2CLK, and CTC data registers (CTC0 to CTC2) are not affected.

[CTC data register]
Next, the CTC control register in the internal function register will be described.

  In the CTC control register, symbols 7 to 0 of the memory space address 1004h (I / O space address 04h) are associated with the symbol CTC0 (lower order), and bits 7 to 5 of the memory space address 1005h (I / O space address 05h). 0 is associated with the symbol CTC0 (upper order). In CTC0, the timer value of CTC0 is set. When reading, the count value is read. In the case of writing, the value written to 65,536, 0001h to 1 in 0000h, and 1 to 1 thereafter increases, and 65,535 is written to FFFFh. Note that R / W is R / W, and the initial value is FFFFh.

  Symbols CTC1 (lower order) are associated with bits 7-0 of memory space address 1006h (I / O space address 06h), and symbols CTC1 are assigned to bits 7-0 of memory space address 1007h (I / O space address 07h). (Upper) is associated. In CTC1, the timer value of CTC1 is set. In addition, CTC1 is the same as CTC0.

  Symbols CTC2 (lower order) are associated with bits 7-0 of memory space address 1008h (I / O space address 08h), and symbols CTC2 are assigned to bits 7-0 of memory space address 1009h (I / O space address 09h). (Upper) is associated. In CTC2, the timer value of CTC2 is set. In addition, CTC2 is the same as CTC0.

  As described above, the timer values CTC0 to CTC2 are set in the CTC data register. When 0000h is set, 65,536 is set. When 1 (fixed value) is set in TMFVM0 to 2 of the CTC control registers (TMCNT0 to 2), this register is unnecessary.

  Further, the count values of CTC0 to CTC2 can be read from this register. Even when 1 (fixed value) is set in TMFVM0 to 2 in the CTC control registers (TMCNT0 to 2), the count value can be read. The count value is read after the CTC is activated.

  When the count value is read using a 2-byte read command, the count value being updated is not read. When the high-order and low-order are read separately by a 1-byte read command, the count value may be updated halfway.

[Watchdog timer (WDT)]
The watchdog timer (WDT) can quickly detect an abnormal operation of the program due to noise or the like, and can return to a normal state by generating a WDT reset.

  WDT operates as follows. The WDT can set the time from 0.1 sec to 12.7 sec (when MCLK = 20 MHz) in units of 0.1 μsec by the WDT control register (WDTCNT). If the WDT is not cleared within the set time, a WDT reset occurs and the CPU core and internal functions are reset. If the WDT is not cleared again within the time set from the time when the WDT is cleared, a WDT reset will occur, so it is necessary to continue to clear the WDT.

  If a WDT reset occurs, the cause can be confirmed by an external signal input / reset factor register (PINSTS). WDT is initialized when a system reset occurs.

  WDT is activated when the same value is set twice in succession in the WDT control register (WDTCNT). Once activated, it cannot be stopped and the set value of WDTCNT cannot be changed.

  There are simple clear mode and circular clear mode for clearing WDT. In the simple clear mode, WDT is cleared by setting 18h in the WDT clear register (WDTCLLR0) in addition to the set time. Thereafter, 18h is repeated in WTCTCLR0 other than the set time. In the cyclic clear mode, the WDT is cleared by setting 60h in the WDT clear register (WDTCLR1) within the first set time. Within the next set time, the WDT clear register (WDTCLR2) is set to 03h to clear the WDT, and within the next set time, the WDT clear register (WDTCLR3) is set to 24h to clear the WDT. Thereafter, this order setting is repeated. If a different order or a different value is set, the WDT is not cleared and does not affect the operation of the WDT.

[WDT control register]
Next, the CTC control register in the internal function register will be described.

  In the WDT control register, the symbol WDTND is associated with bit 7 of the memory space address 100Ah (I / O space address 0Ah). In WDTND, the clear mode is set. At 0, the simple clear mode is set, and at 1, the circular clear mode is set. Note that R / W is R / W, and the initial value is 0.

  Symbols WDT are associated with bits 6 to 0 of memory space address 100Ah (I / O space address 0Ah). In WDT, timer setting is performed. When MCLK = 20 MHz, WDT can be stopped at 00h, 0.1 μsec can be set as the minimum value at 01h, and 12.7 sec can be set as the maximum value at 7Fh. Note that R / W is R / W, and the initial value is 0.

  When WDTCNT is set, the same value is set twice within 15 μsec (when MCLK = 20 MHz). WDTCNT cannot be changed once set. If 00h is set twice continuously in WDTCNT, WDT will not start. Even if 00h is continuously set twice after starting WDT, WDT cannot be stopped.

[WDT clear register]
Next, the WDT clear register in the internal function register will be described.

  In the WDT clear register, the symbol WDTCL0 is associated with bits 7 to 0 of the memory space address 1008h (I / O space address 08h). In WDTCL0, simple clear mode WDT clear is set. And it is set to 18h. R / W is W.

  The symbol WDTCLR1 is associated with bits 7 to 0 of the memory space address 1009h (I / O space address 09h). In WDTCLR1, setting of WDT clear in the circulation clear mode is performed. And it is set to 60h. R / W is W.

  Symbols WTCLR2 are associated with bits 7 to 0 of the memory space address 100Dh (I / O space address 0Dh). In WDTCLR2, the WDT clear setting in the circulation clear mode is performed. And it is set to 03h. R / W is W.

  Symbols WTCLR2 are associated with bits 7 to 0 of the memory space address 100Eh (I / O space address 0Eh). In WDTCLR3, setting of WDT clear in the circulation clear mode is performed. And it is set to 24h. R / W is W.

  The order of WDT clear (60h → 03h → 24h) in the circulation clear mode is maintained when a WDT reset occurs. It is initialized when a system reset occurs.

[Interrupt controller]
Next, the interrupt controller will be described.

  As an interrupt operation, first, an interrupt factor and an interrupt are set.

Interrupt factors include the input signal of the interrupt input / general-purpose input terminal (INP) and the terminal count of CTC0 to 2. Interrupts are generated in the following cases.
1. 1. When INP terminal becomes L level 2. When CTC0 reaches the terminal count 3. When CTC1 reaches the terminal count When CTC2 reaches the terminal count

  When the INP terminal is used as an interrupt input signal, 1 (used as an interrupt input terminal) is set in the HW parameter reset period / INP terminal function setting (HPORTTEN) of the INP terminal setting (HRSTCNT).

  The INP terminal can select INT interrupt input or NMI interrupt input by setting the interrupt input terminal (HPORTMD) of HRSTCNT.

  The four interrupt factors can be individually set to enable or disable interrupts by an interrupt enable register (IER). Also, the interrupt priority can be set by the interrupt priority register (IPR).

  Interrupts other than NMI are allowed to accept and forbid interrupt requests independently of the interrupt controller by the interrupt master permission flag (IMF) assigned to the program status word (PSW) of the CPU core. Can be set.

  The IMF is set by an EI (IMF = 1) command and DI (IMF = 0).

  When the CPU core is in the interrupt permission state (IMF = 1), the interrupt controller outputs an interrupt request signal to the CPU core.

  In the case of an NMI interrupt, an interrupt request signal is output to the CPU core regardless of the interrupt enabled / disabled state.

  The interrupt request register (IRR), the interrupt permission register (IER), and the interrupt priority register (IPR) are initialized when a system reset or a WDT reset occurs.

The interrupt process is started in the next step.
1. When an interrupt occurs, the interrupt factor is latched in the interrupt request register (IRR).
2. An interrupt request signal is output to the CPU core according to the setting state of IER, IPR, and IMF.
3. The CPU core determines whether or not there is an interrupt request during the M1 cycle.
4). When there is an interrupt request, the instruction fetched in the M1 cycle is discarded and the program counter (PC) is not updated. Since this PC is pushed onto the stack at “8.” below, the execution of the program is resumed from this PC at the end of the interrupt process. While the LDIR and CPIR instructions are being executed, there are M1 cycles each time the process is repeated. In this case as well, whether or not there is an interrupt request is determined.
5. M1 and IPEQ0 are simultaneously set to L level, indicating that the CPU core has accepted the interrupt.
6). Clear the bit corresponding to the interrupt factor of IRR to 0.
7). The start address of the interrupt process corresponding to the interrupt factor is read from the interrupt process vector table.
8). Push PSW, PC upper byte (PCH), PC lower byte (PCL) in this order.
9. Clear IMF to 0 and disable interrupts.
10. The address read from the interrupt processing vector table is set in the PC counter.
11. Start interrupt processing.
The above processing is for the case where the interrupt request is an INT interrupt and CTC 0 to 2 interrupts. In the case of an NMI interrupt, an interrupt request signal is output regardless of the settings of IER, IPR, and IMF.

  PSW and PC are automatically saved to the stack during interrupt acceptance processing, but general-purpose registers (W, A, B, C, D, E, H, L, IX, IY) of the CPU core are automatically saved. Not. Evacuate by program if necessary.

  Note that. General-purpose registers can be saved by a PUSH instruction or by switching the general-purpose register banks. For example, in the case of a system in which interrupt processing does not start multiple times, the normal processing uses bank 0 of the general-purpose register, executes the LD, RBS, 1 (RBS = 1) instruction at the top of the interrupt processing, By switching to 1, the bank 0 register can be saved.

  Since the register bank selector (RBS) is included in the PSW, when the interrupt processing return instruction (RETI or RETN) is executed, the PSW returns from the stack and automatically switches to the bank 0.

  The end of the interrupt process does not require any special measures other than the execution of the return instruction (RETI or RETN). When the return instruction is executed, PSW and PC are returned from the stack, and the process returns to the process before starting the interrupt process. The interrupt controller clears the interrupt factor automatically when an interrupt request is received. Since IMF and RBS are included in PSW, they are automatically returned from the stack by a return instruction. Therefore, there is no need to execute an EI command or RBS switching before the end of the interrupt process.

  Since an interrupt can be accepted as soon as the EI instruction is executed, if an EI instruction and a return instruction are described consecutively, a new interrupt may be accepted when the return instruction is fetched.

An example of an interrupt process procedure when executing an interrupt process with CTC0 is shown. The details are as follows.
1. In the main routine, bank 0 (RBS = 0) of general-purpose registers is used.
2. The CTC0 interrupt routine uses bank 1 (RBS = 1) of general purpose registers.
3. The end of the interrupt process is only the execution of RETI.

[Interrupt request register]
Next, the interrupt request register in the internal function register will be described. The interrupt request register is a register that latches an interrupt request signal.

  In the interrupt request register, the symbol IRR3 is associated with bit 7 of the memory space address 1023h (I / O space address 23h). In IRR3, a CTC2 interrupt request is set. In the case of reading, the interrupt request is set without 0 when it is 0, and the interrupt request is set when 1. In the case of writing, when it is 0, it is set to clear, and when it is 1, it is set to do nothing. Note that R / W is R / W, and the initial value is 0.

  Bit 6 of memory space address 1023h (I / O space address 23h) is associated with symbol IPR2. In IRR2, a CTC1 interrupt request is set. In other respects, IRR2 is similar to IRR3.

  Bit 5 of memory space address 1023h (I / O space address 23h) is associated with symbol IPR1. In IRR1, a CTC0 interrupt request is set. In other respects, IRR1 is similar to IRR3.

  Bit 4 of memory space address 1023h (I / O space address 23h) is associated with symbol IPR0. In IRR0, an INT / NMI interrupt request is set. In addition, IRR0 is the same as IRR3.

  Bits 3 to 30 of the memory space address 1023h (I / O space address 23h) are unused and are always 0. Note that R / W is R and the initial value is 0.

  When the CPU core accepts an interrupt request, the interrupt controller automatically clears to zero. If 0 is set, it can be cleared, but even if 1 is set, an interrupt request cannot be set.

  Since the IRR is located in the preceding stage of the interrupt permission register (IER), even if the interrupt factor is set to disable interrupt by the IER, it is latched. When ignoring an interrupt request that occurs while interrupts are prohibited, set the IRR to 0 before clearing the interrupts to clear the interrupt request.

[Interrupt enable register]
Next, the interrupt permission register in the internal function register will be described. The interrupt permission register is a register that permits an interrupt request signal.

  In the interrupt permission register, the symbol IER3 is associated with bit 7 of the memory space address 1024h (I / O space address 24h). In IER3, CTC2 interrupt permission is set. When it is 0, it is set to disable interrupts, and when it is 1, it is set to enable interrupts. Note that R / W is R / W, and the initial value is 0.

  Bit 6 of memory space address 1024h (I / O space address 24h) is associated with symbol IER2. In IER2, CTC1 interrupt permission is set. Otherwise, IER2 is the same as IER3.

  Bit 5 of memory space address 1024h (I / O space address 24h) is associated with symbol IER1. In IER1, CTC0 interrupt permission is set. In addition, IER1 is the same as IER3.

  Symbol 4 is associated with bit 4 of memory space address 1024h (I / O space address 24h). In IER0, setting of INT interrupt permission is performed. Otherwise, IER0 is the same as IRR3.

  Bits 0 to 3 of the memory space address 1024h (I / O space address 24h) are unused and are always 0. Note that R / W is R and the initial value is 0.

  Note that if an interrupt is permitted with the interrupt request signal latched in the interrupt request register (IER), the interrupt request signal is immediately output to the CPU core.

[Interrupt priority register]
Next, the interrupt permission register in the internal function register will be described. The interrupt priority order register is a register for setting the priority order of interrupt factors (INT, CTC0, CTC1, CTC2).

  In the interrupt priority register, the symbol IPR3 is associated with bits 7 to 6 of the memory space address 1025h (I / O space address 25h). In IPR3, the CTC2 priority order is set. At 00, the lowest priority level 0 is set. Further, in the case of 01, the level 1 is set to a priority level higher than 00 and lower priority level than 10. When the priority is 10, level 2 is set higher than 01 and lower than 11. In addition, when it is 11, the highest priority level 3 is set. Note that R / W is R / W, and the initial value is 0.

  The symbols IPR2 are associated with bits 5 to 4 of the memory space address 1025h (I / O space address 25h). In IPR2, the CTC1 priority is set. In addition, IPR2 is the same as IPR3.

  Symbols IPR1 are associated with bits 3 to 2 of the memory space address 1025h (I / O space address 25h). In IPR1, the CTC0 priority is set. In addition, IPR1 is the same as IPR3.

  Symbol IPR0 is associated with bits 1 to 0 of memory space address 1025h (I / O space address 25h). In IPR0, the INT priority is set. In addition, IPR0 is the same as IPR3.

  When a plurality of interrupt factors are generated at the same time, an interrupt factor having a higher priority outputs an interrupt request signal to the CPU core. There are four priorities, level 3 is the highest and level 0 is the lowest. If the level is the same, INT, CTC0, CTC1, and CTC2 are in descending order of priority.

[External signal input / reset source register]
Next, the interrupt permission register in the internal function register will be described. The external signal input / reset factor register can know the state of the interrupt input / general-purpose input terminal (INP) and the random number external latch 0-2 terminals (EXLATCH0-2) and the reset generation factor.

  In the external signal input / reset factor register, the symbol WDTRST is associated with bit 7 of the memory space address 1026h (I / O space address 26h). In WDTRST, WDT reset generation is set. In the case of reading, it is set that it does not occur when 0, but occurs when 1. In the case of writing, it is set to clear when 0 and do nothing when 1. Note that R / W is R / W, and the initial value is 0.

  Symbol 6 is associated with bit 6 of memory space address 1026h (I / O space address 26h). In IARST, the occurrence of illegal reset is set. Otherwise, IARST is the same as WDTRST.

  Symbol INTRST is associated with bit 5 of memory space address 1026h (I / O space address 26h). In INTRST, the occurrence of a periodic reset is set. In addition, INTST is the same as WDTRST.

  Bit 4 of the memory space address 1026h (I / O space address 26h) is unused and is always 0. Note that R / W is R and the initial value is 0.

  Symbol INPS is associated with bit 3 of memory space address 1026h (I / O space address 26h). In INPS, an INP terminal number is set. When 0, terminal number = L is set, and when 1, terminal number = R is set. R / W becomes R.

  Symbol LTC2 is associated with bit 2 of memory space address 1026h (I / O space address 26h). In LTC2, the EXLATCH2 terminal number is set. In addition, LTC2 is the same as INPS.

  The symbol LTC1 is associated with bit 1 of the memory space address 1026h (I / O space address 26h). In LTC1, the EXLATCH1 terminal number is set. In addition, LTC1 is the same as INPS.

  Symbol LTC0 is associated with bit 0 of memory space address 1026h (I / O space address 26h). In LTC0, the EXLATCH0 terminal number is set. In addition, LTC0 is the same as INPS.

  Note that the status of the corresponding reset factor is set in WDTRST, IARST, and INTRST. WDTRST, IARST, and INTRST are held until a system reset occurs, and are cleared to 0 after the system reset. Set 0 to clear WDTRST, IARST, and INTRST.

  In INPS, LTC2, LTC1, and LTC0, the signal level of the corresponding terminal is set as it is. INPS is set to the signal level of the INP terminal regardless of the setting state of the reset period of the HW parameter / INP terminal function setting (HPORTTEN) of the INP terminal setting (HRSTCNT).

  A noise filter having a CPU clock of 5 clocks is inserted into the INP terminal. A noise filter of 128 clocks with a random number clock is inserted into the EXLATCH 0 to 2 terminals. Accordingly, 0 (or 1) is set when a continuous L level signal (or H level signal) of 5 clocks or 128 clocks is input.

  PINTTS is initialized when a system reset occurs.

[Random number operation]
As the random number circuit, an 8-bit fixed-length random number circuit, a 16-bit fixed-length random number circuit, an 8-bit variable-length random number circuit, and a 16-bit variable-length random number circuit are provided. The start value for the first week after the system reset is updated each time the system is reset. The pattern of the random number sequence is automatically updated. A 16-bit fixed-length random number can transpose the bit sequence. For the 16-bit fixed-length random number, the operation clock can be selected from 1/2 of MCLK or 1/2 of EXCLK. A random number value can be latched by three random number external latch terminals. Equipped with a function to judge abnormality of random number circuit.

  The 8-bit fixed-length random number circuit and the 16-bit fixed-length random number circuit are automatically activated after a system reset or a WDT reset. The 8-bit variable length random number circuit and the 16-bit variable length random number circuit are stopped after a system reset or WDT reset, and are activated when a maximum value is set. The random number circuit is initialized by a system reset or a WDT reset. When a periodic reset or illegal access reset occurs, the operation continues without affecting the random number function.

  The random number circuit updates the random value while taking discrete values using the initial value as a start value, and causes all the values to appear once without overlapping. After all values appear, another value is used as a start value, the appearance pattern of the sequence is changed to another pattern, and all values are updated again while taking discrete values.

  The random value is updated at the rising edge of the random number clock (1/2 of MCLK or 1/2 of EXCLK). The random number value can be latched by a signal input to the random number external latch 0-2 terminals (EXLATCH0-2).

  Holding or updating the latch data register can be set by the external latch signal mode register (RDEXLM). When RDEXLM is set to 0 (hold), a random value is latched in the random number latch data register only when a signal is input to EXLATCH 0 to 2 with the random number latch data register being cleared. When there is latch data in the random number latch data register, a signal is input to EXLATCH 0 to 2, the random number latch data register is not updated, and the latch data up to that point is held. When RDEXLM is set to 1 (update), the latch data is updated each time a signal is input to EXLATCH0-2.

[Periodic reset monitor register]
Next, the periodic reset monitor register in the internal function register will be described. The periodic reset monitor can read the value of the periodic reset timer counter.

  In the periodic reset monitor register, the symbol ITRMN is associated with bits 7 to 0 of the memory space address 1094h (I / O space address 94h). In ITRMN, a periodic reset monitor is set. And it is set to any one of 00h to FFh. In addition, R / W is R and the initial value is 0.

  The periodic reset is operated by the periodic reset setting (HPRST) of the HW parameter. The periodic reset counter is initialized to 00h by a system reset or a WDT reset, and is up-counted by a periodic reset clock. The periodic reset counter value can be read from the periodic reset monitor register (ITRMN).

[Register configuration]
Next, the register configuration will be described.

[About general-purpose registers]
As register banks, two register banks including a bank 0 and a bank 1 are provided. Each register bank includes eight 8-bit general-purpose registers W, A, B, C, D, E, H, and L, and two 16-bit general-purpose registers IX and IY. W, A, B, C, D, E, H, and L are used for 8-bit transfer and calculation. These registers can be combined and used as WA, BC, DE, and HL. WA, BC, DE, HL, IX, and IY can be used for 16-bit transfer and computation. The general-purpose register is initialized to 00h or 0000h at the time of system reset, WDT reset, periodic reset, and illegal access reset.

[Program status word (PSW)]
Next, PSW will be described. The PSW is a register that holds the state of the operation result and execution result of the instruction, and includes eight types of flags. The PSW is cleared to 00h at the time of system reset, WDT reset, periodic reset, and illegal access reset in accordance with the initialization with the CPU core described above.

  In PSW, bit 7 is associated with symbol JF (jump status flag). JF is a flag used in a 1-byte JRS instruction or the like. As shown in the example in the figure, there are cases where a zero flag is set and a carry flag is set depending on an instruction. Also, as shown in the example in the figure, in the case of INC and DEC instructions, the carry flag does not change, but the jump status flag is set under the condition that the carry flag is set.

  Also, ZF (zero flag) is associated with bit 6. ZF is set to 1 when the operation result or transfer data is 00h (for 8 bits) or 0000h (for 16 bits), and cleared to 0 in other cases. In the exchange command (XCH dst, src), it is set when the value stored in dst is 0.

  Also, CF (carry flag) is associated with bit 5. In CF, carry or borrow at the time of calculation is set. In the case of a division instruction, 1 is set when the division by 0 or the division result is 0100h or more. In the case of INC and DEC instructions, even when a carry or a borrow occurs, the carry flag does not change and holds the value.

  In addition, HF (half carry flag) is associated with bit 4. HF is set to carry or borrow to the fourth bit during 8-bit operation.

  Also, SF (sign flag) is associated with bit 3. SF is set to 1 when the MBS of the operation result is 1, and cleared to 0 otherwise.

  Also, VF (overflow flag) is associated with bit 2. VF is set to 1 when an overflow occurs in the operation result, and cleared to 0 at other times.

  Also, RBS (register bank selector) is associated with bit 1. RBS indicates the bank selected by the general-purpose register.

  Also, IMF (interrupt master permission flag) is associated with bit 0. The IMF becomes IMF = 0 by the DI command, and acceptance of maskable interrupts is prohibited. With the EI command, IMF = 1 and acceptance of maskable interrupts is permitted.

[Stack pointer (SP)]
Next, SP will be described. SP is a 16-bit register indicating the top address of the stack.

  It is post-decremented at the time of a PUSH instruction, a subroutine call, an interrupt is accepted, and pre-incremented at the time of a POP instruction or a return instruction. At the time of a subroutine call (CALL instruction, CALLV instruction), PUSH is performed in order of higher and lower return addresses. When an interrupt is accepted, the push is performed in the order of program status word, return address upper order, and lower order. The SP is initialized to 01FFh at the time of system reset, WDT reset, periodic reset, and illegal access reset.

[Program counter (PC)]
Next, the PC will be described. This is a 16-bit register indicating an address where an instruction to be executed next is stored. It is initialized to 8000h by system reset, WDT reset, periodic reset, and illegal access reset. After the system reset, WDT reset, periodic reset, and illegal access reset are released, program execution starts from address 8000h.

[Summary of operation when the microcomputer starts]
In the microcomputer configured as described above, when power is supplied and reset signals are input from the reset circuit 49 and the reset circuit 95, the system is reset.

  By this system reset, each function of the microcomputer performs the operation described as the operation change due to the reset factor. For example, the CPU core is initialized and the PSW is cleared to 00h accordingly. Therefore, IMF becomes 0, and the interrupt prohibited state is set. An initial value is set in an internal function register (such as a CTC control register or a register related to a random number circuit) in which system reset is defined as an initialization factor.

  Further, various functions are set with reference to the HW parameter. Here, in the HW parameter, it is determined whether or not a condition that the microcomputer does not start (see FIG. 42) is satisfied. If the condition is satisfied, the microcomputer does not start.

  Then, after the set system reset time has elapsed, the initial setting process shown in FIGS. 5 and 6 is executed according to the user program (program stored in “program / data”).

[Example of executing power interruption processing by NMI interrupt (non-maskable interrupt)]
In the above modification, the power interruption process is executed in the timer interrupt process (main) shown in FIGS. 38 and 39. However, the power interruption process may be executed by an NMI interrupt (non-maskable interrupt).

  In this case, when an interrupt request signal is input, an NMI interrupt is generated regardless of the interrupt enabled / disabled state, and the power interruption process is executed. In the power interruption process, first, the interrupt permission / prohibition state immediately before the power interruption is backed up and set to interrupt prohibition. Next, processing similar to the power interruption processing (main) shown in FIG. 10 is executed. When the microcomputer is started and the initial setting process is executed, the process of Sa17 in FIG. 6 is not performed, and the interrupt enable / disable state is restored based on the interrupt enable / disable state when the power is turned off. Let

  When the power interruption process is executed in this way, if the value set in the vector table is a value other than 0000h and 8000h to HPRGEND, the microcomputer is restricted from starting if the start-up condition shown in FIG. 42 is satisfied. To do. That is, if the INT / NMI values at the addresses A7A0h to A7A1h in the vector table are values other than 0000h and 8000h to HPRGEND, the microcomputer activation is limited when the non-activation condition shown in FIG. 42 is satisfied. Thereby, it is possible to prevent an unintentional non-maskable interrupt process from being performed.

  In this example, the timer interrupt processing (main) generation condition is satisfied during a period (for example, 3 cycles) from when the NMI interrupt request signal is input until the NMI interrupt is generated. Is shorter than a period (for example, 4 cycles) from when the timer interrupt occurs. For this reason, a power interruption process can be performed suitably.

  In this example, the main control unit 41 performs the initial setting process, the timer interrupt process (main), and the power interruption process (main). However, the sub control unit 91 performs the initial setting process (sub), Timer interruption processing (sub) and power interruption processing (sub) may be executed.

[Effects of Modifications of First Embodiment, Second Embodiment, First Embodiment, and Second Embodiment]
In the first embodiment, when the number of consecutive replay wins is 3, the execution of the replay notification effect at the time of losing is restricted in the next game (in this example, the portion shown in FIG. 28).
Therefore, the excitement of the game can be raised without betraying the player's expectation.

In the first embodiment, a winning history display is performed (in this example, a portion indicated by Sp8 in FIG. 22).
Therefore, the player can detect that the ART execution condition can be satisfied.

In the first embodiment, a notification to that effect is made after a plurality of games after the provision of ART is confirmed (in this example, the portion shown in FIG. 28).
Therefore, a player's expectation for giving ART can be enhanced.

In the first embodiment, the state in which the ART can be determined is a state in which the number of consecutive replay wins is less than one (in this example, the 3G portion shown in FIG. 28).
Therefore, the player pays attention to the fact that the replay is continuously won, so that the interest of the game can be improved.

In the first embodiment, the ART lottery is executed when the number of consecutive replay wins is three (in this example, the portion indicated by Sj4 in FIG. 21).
Therefore, the player's expectation can be maintained even if the number of consecutive replay winnings, which is an ART granting condition, is not four.

In the first embodiment, when the number of consecutive winnings of replay is 3, the advantageous suggestion condition is satisfied and the precursor effect starts (in this example, the portion shown in FIG. 28).
Therefore, it is possible to increase the player's expectation that ART will be given.

In the first embodiment, the advantage suggestion condition is established when the precursor effect is executed (in this example, the portion shown in FIG. 28).
Therefore, the player's attention to the replay notification effect can be collected.

In the first embodiment, the advantage suggestion condition is satisfied when the winning probability of the ART lottery is high.
Therefore, the player's attention to the replay notification effect can be collected.

In the second embodiment, after the number of consecutive replay wins is 3 and the grant of ART is confirmed, a sign that suggests or informs that ART is awarded from the fifth game in which no additional ART occurs. The effect is executed (in this example, the portion shown in FIG. 32).
Therefore, the interest of the game can be improved without impairing the player's expectation for giving the ART when the display result is derived a plurality of times.

In the second embodiment, ART is given when the number of consecutive replay wins is three, and ART is given when the number of consecutive replay wins is four (in this example, FIG. 29 Part shown in Sn9 and Sn12).
Therefore, the interest of the game can be improved without impairing the player's expectation for giving the ART when the display result is derived a plurality of times.

In the second embodiment, when the number of consecutive replay wins is three, the precursor effect is executed over a plurality of games (in this example, the portion indicated by Sr7 in FIG. 30).
Therefore, it is possible to attract the player's attention as to whether or not notification that ART is given is performed.

In the second embodiment, the ART lottery is executed when the number of consecutive replay winnings is two (in this example, the portion indicated by Sn4 in FIG. 29).
Therefore, the player's expectation can be maintained even if the ART granting condition is not satisfied because the number of continuous replays is three.

In the second embodiment, when the number of consecutive replay wins is two, the sign effect that suggests or notifies that the ART is given after the number of consecutive replay wins is not three. Execute (in this example, the part shown in FIG. 32B).
Therefore, the player's expectation can be maintained even if the ART granting condition is not satisfied because the number of continuous replays is three.

In the modification of the first embodiment and the second embodiment, when the timer interrupt is set in the initial setting process, the interrupt is permitted and the value set in the vector table is a value other than 0000h and 8000h to HPRGEND. In this example, the activation of the microcomputer is limited (in this example, the portions shown in FIGS. 33, 34, and 42).
Therefore, it is possible to prevent an unintended interrupt process from being executed in advance.

In the modification of the first embodiment and the second embodiment, if TMCNT0 to 2 are set even when the CTC is counting, the timer value being counted is updated by setting contents of CTC0 to 2 and TMCNT0 to 2. Counts down again from the set value of CTC0-2.
Therefore, it is possible to prevent an unintended interrupt process from being executed in advance.

In the modification of the first embodiment and the second embodiment, when a system reset is performed and the interrupt controller is initialized, initial values are stored in the interrupt request register, the interrupt permission register, and the interrupt priority register. Is set.
Therefore, it is possible to prevent the interruption process from being executed with unintended settings in advance.

In the modification of the first embodiment and the second embodiment, when the function of the program end address is used and the symbol is HPRGEND and the setting content is the program end address, HPRGEND1 to A6FFh An illegal access reset occurs when an area is accessed.
Therefore, execution of an illegal program can be prevented.

In the modified example of the first embodiment and the second embodiment, in the initial setting process, the interrupt is set to be prohibited before the timer interrupt is set (in this example, the process of Sa1 in FIG. 33). .
Therefore, it is possible to prevent an unintended interrupt process from being executed in advance.

In the modification of the first embodiment and the second embodiment, HSYSMD bit 3 = 1 in the random number circuit operation mode setting (related symbol name: HRDMD) or HSYSCNT in the system setting (related symbol name: HSYSCNT). When the bit 5 = 1, the HSYSCNT bit 6 = 1, and the HSYSCNT bit 7 = 1, the activation of the microcomputer is limited (in this example, the portion shown in FIG. 42).
Therefore, unintended settings can be prevented in advance.

In the modification of the first embodiment and the second embodiment, when the random number generation circuit is set in the initial setting process, the interrupt is permitted and the value set in the vector table is a value other than 0000h and 8000h to HPRGEND. In this example, the activation of the microcomputer is limited (in this example, the portions shown in FIGS. 33, 34, and 42).
Therefore, it is possible to prevent an unintended interrupt process from being executed in advance.

In the modification of the first embodiment and the second embodiment, when RDEXLM is set to 0 (hold), only when the signal is input to EXLATCH 0 to 2 while the random number latch data register is cleared, the random number latch data A random value is latched in the register. When 1 (update) is set in RDEXLM, the latch data is updated each time a signal is input to EXLATCH 0 to 2 (in this example, the portion shown in [Random number operation]).
Therefore, it is possible to prevent an unintended random value from being taken in.

In the modification of the first embodiment and the second embodiment, when the system reset is performed and the random number circuit is initialized, initial values are set in the registers related to the random number circuit.
Therefore, it is possible to prevent the numerical data that becomes a random value from being set unintentionally.

In the modification of the first embodiment and the second embodiment, interrupts are prohibited during the initial setting process, and if the value set in the vector table is a value other than 0000h and 8000h to HPRGEND, the start of the microcomputer is restricted. (In this example, the portions shown in FIGS. 33, 34, and 42).
Therefore, it is possible to prevent an unintended interrupt process from being executed in advance.

In the modification of the first embodiment and the second embodiment, any one of the initializations 1 to 4 is selected and executed according to the initialization condition (in this example, the portion indicated by [About initialization]).
Therefore, it is possible to prevent an unintended interrupt process from being executed in advance.

In the modification of the first embodiment and the second embodiment, the interrupt is prohibited before the output port is initialized (in this example, the prohibition is executed before Sm3 in FIG. 40).
Therefore, it is possible to prevent unintended data from being output.

In the modification of the first embodiment and the second embodiment, the interruption permission / prohibition state at the time of power interruption is backed up in the power interruption process and the interruption permission / prohibition state at the time of power interruption is restored by the initial setting process. When the values set in the vector table are values other than 0000h and 8000h to HPRGEND, the activation of the microcomputer is restricted (in this example, [Modification], the portion shown in FIG. 42).
Therefore, it is possible to prevent an unintended interrupt process from being executed in advance.

In the modification of the first embodiment and the second embodiment, the activation of the microcomputer is limited when the INT / NMI values in the addresses A7A0h to A7A1h of the vector table are values other than 0000h and 8000h to HPRGEND (this book In the example, [Modification], part shown in FIG.
Therefore, it is possible to prevent an unintended interrupt process from being executed in advance.

In the modification of the first embodiment and the second embodiment, the period from when the NMI interrupt signal is input to when the NMI interrupt is generated is after the generation condition of the timer interrupt process (main) is satisfied. It is shorter than the period until the timer interrupt occurs (in this example, the portion shown in [Modification]).
Therefore, the power interruption process can be suitably executed.

In the modification of the first embodiment and the second embodiment described above, different areas of the RAM are initialized depending on whether or not the contents of the RAM are abnormal (in this example, the process of Sb3 is performed in the case of N in Sb2 of FIG. 35). A part that executes Sb4 processing and executes Sb4 processing without executing Sb3 processing when Sb2 is Y).
Therefore, it is possible to suitably execute initialization of the RAM.

In the modification of the first embodiment and the second embodiment described above, the RAM is initialized even when the setting key is not on when it is determined that the contents of the RAM are not normal (in this example, Sa23 and Sa24 in FIG. 34). The part that executes the process).
Therefore, it is possible to prevent the control from being performed in a state where the storage contents of the RAM are not normal.

In the modification of the first embodiment and the second embodiment, an area including a set value is initialized when it is determined that the contents of the RAM are not normal, and the set value is set when it is determined that the contents of the RAM are normal. (In this example, if Sb2 in FIG. 35 is N, Sb3 processing is executed and Sb4 processing is executed, and if Sb2 is Y, Sb3 processing is not executed. The part that executes the process).
Therefore, the set value can be suitably protected.

In the modification of the first embodiment and the second embodiment, the RAM abnormality flag is set when the RAM contents are abnormal, and whether or not the RAM contents are abnormal based on the RAM abnormality flag in the initial setting process. (In this example, a portion for executing the processing of Sa25 in FIG. 34 and Sa16 in FIG. 33).
Therefore, it is possible to prevent the control from restarting when the storage content of the storage means is not normal.

In the modification of the first embodiment and the second embodiment, when the RAM is initialized, the interrupt is prohibited (in this example, the processing of Sa1 in FIG. 33 and Sc1 in FIG. 37 is executed).
Therefore, it is possible to prevent other processing from being performed during initialization.

In the modification of the first embodiment and the second embodiment, the interrupt is prohibited before the output port is initialized (in this example, the prohibition is executed before Sm3 in FIG. 40).
Therefore, it is possible to prevent unintended data from being output.

In the modified example of the first embodiment and the second embodiment, the execution of the main process is started from the process before the initialization of the RAM for each game after the setting change process is completed (in this example, the setting change is performed). A portion where execution is started from the processing of Sc1 in FIG. 37 after the processing is completed).
Therefore, in addition to the initialization in the setting change process, the initialization for each game can be executed.

In the modification of the first embodiment and the second embodiment, when the timer interrupt is set in the initial setting process, the interrupt is permitted and the value set in the vector table is a value other than 0000h and 8000h to HPRGEND. In this example, the activation of the microcomputer is limited (in this example, the portions shown in FIGS. 33, 34, and 42).
Therefore, it is possible to prevent an unintended interrupt process from being executed in advance.

In the modified example of the first embodiment and the second embodiment, the execution of the main process is started from the process before the initialization of the RAM for each game after the setting change process is completed (in this example, the setting change is performed). A portion where execution is started from the processing of Sc1 in FIG. 37 after the processing is completed).
Therefore, initialization for each game of one game can be executed in a suitable state.

In the modification of the first embodiment and the second embodiment, in the initialization of the setting change process, all the areas (including the unused area and the unused stack area) except the used stack area are initialized, and each game is changed. In the initialization, the unused area and the unused stack area are initialized (in this example, the process of Sb4 in FIG. 35 and the process of Sc3 in FIG. 37).
Therefore, initialization can be surely performed.

In the modification of the first embodiment and the second embodiment, the interrupt process is executed during the setting change process, and the main process is performed before the RAM initialization for each game is executed after the setting change process is completed. Start (in this example, the part that executes the process of Sb6 in FIG. 35).
Therefore, the data rewritten by the interrupt process executed during the setting change process can be initialized by the initialization for each game.

In the modification of the first embodiment and the second embodiment, interrupts are prohibited during the startup of the microcomputer, and interrupts are prohibited during the initial setting process (in this example, PSW is set to 00h when the microcomputer is started up). Cleared to set IMF to 0 and set to the interrupt disabled state, and execute the process of Sa1 in FIG. 33 by executing the DI command in the initial setting process).
Therefore, it is possible to prevent an unintended interrupt from occurring.

In the modification of the first embodiment and the second embodiment, the interrupt is permitted after setting the timer interrupt in the initial setting process (in this example, the part for executing the processes of Sa20 and Sa22 in FIG. 34). .
Therefore, it is possible to prevent an unintended interrupt from occurring.

In the modification of the first embodiment and the second embodiment, if TMCNT0 to 2 are set even when the CTC is counting, the timer value being counted is updated by setting contents of CTC0 to 2 and TMCNT0 to 2. Counts down again from the set value of CTC0-2.
Therefore, it is possible to prevent an unintended interrupt process from being executed in advance.

In the modification of the first embodiment and the second embodiment, when a system reset is performed and the interrupt controller is initialized, initial values are stored in the interrupt request register, the interrupt permission register, and the interrupt priority register. Is set.
Therefore, it is possible to prevent the interruption process from being executed with unintended settings in advance.

In the modification of the first embodiment and the second embodiment, when the function of the program end address is used and the symbol is HPRGEND and the setting content is the program end address, HPRGEND1 to A6FFh An illegal access reset occurs when an area is accessed.
Therefore, execution of an illegal program can be prevented.

[Other variations]
Hereinafter, various modifications of the above embodiment will be described.

[About the conditions for granting benefits]
In the above-described embodiment, the privilege granting condition is that the number of replay winnings continues for a predetermined number of times, but other conditions may be given as the granting condition. For example, it is possible to make the grant condition that the number of consecutive winnings of a specific lottery target role reaches a predetermined number.

  In the above embodiment, the case where the number of consecutive replay winnings is 3 times and the case where the number of consecutive winnings of replaying is 2 is given as an example of the privilege grant condition. It is good also as grant conditions. For example, it is possible to make the quasi-grant condition that an ART lottery is performed every time a replay is won or won, and an ART lottery is won.

[About benefits]
In the above embodiment, ART is applied as a privilege that is advantageous to the player. However, a right that allows the player to shift to an advantageous state that is advantageous to the player (in a lottery that determines whether or not an advantageous state is generated). Winning the game, allowing winnings to be changed to an advantageous state, etc.), the right to be notified of an operation mode advantageous to the player, the right to be controlled to a gaming state with a high expected value to which a gaming value is given, The right to be notified whether or not the current gaming state is advantageous for the player, the period during which it is controlled to the advantageous state (the number of fixed games, the average value of the number of games that vary depending on the end condition, etc.), etc. Direct advantageous benefits may be applied, and it is not directly advantageous to the player, but indirectly for the player, for example, a condition for obtaining the privilege on the Internet. It may be applied to interest benefits.

[About ART]
In the above embodiment, the main control unit 41 performs ART lottery by performing ART lottery, but the sub-control unit 91 may perform ART control. For example, the sub control unit 91 can perform the ART lottery and manage the number of ART games, or the main control unit 41 can perform the ART lottery and the sub control unit 91 can manage the number of ART games.

  As mentioned above, although embodiment of this invention was described with drawing, this invention is not limited to this embodiment, Even if there is a change and addition in the range which does not deviate from the main point of this invention, it is contained in this invention. Needless to say.

  In the embodiment, the example in which the present invention is applied to a slot machine in which bets are set using medals and credits as game values has been described. However, slots for setting bets using game balls as game values. The present invention may be applied to a machine or a fully credit type slot machine that sets a bet amount using only credit as a gaming value. When game balls are used as game values, for example, one medal can correspond to five game balls, and when three bets are set in the first embodiment, 15 game balls are used. This is equivalent to setting the number of bets using.

  Further, the present invention is not limited to the use of only one of a plurality of types of game values such as medals and game balls, for example, a combination of a plurality of types of game values such as medals and game balls. It may be. That is, it is possible to play a game by setting the number of bets using any of a plurality of types of gaming values such as medals and game balls, and a plurality of types of games such as medals and game balls when a winning occurs. You may apply the slot machine which can pay out all of utility values.

  The first embodiment includes the following inventions and provides the following effects.

A variable display unit capable of variably displaying a plurality of types of identification information each identifiable, and after variably displaying the variable display unit, deriving a display result by stopping the variable display of the variable display unit, In a slot machine (for example, slot machine 1) that can generate a prize according to the display result,
A display result determining means (for example, a portion indicated by Sd2 in FIG. 20) for determining a display result that allows derivation;
A privilege granting means (for example, a portion shown in FIG. 21) for granting a privilege (for example, ART) when a grant condition that can be satisfied when a plurality of games are performed is satisfied;
Production execution means (for example, a portion indicated by Sp6 in FIG. 22) that produces an effect before the display result is derived based on the determination result of the display result determination means,
The effect executing means can execute a specific effect (for example, a replay notification effect) suggesting that the specific display result is allowed to be derived when the specific display result is allowed to be derived. An advantageous suggestion condition is satisfied when the allowance time execution means (for example, the portion for performing the effect determination lottery using the precursor replay table indicated by Sg15 in FIG. 25) and the derivation of the specific display result are not permitted. Non-permissible execution means (for example, a part for performing the effect determination lottery using the sign loss table shown by Sg5 in FIG. 24) capable of executing a specific effect when
The non-permitted execution means restricts execution of the specific effect when the provision condition can be satisfied by deriving a display result (for example, a portion shown in FIG. 28).
According to this configuration, it is possible to excite the interest of the game without betraying the player's expectation.

Condition establishment notifying means (for example, a portion indicated by Sp8 in FIG. 22) for notifying that the provision condition can be established is provided.
According to this configuration, the player can detect that the grant condition can be satisfied.

Included is a privilege grant notification means (for example, a portion shown in FIG. 28) for notifying that a privilege is granted after a predetermined period of time has passed since the grant condition is established.
According to this configuration, it is possible to increase the player's expectation for the provision of the privilege.

The privilege grant means grants a privilege as a grant condition is satisfied when the number of consecutive derivations of a specific display result reaches a predetermined number of times,
The non-permitted execution means is such that the application condition can be satisfied when the variable display portion is performing variable display in a state where the number of consecutive derivations of a specific display result is one less than a predetermined number (for example, four times). The execution of a specific effect is restricted (for example, the 3G portion shown in FIG. 28).
According to this configuration, the player pays attention to the fact that specific display results are continuously derived, so that the interest of the game can be improved.

Bonus grant lottery means (for example, determining whether or not to grant a privilege by lottery when the semi-grant condition established before the grant condition is satisfied (for example, when the number of consecutive replay wins is 3) , A portion indicated by Sj4 in FIG.
According to this configuration, the player's expectation can be maintained even if the grant condition is not satisfied.

The advantage suggestion condition is established based on the establishment of the semi-grant condition (for example, a portion shown in FIG. 28).
According to such a configuration, it is possible to increase the player's expectation that a privilege will be granted.

Provided with a sign production execution means for performing a sign production that suggests the possibility of a privilege being given over a plurality of games;
The advantage suggestion condition is satisfied during the period when the precursor effect is executed (for example, the portion shown in FIG. 28).
According to such a configuration, in the game when the advantageous suggestion condition is established, it is possible to attract the player's attention produced by the non-permissible execution means.

Provided with a grant probability changing means for changing the probability that a privilege is granted,
The advantage suggestion condition is established when the probability that the privilege is granted is high. According to such a configuration, in the game when the advantage suggestion condition is established, the non-permissible execution means It can attract the attention of the player who produces by

1 slot machine 2L, 2C, 2R reel 6 MAXBET switch 7 start switch 8L, 8C, 8R stop switch 41 main control unit 56 effect switch 91 sub control unit

Claims (1)

A variable display unit capable of variably displaying a plurality of types of identification information each identifiable, and after variably displaying the variable display unit, deriving a display result by stopping the variable display of the variable display unit, In a slot machine that can generate a prize according to the display result,
A display result determining means for determining a display result that allows derivation;
Derivation control means for deriving a display result based on the determination result of the display result determination means;
A privilege granting means for granting a privilege when a first grant condition that can be established when a plurality of games are played is established;
An informing means for informing that a privilege is granted based on the establishment of the first grant condition;
The privilege granting means grants a privilege even when a second grant condition that can be met after the first grant condition is met,
The notification means grants a privilege based on the fact that the first grant condition is met after the second grant condition cannot be met after the first grant condition is met. A slot machine that starts control for informing the user.

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