JP2016149603A - Synchronization determination system, communication system, and synchronization determination method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a synchronization determination system, a communication system, and a synchronization determination method capable of sufficiently accurately determining whether erroneous lead-in is performed or not.SOLUTION: A synchronization determination part 11 determines whether a demodulated signal obtained by demodulating an input signal by a demodulation circuit 20 and a reference signal are synchronized with each other. When the synchronization determination part 11 determines that the demodulated signal and the reference signal are synchronized, a phase difference detector 12 detects the phase difference between a test signal based on the input signal and the reference signal. On the basis of the phase difference detected by the phase difference detector 12, a reset part 13 inputs a reset signal to the demodulation circuit 20 to reset.SELECTED DRAWING: Figure 11

Description

  The present invention relates to a synchronization determination system, a communication system, and a synchronization determination method for determining whether or not an input signal and a reference signal are synchronized in a digital wireless communication system.

  There is a demodulation circuit mounted on a receiving module in a microwave digital wireless communication system. Such a demodulation circuit performs a process of pulling in to synchronize the input signal with the reference signal when an error occurs in the phase of the input signal with respect to the reference signal.

  Patent Documents 1 to 3 describe a technique for detecting an erroneous pull-in that synchronizes an input signal with an incorrect timing in a reference signal in such a demodulation circuit.

  In the techniques described in Patent Documents 1 and 2, the value of the input signal is used to determine whether or not erroneous pull-in has been performed. Specifically, the techniques described in Patent Documents 1 and 2 determine that erroneous pull-in has been performed when the position where the input signal is mapped on the phase plane is within a predetermined region. In addition, the technique described in Patent Document 3 performs erroneous pull-in when the value of the phase error from the reference signal matches the value of the phase error when the frame becomes asynchronous in the past. judge.

JP 2006-157186 A JP 2008-118471 A JP 2009-164877 A

  However, the techniques described in Patent Documents 1 and 2 determine that erroneous pull-in has been performed even when erroneous pull-in is performed when the position where the input signal is mapped is outside a predetermined region. I can't. In particular, when an unexpected event occurs, erroneous pull-in may occur even when the position where the input signal is mapped is outside a predetermined region. However, the techniques described in Patent Documents 1 and 2 are In such a case, it cannot be determined that an erroneous pull-in has been performed.

  The technique described in Patent Document 3 cannot determine that erroneous pull-in has been performed when a frame error state has not been obtained in the past due to a phase error value from the reference signal.

  Therefore, the techniques described in Patent Documents 1 to 3 have a problem that it cannot be determined with sufficient accuracy whether or not erroneous pull-in has been performed.

  Therefore, an object of the present invention is to provide a synchronization determination system, a communication system, and a synchronization determination method that can determine whether or not erroneous pull-in has been performed with sufficient accuracy.

  The synchronization determination system according to the present invention includes a synchronization determination unit that determines whether or not an input signal is demodulated by a demodulation circuit and a reference signal, and the synchronization determination unit includes a demodulated signal and a reference signal. When it is determined that they are synchronized, the phase difference detection means for detecting the phase difference between the test signal based on the input signal and the reference signal, and reset to the demodulation circuit based on the phase difference detected by the phase difference detection means And a reset means for inputting and resetting a signal.

  A communication system according to the present invention includes any one of the synchronization determination systems and a demodulation circuit.

  The synchronization determination method according to the present invention includes a synchronization determination step for determining whether or not an input signal is demodulated by a demodulation circuit and a reference signal in synchronization, and the demodulation signal and the reference signal at the synchronization determination step. When it is determined that they are synchronized, the phase difference detection step detects the phase difference between the test signal based on the input signal and the reference signal, and resets to the demodulation circuit based on the phase difference detected in the phase difference detection step And a reset step for resetting by inputting a signal.

  According to the present invention, it is possible to determine whether or not erroneous pull-in has been performed with sufficient accuracy.

It is a block diagram which shows the structural example of the determination system of the 1st Embodiment of this invention. It is explanatory drawing which shows the example of the signal input into the orthogonal demodulator. It is explanatory drawing which shows the example of the signal of the baseband input into an AD converter. It is a signal point arrangement diagram showing an Ich signal component and a Qch signal component of a signal input to the first adjustment circuit. FIG. 5 is a signal point arrangement diagram showing an Ich signal component and a Qch signal component of a signal input to a carrier recovery circuit and an erroneous pull-in determination circuit. FIG. 10 is a signal point arrangement diagram showing an Ich signal component and a Qch signal component of a signal input to a second adjustment circuit. FIG. 4 is a signal point arrangement diagram showing an Ich signal component and a Qch signal component of a signal inputted to an equalizer and an erroneous pull-in determination circuit. FIG. 5 is a signal point arrangement diagram showing Ich signal and Qch signal components of a signal that is output to the outside and input to the frame synchronization circuit by the equalizer. It is explanatory drawing which shows the signal for frame-synchronization determination among the signals input by the equalizer. It is a flowchart which shows operation | movement of the determination system of the 1st Embodiment of this invention. It is a block diagram which shows the structural example of the synchronous determination system of the 2nd Embodiment of this invention.

Embodiment 1. FIG.
A determination system 100 according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration example of a determination system 100 according to the first embodiment of this invention. As shown in FIG. 1, the determination system 100 according to the first embodiment of the present invention is connected to a demodulation circuit 200 and includes a frame synchronization circuit 110, an erroneous pull-in determination circuit 120, and a reset signal generation circuit 130.

  First, the demodulation circuit 200 to which the determination system 100 according to the first embodiment of the present invention is connected will be described. As shown in FIG. 1, the demodulation circuit 200 includes a quadrature demodulator 210, an oscillator 220, an analog-to-digital (AD) converter 230, a first adjustment circuit 240, a carrier recovery circuit 250, and a second adjustment. A circuit 260 and an equalizer 270 are included.

  The oscillator 220 outputs an oscillator signal for reproducing the carrier wave used for transmission of the signal input to the quadrature demodulator 210. FIG. 2 is an explanatory diagram illustrating an example of a signal input to the quadrature demodulator 210. As shown in FIG. 2, the signal input to the quadrature demodulator 210 is a signal having a frequency within a predetermined range centered on the intermediate frequency fc. In FIG. 2, the envelope range of the signal input to the quadrature demodulator 210 is illustrated by diagonal lines. The oscillator signal is a signal having a frequency close to the frequency of the output signal transmitted from the oscillator for outputting the carrier wave by the modulation circuit on the transmission side.

  The quadrature demodulator 210 converts the intermediate frequency modulated wave signal input to the demodulation circuit 200 into baseband signals orthogonal to each other, and inputs the baseband signals to the AD converter 230. In the example illustrated in FIG. 1, an Ich signal component 301 and a Qch signal component 302 are input to the A / D converter 230 in the baseband signal. FIG. 3 is an explanatory diagram illustrating an example of a baseband signal input to the AD converter 230. In FIG. 3, the range of the envelope of the baseband signal that is a sufficiently low frequency band from the frequency of the carrier wave is illustrated by hatching.

  The A-D converter 230 converts a baseband signal, which is an analog signal, into a digital signal in order to perform subsequent processing on the digital signal. Then, the AD converter 230 inputs the converted signal to the first adjustment circuit 240. In the example shown in FIG. 1, it is shown that the Ich signal component 303 and the Qch signal component 304 of the signal are input to the first adjustment circuit 240. FIG. 4 is a signal point arrangement diagram showing the Ich signal component 303 and the Qch signal component 304 of the signal input to the first adjustment circuit 240. The signal input to the first adjustment circuit 240 is not synchronized with the carrier wave. Therefore, the Ich signal component 303 and the Qch signal component 304 are shown at any position on the circumference in the signal point arrangement diagram shown in FIG. Therefore, in FIG. 4, the positions where the Ich signal component 303 and the Qch signal component 304 can be arranged are shown in a circle. Further, since the level and DC component of the signal input to the first adjustment circuit 240 is not adjusted, the center of the circle is not the intersection of the I axis and the Q axis in the example shown in FIG.

  The first adjustment circuit 240 adjusts the level and DC component of the signal input by the A / D converter 230 according to the processing capability of the carrier wave recovery circuit 250. Then, the first adjustment circuit 240 inputs the adjusted signal to the carrier wave recovery circuit 250 and the erroneous pull-in determination circuit 120. In the example shown in FIG. 1, it is shown that the Ich signal component 305 and the Qch signal component 306 of the signal are input to the carrier wave reproduction circuit 250 and the erroneous pull-in determination circuit 120. FIG. 5 is a signal point arrangement diagram showing the Ich signal component 305 and the Qch signal component 306 of the signal input to the carrier wave recovery circuit 250 and the erroneous pull-in determination circuit 120. Signals input to the carrier recovery circuit 250 and the erroneous pull-in determination circuit 120 are adjusted in level and DC component by the first adjustment circuit 240. Therefore, in the example shown in FIG. 5, the center of the circle where the Ich signal component 305 and the Qch signal component 306 can be located on the circumference is the intersection of the I axis and the Q axis.

  The carrier recovery circuit 250 recovers the carrier used for transmitting the signal input to the demodulation circuit 200 based on the signal input by the first adjustment circuit 240. A known method is used to reproduce the carrier wave. The carrier wave reproduction circuit 250 detects the signal input by the first adjustment circuit 240 based on the reproduced carrier wave, and inputs the detection result signal to the second adjustment circuit 260. FIG. 6 is a signal point arrangement diagram showing the Ich signal component 307 and the Qch signal component 308 of the signal input to the second adjustment circuit 260.

  The second adjustment circuit 260 modulates the level and direct current component of the signal input by the carrier wave recovery circuit 250 so that the signal is modulated and transmitted to another device. Then, the second adjustment circuit 260 inputs the adjusted signal to the equalizer 270 and the erroneous pull-in determination circuit 120. FIG. 7 is a signal point arrangement diagram showing the Ich signal component 309 and the Qch signal component 310 of the signal input to the equalizer 270 and the erroneous pull-in determination circuit 120. Since the Ich signal component 309 and the Qch signal component 310 have been adjusted in level and DC component by the second adjustment circuit 260, in the example shown in FIG. 7, each point is between the intersection of the I axis and the Q axis. The distances are shown arranged in adjusted positions.

  The equalizer 270 adjusts the frequency characteristic and the phase characteristic in order to transmit the signal input by the second adjustment circuit 260. Then, the equalizer 270 outputs the adjusted signal to the outside and inputs it to the frame synchronization circuit 110. FIG. 8 is a signal point arrangement diagram showing the Ich signal 311 and the Qch signal component 312 of the signal that the equalizer 270 outputs to the outside and inputs to the frame synchronization circuit 110. In FIG. 8, positions corresponding to the Ich signal component 311 and the Qch signal component 312 are indicated by white circles (◯), and positions corresponding to the Ich signal component 309 and the Qch signal component 310 are indicated by black circles (●). Yes. Frequency characteristics and phase characteristics of the Ich signal component 311 and the Qch signal component 312 are adjusted by the equalizer 270. Therefore, the positional relationship between each point corresponding to the Ich signal component 311 and the Qch signal component 312 and the Q axis and the I axis in the example shown in FIG. It is shown rotated about the intersection of the axis and the I axis.

  The configuration of the determination system 100 according to the first embodiment of the present invention will be described. The frame synchronization circuit 110 is an oscillator (not shown) that receives a signal having a frequency close to the frequency of the output signal transmitted from the oscillator for outputting the carrier wave by the modulation circuit on the transmission side of the signal input to the quadrature demodulator 210. ) Is connected. Then, the frame synchronization circuit 110 determines whether or not the reference signal input by the oscillator and the signal input by the equalizer 270 are synchronized. Specifically, the frame synchronization circuit 110 determines whether or not the equalizer 270 has input a frame synchronization determination signal within a predetermined period based on the input reference signal, for example. FIG. 9 is an explanatory diagram showing a frame synchronization determination signal among the signals input by the equalizer 270. The signal for frame synchronization determination is indicated by hatching in FIG. As shown in FIG. 9, in a frame (which may be a subframe) constituted by a signal input to the equalizer 270, a section A including a frame synchronization determination signal is included in the overhead section. Yes. In this example, it is assumed that section A is modulated by QPSK (Quadrature Phase Shift Keying) for frame synchronization determination.

  The frame synchronization circuit 110 determines that the frame is not synchronized when the timing at which the frame synchronization determination signal is input is not within a predetermined period, and indicates that the frame is not synchronized with the reset signal generation circuit 130. Input frame asynchronous signal. Further, the frame synchronization circuit 110 is configured by the signal input by the equalizer 270 by determining that the frame is synchronized when the timing at which the frame synchronization determination signal is input is within a predetermined period. Are synchronized with a predetermined timing based on the reference signal. Then, the frame synchronization circuit 110 inputs a false pull determination signal to the false pull determination circuit 120. For example, as shown in FIG. 9, the erroneous pull-in determination signal is a signal input to the erroneous pull-in determination circuit 120 at a timing according to the frame synchronization determination signal described above, and a signal modulated by QPSK is used. It is done.

  The erroneous pull determination circuit 120 detects a difference between the erroneous pull determination signal input by the frame synchronization circuit 110 and the signal including the Ich signal component 305 and the Qch signal component 306 input by the first adjustment circuit 240. Specifically, for example, the difference between the Ich signal component and the Ich signal component 305 of the erroneous pull-in determination signal and the difference between the Qch signal component and the Qch signal component 306 of the erroneous pull-in determination signal are detected.

  Further, the erroneous acquisition determination circuit 120 detects a difference between the erroneous acquisition determination signal input by the frame synchronization circuit 110 and the signal including the Ich signal component 309 and the Qch signal component 310 input by the second adjustment circuit 260. Specifically, for example, the difference between the Ich signal component and the Ich signal component 309 of the erroneous pull-in determination signal and the difference between the Qch signal component and the Qch signal component 310 of the erroneous pull-in determination signal are detected.

  Then, the erroneous pull-in determination circuit 120 inputs an erroneous pull-in determination result signal indicating that the erroneous pull-in has occurred to the reset generation circuit 130 when at least one of the detected differences is equal to or greater than a predetermined threshold. Further, the erroneous pull-in determination circuit 120 outputs a device failure signal when a reset signal described later is input from the reset signal generation circuit 130 a predetermined number of times within a predetermined time. The signal input to the erroneous pull determination circuit 120 by the first adjustment circuit 240 and the signal input to the erroneous pull determination circuit 120 by the second adjustment circuit 260 may be collectively referred to as a test signal.

  The reset signal generation circuit 130 performs the following processing when a frame asynchronous signal is input by the frame synchronization circuit 110 or when an erroneous acquisition determination result signal is input by the erroneous acquisition determination circuit 120. That is, the reset signal generation circuit 130 is a reset signal for causing the first adjustment circuit 240, the carrier wave recovery circuit 250, the second adjustment circuit 260, the equalizer 270, and the erroneous pull-in determination circuit 120 to reset the input destination circuit. Enter. Then, the settings of the first adjustment circuit 240, the carrier wave recovery circuit 250, the second adjustment circuit 260, and the equalizer 270 are reset.

  Next, operation | movement of the determination system 100 of the 1st Embodiment of this invention is demonstrated. FIG. 10 is a flowchart illustrating the operation of the determination system 100 according to the first embodiment of this invention. As shown in FIG. 10, in the determination system 100 according to the first embodiment of the present invention, the frame synchronization circuit 110 determines whether the reference signal input by the oscillator and the signal input by the equalizer 270 are synchronized. Is determined (step S101).

  When the frame synchronization circuit 110 determines that the reference signal and the signal input by the equalizer 270 are not synchronized (N in step S101), the frame synchronization circuit 110 inputs the frame asynchronous signal to the reset signal generation circuit 130 (step S101). S102). Then, the process proceeds to step S107.

  In addition, when the frame synchronization circuit 110 determines that the reference signal and the signal input from the equalizer 270 are synchronized (Y in step S101), the frame synchronization circuit 110 outputs an error acquisition determination signal to the error acquisition determination circuit 120. Input (step S103).

  The erroneous pull determination circuit 120 detects a difference between the erroneous pull determination signal input by the frame synchronization circuit 110 and the signal including the Ich signal component 305 and the Qch signal component 306 input by the first adjustment circuit 240. Further, the erroneous acquisition determination circuit 120 detects a difference between the erroneous acquisition determination signal input by the frame synchronization circuit 110 and the signal including the Ich signal component 309 and the Qch signal component 310 input by the second adjustment circuit 260 ( Step S104).

  Then, the erroneous pull-in determination circuit 120 inputs an erroneous pull-in determination result signal to the reset generation circuit 130 when the difference detected for any of the test signals is equal to or greater than a predetermined threshold (Y in Step S105) (Step S105). S106). Then, the process proceeds to step S107. The erroneous pull-in determination circuit 120 ends the process when the detected difference is not equal to or greater than the predetermined threshold (N in step S105). In the erroneous pull-in determination circuit 120, a predetermined threshold value may be set in advance for each of the first adjustment circuit 240 and the second adjustment circuit 260 that are input sources of signals.

  The reset signal generation circuit 130, when a frame asynchronous signal is input by the frame synchronization circuit 110 in the process of step S102, or when an erroneous pull-in determination result signal is input by the erroneous pull-in determination circuit 120 in the process of step S106, In the processing of step S107, the following processing is performed. That is, the reset signal generation circuit 130 inputs a reset signal to the first adjustment circuit 240, the carrier wave recovery circuit 250, the second adjustment circuit 260, the equalizer 270, and the erroneous pull-in determination circuit 120 (step S107). The first adjustment circuit 240, the carrier wave recovery circuit 250, the second adjustment circuit 260, and the equalizer 270 that have received the reset signal reset the settings.

  The erroneous pull-in determination circuit 120, when a reset signal is input in the process of step S107, when the number of times the reset signal is input from a predetermined time before is a predetermined number or more (Y in step S108). An equipment failure signal is output (step S109). The equipment failure signal is a signal indicating that an abnormality has occurred in the demodulation circuit 200, for example. The equipment failure signal output in step S109 is input to a management terminal (not shown) such as the demodulation circuit 200, for example. When the management terminal receives a device failure signal, for example, the display unit (not shown) connected to the management terminal may have a failure in the demodulation circuit 200 or the like. Is displayed to prompt the administrator to deal with the failure.

  According to the present embodiment, the erroneous pull-in determination circuit 120 compares the difference between the test signal and the erroneous pull-in determination signal with a predetermined threshold set in advance for each input source of the test signal. Determine whether it was done. Therefore, even if an unexpected event occurs and the position where the input signal is mapped is outside the predetermined area, it can be determined whether or not an erroneous pull-in has occurred. Further, even when the difference between the test signal and the erroneous pull-in determination signal is not a value that has been previously determined as erroneous pull-in, it can be determined that erroneous pull-in has been performed. Therefore, it can be determined with sufficient accuracy whether or not erroneous pull-in has been performed.

  Based on the accurate determination result, the reset signal generation circuit 130 inputs the reset signal to the first adjustment circuit 240, the carrier wave recovery circuit 250, the second adjustment circuit 260, and the equalizer 270 of the demodulation circuit 200. Reset it. Therefore, the first adjustment circuit 240, the carrier wave recovery circuit 250, the second adjustment circuit 260, and the equalizer 270 of the demodulation circuit 200 are reset only at appropriate occasions, and the number of times they are reset can be reduced. Therefore, it is possible to reduce the time required for drawing the input signal in the operation time of the demodulation circuit 200.

  Further, the erroneous pull-in determination circuit 120 determines whether erroneous pull-in has been performed based on a difference between each test signal and an erroneous pull-in determination signal, and a predetermined threshold set in advance for each input source of the test signal. Determine whether. Therefore, an appropriate threshold value can be set according to the input source of each test signal, and it can be determined whether or not erroneous pull-in has been performed. Therefore, it can be determined with sufficient accuracy whether or not erroneous pull-in has been performed.

  In a general receiving circuit, for example, when a signal QPSK modulated by a transmitting circuit is out of phase with respect to a reference signal by about ± π / 4 due to malfunction of at least one of the transmitting circuit and the receiving circuit. In some cases, erroneous pull-in occurs and demodulation is performed. Then, problems such as unstable operation of the demodulation circuit occur. Therefore, it is preferable to determine whether or not erroneous pull-in has occurred with high accuracy. The time required for determining whether or not erroneous pull-in has occurred greatly affects the time required for pull-in in the synchronization characteristics of wireless communication. As in this example, when at least the section A for detecting the difference from the erroneous pull-in determination signal is QPSK modulated, four signal points are used for the synchronization determination using the section A. It is done. In this case, it is possible to use a highly accurate determination method even if transmission takes more time than in the case where modulation is performed using a multi-level modulation method with more signal points. Therefore, according to this example, it can be determined with sufficient accuracy whether or not erroneous pull-in has occurred. Therefore, the demodulation circuit 200 can be reset only at an appropriate timing. Therefore, in the operation time of the demodulation circuit 200, the time required for resetting and restarting can be reduced.

Embodiment 2. FIG.
A synchronization determination system 10 according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 11 is a block diagram illustrating a configuration example of the synchronization determination system 10 according to the second embodiment of this invention. As shown in FIG. 11, the synchronization determination system 10 according to the second exemplary embodiment of the present invention is connected to a demodulation circuit 20 and includes a synchronization determination unit 11, a phase difference detection unit 12, and a reset unit 13.

  The synchronization determination unit 11 corresponds to the frame synchronization circuit 110 in the first embodiment of the present invention shown in FIG. The phase difference detection unit 12 corresponds to the erroneous pull-in determination circuit 120 in the first embodiment of the present invention shown in FIG. The reset unit 13 corresponds to the reset signal generation circuit 130 in the first embodiment of the present invention shown in FIG. Further, the demodulation circuit 20 corresponds to the demodulation circuit 200 shown in FIG.

  The synchronization determination unit 11 determines whether or not the demodulated signal obtained by demodulating the input signal by the demodulation circuit 20 is synchronized with the reference signal.

  When the synchronization determination unit 11 determines that the demodulated signal and the reference signal are synchronized, the phase difference detection unit 12 detects the phase difference between the test signal and the reference signal based on the input signal.

  Based on the phase difference detected by the phase difference detection unit 12, the reset unit 13 inputs a reset signal to the demodulation circuit 20 and resets it.

  According to the present embodiment, it is possible to determine whether or not erroneous pull-in has been performed with sufficient accuracy.

DESCRIPTION OF SYMBOLS 100 Judgment system 110 Frame synchronization circuit 120 Error attraction judgment circuit 130 Reset signal generation circuit 200 Demodulation circuit 210 Quadrature demodulator 220 Oscillator 230 AD converter 240 1st adjustment circuit 250 Carrier recovery circuit 260 2nd adjustment circuit 270 Equalizer 301, 303, 305, 307, 309, 311 Ich signal 302, 304, 306, 308, 310, 312 Qch signal

Claims (7)

Synchronization determination means for determining whether or not the demodulated signal demodulated by the demodulation circuit and the reference signal are synchronized, and
A phase difference detection means for detecting a phase difference between the test signal based on the input signal and the reference signal when the synchronization determination means determines that the demodulated signal and the reference signal are synchronized;
A synchronization determination system comprising: reset means for inputting a reset signal to the demodulation circuit to reset based on the phase difference detected by the phase difference detection means. The synchronization determination system according to claim 1, wherein the reset unit inputs the reset signal to the demodulation circuit when the phase difference detected by the phase difference detection unit is equal to or greater than a predetermined value. The phase difference detection means receives the test signal from a plurality of circuits included in the demodulation circuit, respectively.
When the phase difference between the test signal and the reference signal is greater than or equal to the predetermined value set in advance according to each of the plurality of circuits from which the test signal is input, The synchronization determination system according to claim 2, wherein the reset signal is input to the demodulation circuit. The reset unit inputs the reset signal to the demodulation circuit when the synchronization determination unit determines that the demodulated signal and the reference signal are not synchronized. The synchronization determination system according to the above. 5. A failure signal output unit that outputs a device failure signal indicating that an abnormality has occurred in the demodulation circuit when the reset unit outputs the reset signal a predetermined number of times or more. 5. The synchronization determination system according to the above. The synchronization determination system according to any one of claims 1 to 5,
A communication system comprising the demodulation circuit. A synchronization determination step for determining whether or not the demodulated signal demodulated by the demodulation circuit and the reference signal are synchronized, and
A phase difference detection step of detecting a phase difference between the test signal based on the input signal and the reference signal when it is determined in the synchronization determination step that the demodulated signal and the reference signal are synchronized;
A synchronization determination method comprising: a reset step of inputting a reset signal to the demodulation circuit to reset based on the phase difference detected in the phase difference detection step.

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