JP2000278244A - Receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a receiver that can prevent setting of an erroneous parameter even when a received TMCC(transmission and multiplexing configuration control) signal has an error due to a deteriorated reception environment. SOLUTION: A count down signal from a count down generating circuit 16 is inserted to a TMCC signal outputted from a TMCC mask circuit 18, and the count down signal is forcibly set to a usual value '15' because an error flag is set to '1' in the case that the received TMCC signal has an error due to fading or the like. When the error flag is set to '0', a count down signal that is cyclicly decremented by one each for each input of a frame pulse from '15' until '0', can be obtained. Thus, even when an error is caused in the received TMCC signal due to fading or the like, mis-setting of a parameter to the receiver can be prevented and the setting can be restored to a regular value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver, and more particularly to a receiver for receiving a TMCC signal in a terrestrial digital broadcast wave.

[0002]

2. Description of the Related Art Orthogonal frequency division multiplexing (OFDM)
In digital terrestrial broadcasting that transmits and receives digital broadcast waves of the onal Frequency Division Multiplex (DM) system, parameters such as the modulation method, convolutional coding rate, and time interleave depth of the digital broadcast wave are set in TMCC (Transmission).
and Multiplexing Configuration Control) information is superimposed on the OFDM broadcast signal and broadcast. On the receiving side, parameters necessary for demodulation are obtained from the TMCC signal separated from the received signal, and the receiving device is set to an operation mode corresponding to the parameters.

The above-mentioned TMCC signal is a 204-bit signal including a synchronization signal, a segment format identification unit, TMCC information, and parity bits, and is transmitted after being allocated to at least one OFDM signal after being DBPSK-modulated. Here, for example, the 102-bit TMCC information in the above-described TMCC signal includes a transmission parameter switching index, that is, a countdown signal for switching transmission parameters, together with the various parameters described above. Then, each parameter is decremented by one for each frame from 15 frames before switching, and various parameters are switched at the timing when the value becomes 0.

[0004]

However, if the receiving device for receiving the terrestrial digital broadcasting wave is installed in a place where the receiving condition is not good due to fading or the like or moves, the TMCC signal is correctly demodulated. Without
As a result, there is a problem that parameters may be erroneously changed, or the receiving apparatus may be set to a parameter different from the parameter set on the transmitting side, and reception may be disabled.

[0005] The present invention has been made in view of the above points,
It is an object of the present invention to provide a receiving apparatus capable of preventing setting of erroneous parameters even when an error occurs in a received TMCC signal due to a poor reception environment.

It is another object of the present invention to provide a receiving apparatus capable of performing a recovery operation even when a TMCC signal cannot be received.

[0007]

According to the present invention, there is provided a digital information signal comprising:
Receives the TMCC signal synchronized with the frame, and
When the countdown signal in the C signal reaches a predetermined value,
In a receiver for setting each circuit to information necessary for demodulation in a TMCC signal, an error correction unit for correcting an error of the TMCC signal and outputting an error flag indicating presence or absence of an error, and synchronizing with a frame from the TMCC signal Based on a frame synchronization unit that detects a synchronization signal and generates and outputs a frame pulse, and based on the frame pulse and the received TMCC signal and error flag from the error correction unit, when the error flag has a value indicating that there is an error, the received TMCC signal A normal value is output regardless of the value of, and when the error flag is a value indicating no error, the down-count value that cycles down from the normal value to a predetermined value by counting down every time a frame pulse is input is calculated. The output countdown signal generation means and the countdown signal from the countdown signal generation means are received from the error correction unit. Insert instead of down signal in TMCC signal is obtained by a structure having an insertion circuit for outputting a received TMCC signal.

[0008] Here, the countdown signal generating means includes a frame pulse and a TMCC received from an error correction unit.
When a signal and an error flag are received as inputs and the error flag is a value indicating that there is an error, a normal value is output regardless of the value in the received TMCC signal, and when the error flag is a value indicating that there is no error, and When the countdown signal in the received TMCC signal is a value indicating a normal value, the countdown signal is counted down every time a frame pulse is input, and a downcount value circulating from the normal value to a predetermined value is output. When the value indicates no error and the received TMC
When the countdown signal in the C signal has a value other than the normal value, the value of the countdown signal in the received TMCC signal is output.

The countdown signal generating means of the present invention receives the frame pulse, the received TMCC signal from the error correction section and the error flag as inputs, and, when the error flag has a value indicating no error, receives the received TCC signal.
Detect and output countdown signal in MCC signal,
If the error flag has a value indicating that there is an error, the reception TMC
A countdown detection circuit that outputs a normal value irrespective of the value in the C signal, a frame pulse, an output signal of the countdown detection circuit and an error flag are received as inputs, and when the error flag is a value indicating no error, the frame pulse is output. Each time is input, a down-count value that circulates from a normal value to a predetermined value is output, and when the error flag is a value indicating an error, a count-down generation circuit that outputs a normal value is output. It is characterized by becoming.

The countdown generation circuit has a built-in downcounter that counts down by one with a frame pulse. When the error flag has a value indicating no error, a normal value is input from the countdown detection circuit. In this case, the down counter counts down every time a frame pulse is input and outputs a down count value that circulates from a normal value to a predetermined value from the down counter. Regardless of the value, the normal value is forcibly output, and when the error flag changes from an error to a value indicating no error, the down counter is set to the value of the received countdown signal input from the countdown detection circuit. And

Further, the digital information signal received in the present invention is an orthogonal frequency division multiplex signal composed of a large number of carrier waves, and the TMCC signal is modulated by a predetermined modulation method and assigned to two or more of the large number of carrier waves. The received TMCC is transmitted by a majority decision from a plurality of TMCC signals obtained by demodulating the
It has a majority decision unit for determining a signal and outputting the signal to the error correction unit.

Also, the present invention relates to an output circuit
When the signal and the error flag from the error correction unit are received as inputs and the error flag has a value indicating that there is an error, the output TMCC signal of the insertion circuit is not output, and the previous time when the error flag has a value indicating that there is no error is output. And a TMCC mask circuit for outputting the output TMCC signal of the insertion circuit.

According to the present invention, TMC is performed by fading or the like.
When an error occurs in the C signal, the countdown signal in the TMCC signal is forcibly set to a normal value different from a predetermined value when each circuit is set to information necessary for demodulation.

Further, according to the present invention, even if the countdown signal cannot be received when the countdown signal has a predetermined value for setting each circuit to the information necessary for demodulation due to fading or the like, the signal can be normally received thereafter and the error flag is set. When the value indicates no error, the predetermined value can be output by counting down every time a frame pulse is input.

[0015]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of a receiving apparatus according to the present invention, and FIG. 2 is a timing chart for explaining the operation of FIG. The embodiment shown in FIG. 1 is a part of the terrestrial digital broadcast wave receiver T
An MCC signal receiving unit, and a DBSK demodulation circuit 1
1, the TMCC majority decision unit 12, the frame synchronization unit 13,
TMCC error correction unit 14, countdown detection circuit 1
5, a countdown generation circuit 16, a countdown insertion circuit, and a TMCC mask circuit 17.

An OFDM signal for digital terrestrial broadcasting is
Each of the signals is received by a receiving unit (not shown), and further decoded using a known fast Fourier transform circuit (FFT circuit).
Bit Ich data (in-phase data) and Qch data (quadrature data) are supplied to the DBPSK demodulation circuit 11, where the current input data and data one symbol before are converted to s.
The data subjected to the in / cos conversion is subjected to complex multiplication and differential demodulation. In digital terrestrial broadcasting, the TMCC signal is assigned data on the I axis and is DBPSK modulated, so that only the TMCC signal is differentially demodulated normally, and the data after the differential demodulation is a 12-bit Ich data. Only the amplitude component is supplied to the TMCC majority decision unit 12 and the frame synchronization unit 13, respectively.

The TMCC majority judging unit 12 makes a majority decision on the amplitude data after differential demodulation of the carrier wave allocated to the TMCC signal transmission which exists in a large number in the same symbol, and corrects the amplitude data having the majority value by the TMCC error correction. Input to the unit 14. On the other hand, as described above, the TMCC signal includes the synchronization signal, the segment format identification unit, the TMCC information, and the parity bit, and the synchronization signal is synchronized with the frame.
The synchronization signal inserted into the signal is detected, and a frame pulse indicating the beginning of the frame is generated.

The TMCC error correction unit 14 receives the TMCC data from the TMCC majority decision unit 12 and the frame pulse shown in FIG.
Error correction is performed using the parity included in the TMCC signal. The TMCC error correction section 14 corrects the error-free TMCC data without any error, and supplies the TMCC data to the countdown detection circuit 15 and the countdown insertion circuit 17 serially. Also, TM
When the CC error correction unit 14 cannot correct the error,
When a normal value is output at "1", an error flag which is "0" is generated and output to the countdown detection circuit 15 and the countdown generation circuit 16, respectively.

The countdown detection circuit 15 is provided with a TMCC
The 4-bit reception countdown signal multiplexed from the synchronization signal position in the TMCC data serially input from the error correction unit 14 to a predetermined bit position is
If the error is detected with reference to the frame pulse from the frame synchronization unit 13 and the error flag from the TMCC error correction unit 14 is "0", the detected reception countdown signal is serially output as it is, and the error flag is set to "1". If so, a countdown signal of "15" (4 bits all "1"), which is a normal value, is forcibly output in place of the reception countdown signal.

Here, the countdown signal in the TMCC signal is normally set to a value of "15", but only when the parameter is switched on the transmission side, the countdown signal is decremented by 1 for every 15 frames before switching. Value and
After the value is “0”, the frame returns to “15” and is received with a new transmission parameter switched from the frame returned to “15”.

The countdown generation circuit 16 receives a detection countdown signal serially input from the countdown detection circuit 15, a frame pulse from the frame synchronization section 13, and an error flag from the TMCC error correction section 14 as inputs. The flag is “0” and
When the value of the detection countdown signal is the normal value “15”, every time a frame pulse is input from the built-in 4-bit down counter, the countdown signal is counted down from the normal value “15” by one, and becomes “0”. After that, returning to "15" is repeated, and a 4-bit value circulating around the value from "15" to "0" is serially output.

When the error flag is "0" and the value of the detected countdown signal changes to a value different from the normal value, the countdown generation circuit 16 sets this value in the built-in down counter. From the next frame, a value that counts down by one each time a frame pulse is input is output from the built-in down counter from the next frame, regardless of the value of the error flag, but the error flag is “1”. At this time, the detection countdown signal value "15" from the countdown detection circuit 15 is forcibly output regardless of the value of the built-in downcounter.

Therefore, for example, the reception countdown signal input to the countdown detection circuit 15 is shown in FIG.
And the error flag changes as shown in FIG. 4D, the error flag is “0” and the reception countdown signal is the normal value “15” before time t1. From the countdown generation circuit 16
Outputs a countdown signal whose value decreases by one each time a frame pulse is input, as shown in FIG.

Subsequently, the error flag is changed from time t1 to t2.
During the period "1", the countdown generation circuit 16
Outputs the normal value "15" output from the countdown detection circuit 15 irrespective of the value of the built-in down counter as shown in FIG.
Also when the error flag is "1" from 3 to time t4, the output signal of the countdown generation circuit 16 is set to the normal value "15" as shown in FIG.

When the error flag changes to "0" at time t2, the countdown generating circuit 16 outputs the received countdown signal value "12" output from the countdown detection circuit 15 shown in FIG. Since it is set in the counter, every time a frame pulse is input from time t2, as shown in FIG.
A countdown signal of a value to be counted down by 1 is output from the countdown generation circuit 16. on the other hand,
When the error flag changes to “0” at time t4, the value of the received countdown signal is the normal value “15”, and the countdown generation circuit 16 outputs the output value “11” of the built-in down counter at that time. Output as is.

The countdown signal output from the countdown generation circuit 16 is supplied to a countdown insertion circuit 17.
After being replaced with a countdown signal in the TMCC signal input from the TMCC error correction unit 14, the signal is supplied to the TMCC mask circuit 18. TMC
The C mask circuit 18 looks at the error flag output from the TMCC error correction unit 14 and updates the TMCC signal to be output when there is an error in the current TMCC so that the receiver does not operate with an incorrect reception parameter. Instead, the previously output TMCC signal is output again. This output TMCC signal is supplied to a required circuit section in the receiver.

As described above, in this embodiment, the TMCC
The countdown signal from the countdown generation circuit 16 is inserted in the TMCC signal output from the mask circuit 18. The countdown signal is set to "1" when an error occurs in the received TMCC signal due to fading or the like. Therefore, the value is forcibly set to the normal value "15". Therefore, the setting of the parameters of the receiver depends on the value of the countdown signal in the TMCC signal.
Since it is performed when it becomes 0 ", even if an error occurs in the received TMCC signal due to fading or the like, it is possible to prevent the parameters of the receiver from being erroneously changed.

In this embodiment, even if the countdown signal having the value "0" cannot be received by chance due to fading or the like, the error flag is "0" and the received countdown signal has the normal value "15". In the case of, a countdown signal that counts down by one every frame pulse input is output, and the value of the countdown signal eventually becomes “0”. Can be set as a parameter and can perform a recovery operation.

When the error flag is "0" and the value of the detection countdown signal is the normal value "15", 1
The parameter setting operation is performed every five frames, but since the parameters are the same as before,
There is no erroneous parameter setting.

[0030]

As described above, according to the present invention,
When an error occurs in the TMCC signal due to fading or the like, the countdown signal in the TMCC signal is forcibly set to a normal value different from a predetermined value when setting each circuit to information necessary for demodulation. Therefore, it is possible to prevent erroneous setting of parameters of the receiving apparatus when an error occurs in the TMCC signal due to fading or the like.

Further, according to the present invention, even if the countdown signal cannot be received when the countdown signal has a predetermined value for setting each circuit to the information necessary for demodulation due to fading or the like, it can be normally received thereafter and an error occurs. When the flag becomes a value indicating no error, the count value is counted down every time a frame pulse is input and the above-mentioned predetermined value is output. Can be reset to

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of FIG. 1;

[Explanation of symbols]

 Reference Signs List 11 DBPSK demodulation circuit 12 TMCC majority decision unit 13 Frame synchronization unit 14 TMCC error correction unit 15 Countdown detection circuit 16 Countdown generation circuit 17 Countdown insertion circuit 18 TMCC mask circuit

Claims (6)

[Claims] 1. A frame-synchronized TMCC signal multiplexed in a digital information signal is received.
When the countdown signal in the MCC signal has reached a predetermined value, a receiving device that sets each circuit to information necessary for demodulation in the TMCC signal. An error correction unit that outputs a flag; a frame synchronization unit that detects a synchronization signal synchronized with the frame from the TMCC signal and generates and outputs a frame pulse; and a TMC received from the error correction unit and the frame pulse.
Based on the C signal and the error flag, when the error flag is a value indicating that there is an error, a normal value is output regardless of the value in the received TMCC signal, and when the error flag is a value indicating that there is no error, Countdown signal generating means for counting down every time a frame pulse is input and outputting a downcount value circulating from the normal value to the predetermined value; and outputting the countdown signal from the countdown signal generating means to the error. A receiving circuit that inserts a countdown signal in the received TMCC signal from the correction unit in place of the countdown signal and outputs the signal as a received TMCC signal. 2. The method according to claim 1, wherein the countdown signal generating means is configured to receive the frame pulse and a TMCC received from the error correction unit.
A signal and an error flag are received as inputs, and when the error flag is a value indicating that there is an error, a normal value is output regardless of the value in the received TMCC signal, and when the error flag is a value indicating that there is no error. And when the countdown signal in the received TMCC signal is a value indicating the normal value, a downcount value which counts down every time the frame pulse is input and circulates from the normal value to the predetermined value. And when the error flag has a value indicating no error and the countdown signal in the received TMCC signal has a value other than the normal value, the reception T
2. The receiving device according to claim 1, wherein a value of a countdown signal in the MCC signal is output. 3. The countdown signal generating means according to claim 1, wherein said countdown signal generating means is adapted to receive said TMCC from said error correcting unit.
Signal and an error flag as inputs, when the error flag is a value indicating no error, a countdown signal in the received TMCC signal is detected and output, and when the error flag is a value indicating an error, A countdown detection circuit that outputs a normal value irrespective of a value in a received TMCC signal, and receives as input the frame pulse, an output signal of the countdown detection circuit, and an error flag,
When the error flag is a value indicating that there is no error, a down count is performed each time the frame pulse is input, and a down count value that circulates from the normal value to the predetermined value is output. 2. The receiving apparatus according to claim 1, further comprising a countdown generating circuit that outputs the normal value when the value indicates an error. 4. The countdown generation circuit has a built-in downcounter that counts down by one with the frame pulse, and when the error flag has a value indicating no error, and when the normal value is detected from the countdown detection circuit. When input, the down counter counts down each time the frame pulse is input and outputs a down count value circulating from the normal value to the predetermined value from the down counter, and the error flag indicates that there is an error. When the value indicates, the normal value is forcibly output regardless of the value of the down counter, and when the error flag changes from a value indicating an error to a value indicating no error, the value of the down counter is changed from the countdown detection circuit. 4. The receiving apparatus according to claim 3, wherein the value is set to a value of an input reception countdown signal. . 5. The digital information signal is an orthogonal frequency division multiplex signal composed of a plurality of carriers, and the TMCC
The signal is modulated by a predetermined modulation scheme and transmitted on two or more assigned carriers of the plurality of carriers, and a plurality of TMCCs obtained by demodulating the assigned carriers are obtained.
The receiving apparatus according to claim 1, further comprising a majority decision unit that determines a received TMCC signal from the signal by majority decision and outputs the signal to the error correction unit. 6. An output TMCC signal of the insertion circuit is received as an input when the output flag of the insertion circuit and an error flag from the error correction unit are indicated. 2. The receiving apparatus according to claim 1, further comprising a TMCC mask circuit that outputs a previous TMCC signal output from the insertion circuit when the error flag has a value indicating no error.