JP2010074506A - Clock regeneration circuit, demodulation circuit, receiving device, wireless communication system, and method of operating clock regeneration circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock regeneration circuit which suppresses deterioration in quality of a received signal even if the distances from a quadrature demodulator to A/D converters which inputs via an I channel and a Q channel, two orthogonal baseband components, respectively, are different. <P>SOLUTION: A clock regeneration circuit is equipped with: a quadrature demodulator; two A/D converters; a phase detector; a low-pass filter; an oscillator; a C/N estimation circuit which calculates C/N estimated values for output signals of the two A/D converters and allows a phase error of the output signal of the A/D converter corresponding to a channel with a larger C/N estimated value from among the calculated two C/N estimated values be output as a phase error signal of the phase detector; and a phase adjustment circuit which adjusts the phase of the output signal of the A/D converter corresponding to a channel with a smaller C/N estimated value from among the C/N estimated values calculated by the C/N estimation circuit to make it identical to the phase of the output signal of the A/D converter corresponding to the channel with the larger C/N estimated value. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a clock recovery circuit, a demodulation circuit, a receiver, a radio communication system, and an operation method of the clock recovery circuit, and more particularly to a clock recovery circuit used in a demodulation circuit using an orthogonal modulation method.

  In a digital wireless communication system using a quadrature modulation method such as QPSK (Quadrature Phase Shift Keying) or QAM (Quadrature Amplitude Modulation), the demodulator (demodulator) on the receiving side normally demodulates the received signal. A clock recovery circuit that recovers a necessary clock signal (sampling clock) from a received signal is used (see, for example, Patent Document 1).

  FIG. 3 shows an example of a clock recovery circuit used in a demodulation circuit related to this. In the following description, the modulation method is assumed to be a quadrature modulation method such as QPSK or QAM, and the detection method of the demodulator is assumed to be a synchronous detection method, and in-phase and quadrature which are baseband components orthogonal to each other. The general notation of Ich (I channel) and Qch (Q channel) is used as the notation of (Quadrature) component.

  The clock recovery circuit shown in FIG. 3 includes a quadrature demodulator 1, an oscillator 2, an analog / digital converter for Ich and Qch (hereinafter referred to as A / D (Ich) 3 and A / D (Qch)) 4, A phase detector (also referred to as a phase comparator) (hereinafter referred to as CLK PD) 5, a low-pass filter (hereinafter referred to as CLK LPF) 6 constituting a loop filter, and an oscillator 7 are included. Among these, A / D (Ich) 3, A / D (Qch) 4, CLK PD5, CLK LPF6, and oscillator 7 constitute a PLL (Phase Locked Loop) circuit.

  Based on the local oscillation signal fc102 from the oscillator 2, the quadrature demodulator 1 demodulates the intermediate frequency signal IFIN101 frequency-converted from the high-frequency received signal into two analog signals Ich103 and Qch104 that are orthogonal to each other in the baseband signal. .

  A / D (Ich) 3 samples analog signal Ich 103 demodulated by quadrature demodulator 1 based on sampling clock 114 from oscillator 7 and converts it into digital signal Ich 105. Similarly, A / D (Qch) 4 also samples analog signal Qch 104 demodulated by quadrature demodulator 1 based on sampling clock 114 from oscillator 7 and converts it into digital signal Qch 106.

  CLK PD5 detects the phase errors of digital signals Ich105 and Qch106 converted by A / D (Ich) 3 and A / D (Qch) 4, respectively. CLK PD5 is a sampling phase at A / D (Ich) 3 and A / D (Qch) 4 by detecting Zero-Cross (zero cross) in an eye pattern (eye diagram) as shown in FIG. The deviation from the optimum point (eye opening), that is, the phase error is detected, and the phase error signal 112 is output.

  FIG. 4 shows an example of a method for detecting a phase error in CLK PD5. If the polarities of (1) and (3) are different at the sampling points (1) to (3) corresponding to the eye opening shown in the figure, the phase error from the eye opening can be detected. That is, the phase information detection condition is that the polarities of (1) and (3) are opposite. If this condition is satisfied, and the polarities of (2) and (3) match, the phase is delayed, and if the polarities of (2) and (3) do not match, the phase advance etc. A phase error from the opening can be detected.

  The CLK LPF 6 removes a high frequency component from the phase error signal 112 output from the CLK PD 5 and outputs a phase error integration signal 113.

The oscillator 7 supplies a clock having a frequency corresponding to the value of the phase error integration signal 113 to the A / D (Ich) 3 and A / D (Qch) 4 as the sampling clock 114, respectively.
JP 7-226781 A

  In the related art clock recovery circuit described above, in order to detect the phase error in CLK PD5, it is necessary to satisfy the phase information detection condition shown in FIG. 4, and therefore it is not always possible to detect the phase error. Absent. Therefore, in the CLK PD 5, the channel that satisfies the phase detection condition among the Ich 103 and the Qch 104 is always selected and output as the phase error signal 112. Therefore, in the clock recovery circuit, two PLLs, that is, a PLL composed of A / D (Ich) 3-CLK PD5-CLK LPF6-oscillator 7 on the Ich side, A / D (Qch) 4-CLK on the Qch side. Each PLL comprised of PD5-CLK LPF6-oscillator 7 existed.

  In this case, if the distance from the quadrature demodulator 1 to A / D (Ich) 3 and the distance from the quadrature demodulator 1 to A / D (Qch) 4 are substantially the same, the eye openings of Ich 103 and Qch 104 Are substantially the same in phase, and thus operate as a PLL circuit without any problem. However, when the distance from the quadrature demodulator 1 to A / D (Ich) 3 and the distance from the quadrature demodulator 1 to A / D (Qch) 4 are different, there is an electrical connection between the Ich 103 and the Qch 104. A length difference will occur.

  FIG. 5 shows the eye patterns of the input waveforms of A / D (Ich) 3 and A / D (Qch) 4 when there is an electrical length difference between Ich 103 and Qch 104, and (a) shows the phase of Qch. In the case of advance, (b) corresponds to the case where the phase of Qch is delayed. As shown in FIGS. 4A and 4B, when there is a difference in electrical length between Ich 103 and Qch 104, the point at which the signal converges (hereinafter, the eye opens) differs between Ich 103 and Qch 104. As a result, the eye openings of Ich 103 and Qch 104 are shifted, and therefore, A / D (Ich) 3 and A / D (Qch) 4 can sample Ich 103 and Qch 104 at their optimum points. However, there was a problem that the quality of the received signal deteriorated.

  The present invention solves such a problem, and even when the distance from the quadrature demodulator to the A / D converter that receives two baseband components I and Q, which are orthogonal to each other, is different, An object of the present invention is to provide a clock recovery circuit, a demodulation circuit, and a wireless communication system that can suppress quality degradation.

  To achieve the above object, a clock recovery circuit according to the present invention includes a quadrature demodulator that demodulates I and Q channels, which are baseband components orthogonal to each other, from a received signal, and the I and Q channels based on a sampling clock. Two A / D (Analog to Digital) converters that respectively convert to digital signals, a phase detector that detects a phase error in the output signals of the two A / D converters, and the phase detector A low-pass filter that removes high-frequency components from the phase error signal and outputs a phase error integrated signal, and a clock having a frequency corresponding to the value of the phase error integrated signal is output to the two A / D converters as the sampling clock. C / N (Carrier to Noise) estimates of the output signals of the oscillator and the two A / D converters are obtained respectively. A C / N estimation circuit that outputs a phase error of an output signal of an A / D converter corresponding to a channel having a high C / N estimation value of two C / N estimation values as a phase error signal of the phase detector; The phase of the output signal of the A / D converter corresponding to the channel with the low C / N estimation value obtained by the C / N estimation circuit is set to the phase of the A / D converter corresponding to the channel with the high C / N estimation value. And a phase adjustment circuit that adjusts to match the phase of the output signal.

  A demodulation circuit according to the present invention includes the clock recovery circuit described above.

  A receiver according to the present invention includes the demodulation circuit described above.

  A radio communication system according to the present invention includes the receiver described above.

  In the operation method of the clock recovery circuit according to the present invention, the quadrature demodulator demodulates the I and Q channels, which are baseband components orthogonal to each other, from the received signal, and two A / D (Analog to Digital) converters, The I and Q channels are each converted into a digital signal based on a sampling clock, a phase detector detects a phase error between the output signals of the two A / D converters, and a low-pass filter is converted by the phase detector. A high frequency component is removed from the detected phase error signal to output a phase error integration signal, and the oscillator uses a clock having a frequency corresponding to the value of the phase error integration signal as the sampling clock. And the C / N estimation circuit obtains C / N (Carrier to Noise) estimated values of the output signals of the two A / D converters, respectively. The phase error of the output signal of the A / D converter corresponding to the channel having the higher C / N estimated value of the two C / N estimated values is output as the phase error signal of the phase detector. The phase of the output signal of the A / D converter corresponding to the channel with the low C / N estimation value obtained by the C / N estimation circuit is converted into the A / D converter corresponding to the channel with the high C / N estimation value. The output signal is adjusted so as to match the phase of the output signal.

  According to the present invention, even when the distance from an orthogonal demodulator to an A / D converter that receives two I and Q channels, which are two baseband components orthogonal to each other, is different, it is possible to suppress the quality deterioration of the received signal. It is possible to provide a clock recovery circuit, a demodulation circuit, and a wireless communication system that can perform the above.

  Hereinafter, embodiments of a clock recovery circuit, a demodulation circuit, a receiver, a wireless communication system, and an operation method of the clock recovery circuit according to the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a configuration of a clock recovery circuit according to the present embodiment. This clock recovery circuit is applied to a demodulation circuit using a quadrature modulation method such as QPSK or QAM in a receiver of a digital radio communication system. In the following description, as in the related art of FIG. 3 described above, the modulation method is assumed to be a quadrature modulation method such as QPSK or QAM, and the detection method of the demodulator is assumed to be a synchronous detection method. As the notation, general notations such as Ich and Qch are used. Note that the same components as those in FIG. 3 described above will be described with the same reference numerals.

  The clock recovery circuit used in the demodulating circuit shown in FIG. 1 is similar to the related art shown in FIG. 3 described above, and includes a quadrature demodulator 1, an oscillator 2, and two A / Ds, that is, A / D (Ich) 3 and A / D (Qch) 4, CLK PD (phase detector) 5, CLK LPF (low-pass filter) 6 constituting a loop filter, and an oscillator 7. In this embodiment, in addition to these components, a phase adjustment circuit 8 and a C / N (Carrier to Noise ratio) estimation circuit 9 are provided.

  Based on the local oscillation signal fc102 from the oscillator 2, the quadrature demodulator 1 demodulates the intermediate frequency signal IFIN101 frequency-converted from the high frequency received signal into analog signals Ich103 and Qch104 which are baseband components orthogonal to each other. Output.

  A / D (Ich) 3 samples analog signal Ich 103 demodulated by quadrature demodulator 1 based on sampling clock 114 from oscillator 7, converts it to digital signal Ich 105, and outputs it to CLK PD5. Similarly, A / D (Qch) 4 also samples analog signal Qch 104 demodulated by quadrature demodulator 1 based on sampling clock 114 from oscillator 7, converts it to digital signal Qch 106, and outputs it to CLK PD5. .

  The C / N estimation circuit 9 obtains C / N estimation values of the output signals Ich 105 and Qch 106 at the sampling points of A / D (Ich) 3 and A / D (Qch) 4 and compares both C / N estimation values. Then, the channel with the higher C / N estimation value, that is, the higher convergence is output as Ich / Qch selection information 116 to the CLK PD 5 and the phase adjustment circuit 8 respectively.

  CLK PD5 detects the phase errors of digital signals Ich105 and Qch106 converted by A / D (Ich) 3 and A / D (Qch) 4, respectively. CLK PD5 is a sampling phase at A / D (Ich) 3 and A / D (Qch) 4 by detecting Zero-Cross (zero cross) in an eye pattern (eye diagram) as shown in FIG. Deviation from the optimum point (eye opening), that is, a phase error is detected.

  FIG. 4 shows an example of a method for detecting a phase error in CLK PD5. If the polarities of (1) and (3) are different at the sampling points (1) to (3) corresponding to the eye opening shown in the figure, the phase error from the eye opening can be detected. That is, the phase information detection condition is that the polarities of (1) and (3) are opposite. If this condition is satisfied and the polarities of (2) and (3) match, the phase is delayed, and if the polarities of (2) and (3) do not match, the eye opening such as phase advance The phase lag and phase lead from can be detected.

  In this embodiment, the CLK PD 5 detects the phase errors of the digital signals Ich 105 and Qch 106 converted by A / D (Ich) 3 and A / D (Qch) 4, respectively, of which the Ich / Qch selection signal 116 is used. The phase error of the selected channel with the higher estimated C / N value (hereinafter referred to as “selected channel”) is output as the phase error signal 112 of CLK PD5. The CLK PD 5 outputs the phase errors of the Ich 105 and Qch 106 to the phase adjustment circuit 8 as Ich phase information 110 and Qch phase information 111, respectively.

  The phase adjustment circuit 8 adjusts the phase so that the phase of the non-selected channel matches the phase of the selected channel based on the Ich phase information 110 and the Qch phase information 111 output from the CLK PD 5.

  The phase adjustment circuit 8 and the C / N estimation circuit 9 do not operate when the clock recovery circuit is asynchronous. Whether the clock recovery circuit is synchronous or asynchronous is determined by a control system circuit of the demodulation circuit. That is, the phase adjustment circuit 8 and the C / N estimation circuit 9 operate only when the clock recovery circuit of the demodulation circuit is synchronized. The synchronous / asynchronous information of the clock recovery circuit is determined from the DEM CLK SYNC signal 115. The DEM CLK SYNC signal 115 is supplied from a control system circuit (not shown) of the demodulation circuit.

  The CLK LPF 6 removes a high frequency component from the phase error signal 112 output from the CLK PD 5 and outputs a phase error integration signal 113.

  The oscillator 7 supplies a clock having a frequency corresponding to the value of the phase error integration signal 113 to the A / D (Ich) 3 and A / D (Qch) 4 as the sampling clock 114, respectively.

  Next, the overall operation of this embodiment will be described.

  First, the synchronization of the clock is normally established by a clock recovery circuit composed of A / D (Ich) 3, A / D (Qch) 4, CLK PD 5, CLK LPF 6, and oscillator 7. In this embodiment, A phase adjustment circuit 8 and a C / N estimation circuit 9 are newly added and will be described below.

  The input intermediate frequency signal IFIN101 is converted by the oscillator 2 and the quadrature demodulator 1 into analog signals Ich103 and Qch104 which are two baseband signals orthogonal to each other. The converted analog signals Ich103 and Qch104 are converted into digital signals Ich105 and Qch106 by A / D (Ich) 3 and A / D (Qch) 4, respectively. The converted digital signals Ich 105 and Qch 106 are sampled at the A / D (Ich) 3 and A / D (Qch) 4 in the CLK PD 5 by, for example, a method of detecting Zero-Cross as shown in FIG. Deviation from the optimum point (eye opening), that is, a phase error is detected.

  Here, in the clock recovery circuit of the related art shown in FIG. 3 described above, in order to detect the phase error in CLK PD5, it is necessary to satisfy the phase detection condition, so that the phase error can always be detected. Not exclusively. Therefore, in CLK PD5, the one that satisfies the phase detection condition for Ich and Qch is always selected and output as a phase error signal. Therefore, in the clock recovery circuit, there are two PLLs composed of A / D (Ich) 3-CLK PD5-CLK LPF6-oscillator 7 and A / D (Qch) 4-CLK PD5-CLK LPF6-oscillator 7. It was.

  In this case, as described above, if the distance from the quadrature demodulator 1 to A / D (Ich) 3 and the distance from the quadrature demodulator 1 to A / D (Qch) 4 are substantially the same, the Ich and Qch eyes Since the phases of the openings of the first and second apertures are substantially the same, they operate as a PLL circuit without any problem. However, when the distance from the quadrature demodulator 1 to A / D (Ich) 3 and the distance from the quadrature demodulator 1 to A / D (Qch) 4 are different, the above-described FIG. As shown in b), the Ich and Qch eye openings are displaced. For this reason, in A / D (Ich) 3 and A / D (Qch) 4, sampling cannot be performed at the respective optimum points, resulting in deterioration of the received signal.

  In contrast, in the present embodiment, the C / N estimation circuit 9 obtains respective C / N estimation values at the sampling points of A / D (Ich) 3 and A / D (Qch) 4, and Ich and Qch Are compared, and the selected channel with the higher C / N estimated value is output as the Ich / Qch selection signal 116. In CLK PD5, the phase error signal of the selected channel is output as the phase error signal 112 of CLK PD5 by the Ich / Qch selection signal 116 input from the C / N estimation circuit 9. That is, the C / N estimation circuit 9 obtains the convergence level of the output signals of A / D (Ich) 3 and A / D (Qch) 4 so that the higher convergence level (higher C / N estimation value) is obtained. The phase error of the channel is output as the phase error signal of CLK PD5.

  As a result, the CLK PD5 outputs the phase error signal of the selected channel with the higher C / N estimated value as the phase error signal 112 of the CLK PD5 by the Ich / Qch selection signal 116, and based on this, the clock recovery is performed. Operate the circuit. Thus, in the selected channel, sampling is always performed at the point where the eye opens, so that a reception signal with stable quality can be obtained.

  That is, the related art clock recovery circuit shown in FIG. 3 includes an A / D (Ich) 3-CLK PD5-CLK LPF6-oscillator 7 and an A / D (Qch) 4-CLK PD5-CLK LPF6-oscillator 7. Since there are only two PLLs to be provided, the control of the clock recovery circuit is simplified. By selecting two PLLs that existed for Ich and Qch as one, it is possible to reliably sample the selected channel at the point where the eye opens.

  Further, in the present embodiment, the phase adjustment circuit 8 performs control so that the phase of the non-selected channel with the lower C / N estimation value obtained by the C / N estimation circuit 9 matches the phase of the selected channel. . In this case, the phase adjustment circuit 8 adjusts the phase of the non-selected channel so as to match the eye opening of the selected channel based on the Ich phase information 110 and the Qch phase information 111 output by the CLK PD 5. As a result, even non-selected channels can be reliably sampled at the eye opening. In the phase adjustment circuit 8, Ich phase information 110 and Qch phase information 111, which are Ich and Qch phase error signals input from the CLK PD 5, and an Ich / Qch selection signal 116 input from the C / N estimation circuit 9. Based on the above, phase adjustment is performed. An example of phase adjustment is shown below.

  Based on the input Ich / Qch selection signal 116, the phase adjustment circuit 8 determines which of the Ich and Qch is the selected channel or the non-selected channel. It is possible to determine whether the phase of the non-selected channel is advanced or delayed with respect to the selected channel by averaging the phase errors of the selected channel and the non-selected channel at a certain time and comparing the phases with each other. it can. The phase of the non-selected channel can be made closer to the selected channel by delaying the phase when the phase of the non-selected channel is advanced with respect to the selected channel and by moving the phase when the phase is delayed.

  FIG. 2 shows the input waveforms of A / D (Ich) 3 and A / D (Qch) 4 when there is a difference in electrical length between Ich and Qch, and (a) is the phase adjustment as in the related art of FIG. In the case where the circuit 8 and the C / N estimation circuit 9 are not provided, (b) corresponds to the case where the phase adjustment circuit 8 and the C / N estimation circuit 9 according to the present embodiment are provided. In this embodiment, a phase adjustment circuit 8 and a C / N estimation circuit 9 are newly added to the clock recovery circuit, so that the circuit shown in FIG. 2B is compared with the related art shown in FIG. As described above, both Ich and Qch can be sampled at the point where the eye is opened, and the quality of the received signal can be improved.

  Therefore, according to the present embodiment, the distance from the quadrature demodulator 1 to A / D (Ich) 3 and the distance from the quadrature demodulator 1 to A / D (Qch) 4 are different, and the point at which the eye opens is Ich. Even when Qch is different, the phase adjustment circuit 8 and the C / N estimation circuit 9 are newly added to the clock recovery circuit, so that Ich and Qch can be sampled at optimum points (points where the eyes are opened). It becomes possible. As a result, it is possible to prevent the reception signal from deteriorating when the distance from the quadrature demodulator 1 to A / D3 (Ich) is different from the distance from the quadrature demodulator 1 to A / D4 (Qch). Signal quality can be improved.

  Note that the detection method of the demodulator in the present invention assumes a synchronous detection method, but can also be applied to a quasi-synchronous detection method.

  The present invention can be used in a digital radio communication system, a receiver, a demodulation circuit, and a clock recovery circuit using an orthogonal modulation system.

It is a block diagram which shows the structure of the clock reproduction circuit which concerns on embodiment of this invention. It is a figure which shows the input waveform of A / D (Ich) and A / D (Qch) when there is a difference in electrical length between Ich and Qch, and (a) shows a configuration without a phase adjustment circuit and a C / N estimation circuit. The figure which shows the input waveform in a case, (b) is a figure which shows the input waveform in the case of the structure which has a phase adjustment circuit and a C / N estimation circuit. It is a block diagram which shows the structure of the clock reproduction circuit of related technology. It is a figure explaining an example of the method of detecting Zero-Cross. FIG. 7 is a diagram showing input waveforms of A / D (Ich) and A / D (Qch) when there is a difference in electrical length between Ich and Qch, where (a) shows that the phase of Qch is ahead of the phase of Ich. The figure which shows the input waveform in a case, (b) is a figure which shows the input waveform in case the phase of Qch is behind the phase of Ich.

Explanation of symbols

1 Quadrature demodulator 2 Oscillator 3 A / D (Ich) (Ich analog / digital converter)
4 A / D (Qch) (analog / digital converter for Qch)
5 CLK PD (Phase detector)
6 CLK LPF (low pass filter)
7 Oscillator 8 Phase adjustment circuit 9 C / N estimation circuit

Claims (7)

An orthogonal demodulator that demodulates I and Q channels, which are baseband components orthogonal to each other, from a received signal;
Two A / D (Analog to Digital) converters for converting the I and Q channels into digital signals based on a sampling clock;
A phase detector for detecting a phase error between output signals of the two A / D converters;
A low-pass filter that removes high-frequency components from the phase error signal detected by the phase detector and outputs a phase error integrated signal;
As the sampling clock, an oscillator that outputs a clock having a frequency corresponding to the value of the phase error integration signal to each of the two A / D converters,
C / N (Carrier to Noise) estimated values of the output signals of the two A / D converters are respectively obtained, and A corresponding to a channel having a higher C / N estimated value among the obtained two C / N estimated values. A C / N estimation circuit for outputting a phase error of an output signal of the / D converter as a phase error signal of the phase detector;
The phase of the output signal of the A / D converter corresponding to the channel with the low C / N estimation value obtained by the C / N estimation circuit is set to the phase of the A / D converter corresponding to the channel with the high C / N estimation value. A clock recovery circuit comprising: a phase adjustment circuit that adjusts to match the phase of the output signal.   The phase adjustment circuit compares the phase errors of the output signals of the two A / D converters with each other, and the phase of the output signal of the A / D converter corresponding to the channel with the low C / N estimation value is determined. It is determined whether the phase of the output signal of the A / D converter corresponding to the channel having a high C / N estimated value is advanced or delayed, and the channel having the low C / N estimated value is determined according to the determination result. 2. The phase of the output signal of the A / D converter corresponding to the above is delayed or advanced from the phase of the output signal of the A / D converter corresponding to the channel having the higher C / N estimation value. The clock recovery circuit described.   The clock recovery circuit according to claim 1, wherein the C / N estimation circuit and the phase adjustment circuit operate when the clock recovery circuit is synchronized.   A demodulation circuit comprising the clock recovery circuit according to claim 1.   A receiver comprising the demodulation circuit according to claim 4.   A wireless communication system comprising the receiver according to claim 5. An orthogonal demodulator demodulates I and Q channels, which are baseband components orthogonal to each other, from a received signal,
Two A / D (Analog to Digital) converters convert the I and Q channels into digital signals based on a sampling clock,
A phase detector detects a phase error between the output signals of the two A / D converters;
A low-pass filter removes high frequency components from the phase error signal detected by the phase detector and outputs a phase error integrated signal,
An oscillator outputs, as the sampling clock, a clock having a frequency corresponding to the value of the phase error integration signal to each of the two A / D converters,
A C / N estimation circuit obtains C / N (Carrier to Noise) estimated values of the output signals of the two A / D converters, and of the obtained two C / N estimated values, the C / N estimated value The phase error of the output signal of the A / D converter corresponding to the high channel is output as the phase error signal of the phase detector,
The phase adjustment circuit converts the phase of the output signal of the A / D converter corresponding to the channel with the low C / N estimation value obtained by the C / N estimation circuit to A corresponding to the channel with the high C / N estimation value. A method for operating a clock recovery circuit, wherein the clock recovery circuit is adjusted to match the phase of the output signal of the / D converter.

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