JP2016134424A - Method of manufacturing multilayer wiring board - Google Patents

Method of manufacturing multilayer wiring board Download PDF

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JP2016134424A
JP2016134424A JP2015006659A JP2015006659A JP2016134424A JP 2016134424 A JP2016134424 A JP 2016134424A JP 2015006659 A JP2015006659 A JP 2015006659A JP 2015006659 A JP2015006659 A JP 2015006659A JP 2016134424 A JP2016134424 A JP 2016134424A
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substrate
multilayer wiring
wiring board
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JP6447156B2 (en
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久保田 正博
Masahiro Kubota
正博 久保田
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Murata Manufacturing Co Ltd
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  • Production Of Multi-Layered Print Wiring Board (AREA)
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Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a multilayer wiring board, capable of alleviating the occurrence of warps even when the number of laminated layers of wiring layers and insulation layers increases.SOLUTION: In a method of manufacturing a multilayer wiring board, (1) a thin substrate having a thickness of 50 μm or less is adhered to a thick substrate having a thickness of 0.5 mm or more, (2) a conductive paste containing a conductive material is coated by printing, a pattern is formed to the conductive paste having been coated by printing, and thereby a wiring layer comprising a conductor pattern is formed, (3) an insulating paste containing an insulating material is coated on the wiring layer by printing to form an insulation layer, (4) the steps (2) and (3) are repeated a plurality of times, and (5) the thick substrate is peeled off from the thin substrate to obtain a multilayer wiring board including a plurality of the wiring layers and the insulation layers on the thin substrate.SELECTED DRAWING: Figure 5

Description

本発明は、多層配線基板の製造方法に関する。   The present invention relates to a method for manufacturing a multilayer wiring board.

様々な電気機器に使用されている多層配線基板としては、コイル部品、チップインダクタ、コンデンサ、多層LCフィルタ等の電子部品、VCO(Voltage Controlled Oscillator)、PLL(Phase Locked Loop)等の機能モジュール、及び、セラミック多層基板等がある。   As multilayer wiring boards used in various electrical devices, electronic components such as coil components, chip inductors, capacitors, multilayer LC filters, functional modules such as VCO (Voltage Controlled Oscillator), PLL (Phase Locked Loop), and the like And ceramic multilayer substrates.

この多層配線基板の製造方法としては、例えば、アルミナ基板を用意し、その上に導電ペーストを印刷塗布し、パターン形成して配線層を形成し、さらに、ガラスペーストを印刷塗布して絶縁層を形成し、この配線層及び絶縁層の形成を複数回繰り返し、その後、焼成して、多層配線基板を得る製造方法がある(例えば、特許文献1及び3参照。)。   As a method for manufacturing this multilayer wiring board, for example, an alumina substrate is prepared, and a conductive paste is printed and applied thereon, a pattern is formed to form a wiring layer, and a glass paste is further printed and applied to form an insulating layer. There is a manufacturing method in which the formation of the wiring layer and the insulating layer is repeated a plurality of times, followed by firing to obtain a multilayer wiring board (see, for example, Patent Documents 1 and 3).

近年は、これらの多層配線基板について、小型化及び高機能化のためにさらなる多層化が求められている。   In recent years, these multilayer wiring boards have been required to be further multilayered for miniaturization and high functionality.

特開平11−120823号公報Japanese Patent Laid-Open No. 11-120823 特開平4−305996号公報JP-A-4-305996 特開2001−264965号公報JP 2001-264965 A

しかし、上記方法で多層配線基板として、例えばインダクタを製造する場合、高インダクタンス値を得る目的で層数を多くすると、絶縁層のトータル厚みがより厚くなる。このため、多層配線基板全体の厚さを抑えようとするとアルミナ基板の厚みをより薄くする必要がある。トータル厚みを抑えるためにアルミナ基板の厚みが50μm以下になると、積層数が多くなるに従って乾燥後の配線層及び絶縁層を含む全体の反りが大きくなり、積層が困難となる。   However, when an inductor is manufactured as a multilayer wiring board by the above method, for example, if the number of layers is increased for the purpose of obtaining a high inductance value, the total thickness of the insulating layer becomes thicker. For this reason, if it is going to suppress the thickness of the whole multilayer wiring board, it is necessary to make the thickness of the alumina substrate thinner. If the thickness of the alumina substrate is 50 μm or less in order to suppress the total thickness, the overall warpage including the wiring layer and the insulating layer after drying increases as the number of laminations increases, making lamination difficult.

本発明の目的は、配線層及び絶縁層の積層数が多くなっても反りを抑えられる多層配線基板の製造方法を提供することである。   An object of the present invention is to provide a method for manufacturing a multilayer wiring board capable of suppressing warpage even when the number of wiring layers and insulating layers is increased.

本発明に係る多層配線基板の製造方法は、(1)厚さが0.5mm以上の厚基板に厚さが50μm以下の薄基板を接着剤で貼りつけ、
(2)導電性材料を含む導電性ペーストを印刷塗布し、印刷塗布した前記導電性ペーストにパターン形成して導体パターンからなる配線層を形成し、
(3)前記配線層の上に絶縁性材料を含む絶縁性ペーストを印刷塗布して絶縁層を形成し、
(4)上記(2)及び(3)の工程を複数回繰り返し、
(5)前記薄基板から前記厚基板を剥離して、前記薄基板の上に複数の前記配線層及び前記絶縁層を有する多層配線基板を得る。
The manufacturing method of a multilayer wiring board according to the present invention is as follows: (1) A thin substrate with a thickness of 50 μm or less is attached to a thick substrate with a thickness of 0.5 mm or more with an adhesive;
(2) A conductive paste containing a conductive material is printed and applied, and a pattern is formed on the printed conductive paste to form a wiring layer made of a conductor pattern;
(3) An insulating paste containing an insulating material is printed on the wiring layer to form an insulating layer;
(4) The above steps (2) and (3) are repeated a plurality of times,
(5) The thick substrate is peeled from the thin substrate to obtain a multilayer wiring substrate having a plurality of the wiring layers and the insulating layers on the thin substrate.

本発明に係る多層配線基板の製造方法によれば、厚さの厚い厚基板を厚さの薄い薄基板に接着させることで、薄基板上の絶縁層/配線層の積層数が多くなっても、反りが大きくなることなく積層することができる。   According to the method for manufacturing a multilayer wiring board according to the present invention, even if the number of insulating layers / wiring layers stacked on the thin substrate is increased by adhering the thick substrate to the thin substrate. Further, the layers can be stacked without warping.

実施の形態1に係る多層配線基板の製造方法において、薄基板を厚基板に貼り付けた状態を示す概略断面図である。In the manufacturing method of the multilayer wiring board concerning Embodiment 1, it is a schematic sectional view showing the state where the thin board was stuck on the thick board. 実施の形態1に係る多層配線基板の製造方法において、薄基板の上に導電パターンからなる1層目の配線層を形成した状態を示す概略断面図である。In the manufacturing method of the multilayer wiring board concerning Embodiment 1, it is a schematic sectional view showing the state where the 1st wiring layer which consists of a conductive pattern was formed on the thin board. 実施の形態1に係る多層配線基板の製造方法において、1層目の配線層の上に1層目の絶縁層を形成した状態を示す概略断面図である。FIG. 3 is a schematic cross-sectional view showing a state in which a first insulating layer is formed on a first wiring layer in the method for manufacturing a multilayer wiring board according to the first embodiment. 実施の形態1に係る多層配線基板の製造方法において、2層目の配線層と、2層目の絶縁層とを形成した状態を示す概略断面図である。FIG. 5 is a schematic cross-sectional view showing a state in which a second wiring layer and a second insulating layer are formed in the method for manufacturing a multilayer wiring board according to the first embodiment. 実施の形態1に係る多層配線基板の製造方法において、6層目の配線層と、6層目の絶縁層とを形成した状態を示す概略断面図である。5 is a schematic cross-sectional view showing a state in which a sixth wiring layer and a sixth insulating layer are formed in the method for manufacturing a multilayer wiring board according to Embodiment 1. FIG. 実施の形態1に係る多層配線基板の製造方法において、薄基板から厚基板を剥離して得られた、薄基板の上に複数の配線層及び絶縁層を有する多層配線基板の構成を示す概略断面図である。Schematic cross section showing a configuration of a multilayer wiring board having a plurality of wiring layers and an insulating layer on a thin substrate obtained by peeling the thick substrate from the thin substrate in the method for manufacturing a multilayer wiring board according to Embodiment 1 FIG.

第1の態様に係る多層配線基板の製造方法は、(1)膜厚が0.5mm以上の厚基板に膜厚が50μm以下の薄基板を接着剤で貼りつけ、
(2)導電性材料を含む導電性ペーストを印刷塗布し、印刷塗布した前記導電性ペーストにパターン形成して導体パターンからなる配線層を形成し、
(3)前記配線層の上に絶縁性材料を含む絶縁性ペーストを印刷塗布して絶縁層を形成し、
(4)上記(2)及び(3)の工程を複数回繰り返し、
(5)前記薄基板から前記厚基板を剥離して、前記薄基板の上に複数の前記配線層及び前記絶縁層を有する多層配線基板を得る。
The manufacturing method of the multilayer wiring board which concerns on a 1st aspect attaches the thin board | substrate with a film thickness of 50 micrometers or less to the thick board | substrate with a film thickness of (1) 0.5 mm or more with an adhesive agent,
(2) A conductive paste containing a conductive material is printed and applied, and a pattern is formed on the printed conductive paste to form a wiring layer made of a conductor pattern;
(3) An insulating paste containing an insulating material is printed on the wiring layer to form an insulating layer;
(4) The above steps (2) and (3) are repeated a plurality of times,
(5) The thick substrate is peeled from the thin substrate to obtain a multilayer wiring substrate having a plurality of the wiring layers and the insulating layers on the thin substrate.

第2の態様に係る多層配線基板の製造方法は、上記第1の態様において、前記(1)の前記厚基板に前記薄基板を貼り付ける工程において、加熱によって焼失又は接着力を失う接着剤で前記厚基板に前記薄基板を貼り付け、
前記(5)の前記薄基板から前記厚基板を剥離する工程では、積層した前記配線層及び前記絶縁層を乾燥させた後に、加熱して前記接着剤を焼失又は接着力を失わせて、前記薄基板から前記厚基板を剥離させてもよい。
The method for manufacturing a multilayer wiring board according to a second aspect is the adhesive according to the first aspect, wherein the adhesive loses its adhesive strength or is lost by heating in the step of attaching the thin board to the thick board in (1). Affixing the thin substrate to the thick substrate,
In the step of peeling the thick substrate from the thin substrate of (5), after drying the laminated wiring layer and the insulating layer, the adhesive is burned out or the adhesive force is lost, The thick substrate may be peeled from the thin substrate.

第3の態様に係る多層配線基板の製造方法は、上記第1又は第2の態様において、前記絶縁性ペーストは、ガラスペーストからなってもよい。   In the method for manufacturing a multilayer wiring board according to a third aspect, in the first or second aspect, the insulating paste may be made of a glass paste.

第4の態様に係る多層配線基板の製造方法は、上記第1から第3のいずれかの態様において、前記薄基板及び前記厚基板は、アルミナ基板であってもよい。   In the method for manufacturing a multilayer wiring board according to a fourth aspect, in any one of the first to third aspects, the thin substrate and the thick substrate may be an alumina substrate.

第5の態様に係る多層配線基板は、厚さが50μm以下の薄基板と、
導体パターンからなる配線層と、
前記配線層の上に設けられ、絶縁性材料からなる絶縁層と、
を備え、
前記薄基板の上に、複数組の前記配線層と前記絶縁層とを有する。
A multilayer wiring board according to a fifth aspect includes a thin board having a thickness of 50 μm or less,
A wiring layer comprising a conductor pattern;
An insulating layer provided on the wiring layer and made of an insulating material;
With
A plurality of sets of the wiring layer and the insulating layer are provided on the thin substrate.

第6の態様に係る多層配線基板は、上記第5の態様において、前記薄基板は、アルミナ基板であってもよい。   In the multilayer wiring board according to a sixth aspect, in the fifth aspect, the thin substrate may be an alumina substrate.

第7の態様に係る多層配線基板は、上記第5又は第6の態様において、前記多層配線基板は、コイル部品を構成してもよい。   In the multilayer wiring board according to a seventh aspect, in the fifth or sixth aspect, the multilayer wiring board may constitute a coil component.

以下に実施の形態に係る多層配線基板の製造方法について、添付図面を用いて説明する。なお、図面において、実質的に同一の部材には同一の符号を付している。   A method for manufacturing a multilayer wiring board according to an embodiment will be described below with reference to the accompanying drawings. In the drawings, substantially the same members are denoted by the same reference numerals.

(実施の形態1)
<多層配線基板の製造方法>
実施の形態1に係る多層配線基板の製造方法は、以下の工程を含む。
(1)厚さが0.5mm以上の厚基板1に厚さが50μm以下の薄基板2を接着剤で貼りつける(図1)。
(2)導電性材料を含む導電性ペーストを印刷塗布し、印刷塗布した導電性ペーストにパターン形成して導体パターンからなる配線層3aを形成する(図2)。
(3)配線層3aの上に絶縁性材料を含む絶縁性ペーストを印刷塗布して絶縁層4aを形成する(図3)。
(4)上記(2)及び(3)の工程を複数回繰り返して複数の配線層3a、3b、3c、3d、3e、3f/絶縁層4a、4b、4c、4d、4e、4fを積層する(図4、図5)。図4は、2層目の配線層3b/絶縁層4bまでを形成した状態を示す概略断面図であり、図5は、6層目の配線層3f/絶縁層4fまでを形成した状態を示す概略断面図である。
(5)薄基板2から厚基板1を剥離して、薄基板2の上に複数の配線層3a、3b、3c、3d、3e、3f及び絶縁層4a、4b、4c、4d、4e、4fを有する多層配線基板10を得る(図6)。
(Embodiment 1)
<Manufacturing method of multilayer wiring board>
The method for manufacturing a multilayer wiring board according to the first embodiment includes the following steps.
(1) A thin substrate 2 having a thickness of 50 μm or less is attached to a thick substrate 1 having a thickness of 0.5 mm or more with an adhesive (FIG. 1).
(2) A conductive paste containing a conductive material is printed and applied, and a pattern is formed on the printed conductive paste to form a wiring layer 3a composed of a conductor pattern (FIG. 2).
(3) An insulating paste containing an insulating material is printed on the wiring layer 3a to form the insulating layer 4a (FIG. 3).
(4) The steps (2) and (3) are repeated a plurality of times to laminate a plurality of wiring layers 3a, 3b, 3c, 3d, 3e, 3f / insulating layers 4a, 4b, 4c, 4d, 4e, 4f. (FIGS. 4 and 5). FIG. 4 is a schematic cross-sectional view showing a state where up to the second wiring layer 3b / insulating layer 4b is formed, and FIG. 5 shows a state where up to the sixth wiring layer 3f / insulating layer 4f is formed. It is a schematic sectional drawing.
(5) The thick substrate 1 is peeled from the thin substrate 2, and a plurality of wiring layers 3a, 3b, 3c, 3d, 3e, 3f and insulating layers 4a, 4b, 4c, 4d, 4e, 4f are formed on the thin substrate 2. A multilayer wiring board 10 having the following is obtained (FIG. 6).

この多層配線基板の製造方法によれば、厚さの厚い厚基板1を厚さの薄い薄基板2に接着させることで、薄基板2上の配線層3a、3b、3c、3d、3e、3f/絶縁層4a、4b、4c、4d、4e、4fの積層数が多くなっても、乾燥時の反りが大きくなることなく積層することができる。具体的には、膜厚が0.5mm以上の厚基板1に膜厚が50μm以下の薄基板2を貼り付けることによって、薄基板2を厚基板1によって下支えできる。これによって、塗布した導電性ペースト及び絶縁性ペーストが乾燥する際に縮もうとする収縮応力に抗することができ、乾燥時の反りの発生を抑えることができる。なお、薄基板2の反りは、4インチ(10.16cm)の長さの薄基板2について、端と中央との厚さの差としての反りが0.5mm以下であることが好ましい。これによって多層配線基板10を真空チャックする際の割れの発生等を抑制できる。   According to this multilayer wiring board manufacturing method, the thick substrate 1 is bonded to the thin substrate 2 so that the wiring layers 3a, 3b, 3c, 3d, 3e, 3f on the thin substrate 2 are bonded. / Even if the number of the insulating layers 4a, 4b, 4c, 4d, 4e, and 4f increases, the insulating layers 4a, 4b, 4c, 4d, 4e, and 4f can be stacked without increasing warpage during drying. Specifically, the thin substrate 2 can be supported by the thick substrate 1 by attaching the thin substrate 2 having a thickness of 50 μm or less to the thick substrate 1 having a thickness of 0.5 mm or more. As a result, the applied conductive paste and insulating paste can resist shrinkage stress that tends to shrink when drying, and the occurrence of warping during drying can be suppressed. The warp of the thin substrate 2 is preferably 0.5 mm or less as a difference in thickness between the end and the center of the thin substrate 2 having a length of 4 inches (10.16 cm). As a result, the occurrence of cracks or the like when the multilayer wiring board 10 is vacuum chucked can be suppressed.

以下に、この多層配線基板の製造方法における各構成要素について説明する。   Below, each component in the manufacturing method of this multilayer wiring board is demonstrated.

<薄基板>
薄基板2としては、厚さ50μm以下の絶縁性の基板、例えば、アルミナ基板、セラミック基板、フェライト等を用いることができる。
<Thin substrate>
As the thin substrate 2, an insulating substrate having a thickness of 50 μm or less, such as an alumina substrate, a ceramic substrate, or ferrite can be used.

<厚基板>
厚基板1としては、厚さ0.5mm以上の基板、例えば、アルミナ基板、セラミック基板等を用いることができる。なお、アルミナ基板、セラミック基板等は一例であって、これに限定されるものではなく、任意の材料からなるものを用いることができる。
<Thick substrate>
As the thick substrate 1, a substrate having a thickness of 0.5 mm or more, for example, an alumina substrate, a ceramic substrate, or the like can be used. In addition, an alumina substrate, a ceramic substrate, etc. are examples, and it is not limited to this, What consists of arbitrary materials can be used.

<接着剤>
接着剤は、厚基板1を薄基板2に接着させることができるものであって、且つ、加熱によって焼失又は接着力を失って剥離するものであればよい。この接着剤としては、例えば、熱硬化性樹脂、熱可塑性樹脂等の樹脂、あるいは、仮止め接着剤(例えば、株式会社ダイセル製のもの(化学工業日報2014年3月31日の記事参照))を用いることができる。
上記のように、厚基板1を薄基板2に貼り付ける接着剤として、加熱(焼成)によって焼失又は接着力を失って剥離するものを用いているので、複数の配線層/絶縁層を積層した後、乾燥後に加熱することによって、厚基板1を薄基板2から剥離させることができる。また、配線層及び絶縁層の焼成と、加熱による厚基板1の剥離とを同時に行った場合には、配線層及び絶縁層の焼成によって溶剤が焼失するので収縮応力が開放される。なお、加熱による厚基板1の剥離後に配線層及び絶縁層の焼成を行ってもよい。
なお、焼成によって厚基板1が薄基板2から剥離するので、個々の配線層、絶縁層の積層ごとに焼成することはできず、全ての配線層/絶縁層を積層した後に焼成する必要がある。
<Adhesive>
Any adhesive may be used as long as it can adhere the thick substrate 1 to the thin substrate 2 and is peeled off by heating or loss of adhesion. As this adhesive, for example, a resin such as a thermosetting resin or a thermoplastic resin, or a temporary fixing adhesive (for example, manufactured by Daicel Corporation (see article on March 31, 2014 in Chemical Industry Daily)) Can be used.
As described above, as the adhesive for attaching the thick substrate 1 to the thin substrate 2, the adhesive that peels off by heating (firing) or loses the adhesive force is used, so a plurality of wiring layers / insulating layers are laminated. Then, the thick substrate 1 can be peeled from the thin substrate 2 by heating after drying. Further, when the wiring layer and the insulating layer are fired and the thick substrate 1 is peeled off by heating at the same time, the shrinkage stress is released because the solvent is burned away by the firing of the wiring layer and the insulating layer. Note that the wiring layer and the insulating layer may be fired after the thick substrate 1 is peeled off by heating.
Since the thick substrate 1 is peeled off from the thin substrate 2 by firing, firing cannot be performed for each wiring layer and insulating layer, and it is necessary to fire after all the wiring layers / insulating layers are stacked. .

<導電性ペースト>
導電性材料を含む導電性ペーストとしては、通常用いられるものであれば使用できる。導電性材料としては、例えば、金、銀、銅、白金、アルミニウム、パラジウム、ニッケル、モリブデン、タングステン等の金属粉末を使用できる。有機溶剤としては、アルコール、トルエン、メチルエチルケトン、アセトン、酢酸エチル、酢酸ビニル、エチルカルビトールアセテート、ジプロピレングリコールモノメチルエーテル等の通常使用される有機溶剤であれば使用できる。導電性ペーストとしては、例えば、金ペースト、銀ペースト、アルミニウムペースト等を用いてもよい。
<Conductive paste>
As a conductive paste containing a conductive material, any conventional paste can be used. As the conductive material, for example, metal powder such as gold, silver, copper, platinum, aluminum, palladium, nickel, molybdenum and tungsten can be used. As the organic solvent, any commonly used organic solvent such as alcohol, toluene, methyl ethyl ketone, acetone, ethyl acetate, vinyl acetate, ethyl carbitol acetate, and dipropylene glycol monomethyl ether can be used. As the conductive paste, for example, a gold paste, a silver paste, an aluminum paste, or the like may be used.

<絶縁性ペースト>
絶縁性材料を含む絶縁性ペーストとしては、通常用いられるものであれば使用できる。
絶縁性材料としては、Al、結晶化ガラス系、ガラス複合系、非ガラス系等の絶縁性セラミック粉末、BaTiO等の誘電体セラミック粉末、ニッケル亜鉛フェライト、ニッケル亜鉛銅フェライト等のフェライト系粉末、RuO、PbRu、BiRu、Mn・Co・Niの複合酸化物等の高抵抗セラミック粉末、PZT等の圧電体セラミック粉末等を使用できる。有機溶剤としては、アルコール、トルエン、メチルエチルケトン、アセトン、酢酸エチル、酢酸ビニル、エチルカルビトールアセテート、ジプロピレングリコールモノメチルエーテル等の通常使用される有機溶剤であれば使用できる。絶縁性ペーストとしては、例えば、アルミナペースト、ガラスペースト等を用いてもよい。
なお、多層配線基板10をコイル部品として使用する場合には、絶縁性ペーストとして低誘電率のガラスペーストが好ましい。
<Insulating paste>
As an insulating paste containing an insulating material, any conventional paste can be used.
Insulating materials include Al 2 O 3 , crystallized glass-based, glass composite-based, non-glass-based insulating ceramic powders, dielectric ceramic powders such as BaTiO 3 , ferrites such as nickel zinc ferrite and nickel zinc copper ferrite A high-resistance ceramic powder such as a composite powder, RuO 2 , Pb 2 Ru 2 O 7 , Bi 2 Ru 2 O 7 , a composite oxide of Mn · Co · Ni, a piezoelectric ceramic powder such as PZT, or the like can be used. As the organic solvent, any commonly used organic solvent such as alcohol, toluene, methyl ethyl ketone, acetone, ethyl acetate, vinyl acetate, ethyl carbitol acetate, and dipropylene glycol monomethyl ether can be used. As the insulating paste, for example, an alumina paste, a glass paste, or the like may be used.
When the multilayer wiring board 10 is used as a coil component, a low dielectric constant glass paste is preferable as the insulating paste.

<多層配線基板>
図6は、薄基板2の上に複数の配線層3a、3b、3c、3d、3e、3f及び絶縁層4a、4b、4c、4d、4e、4fを有する多層配線基板10の構成を示す概略断面図である。この多層配線基板10は、厚さが50μm以下の薄基板2と、導体パターンからなる配線層3a、3b、3c、3d、3e、3fと、配線層3a、3b、3c、3d、3e、3fの上に設けられ、絶縁性材料からなる絶縁層4a、4b、4c、4d、4e、4fと、を備える。また、薄基板2の上に、複数組の配線層3a、3b、3c、3d、3e、3fと絶縁層4a、4b、4c、4d、4e、4fとを有する。
この多層配線基板10は、厚さが50μm以下の薄基板2を有しながら、4インチ(10.16cm)の長さの薄基板2について、端と中央との厚さの差としての反りが0.5mm以下とすることができる。この多層配線基板10は、上記多層配線基板の製造方法によって得られたものであり、厚さの厚い厚基板1を厚さの薄い薄基板2に接着させることで、乾燥時の反りの発生を抑制できたことによる。後述する比較例に見られるように、厚基板1を用いないで、厚さが50μm以下の薄基板2に直接に配線層及び絶縁層を形成した場合には反りが1mm以上となって多層化が困難となる。つまり、厚さが50μm以下の薄基板2を用いた多層配線基板10であって、4インチ(10.16cm)の長さの薄基板2について、端と中央との厚さの差としての反りが0.5mm以下であるものは、上記多層配線基板の製造方法によって製造されたものであると推測される。
<Multilayer wiring board>
FIG. 6 schematically shows a configuration of a multilayer wiring board 10 having a plurality of wiring layers 3a, 3b, 3c, 3d, 3e, and 3f and insulating layers 4a, 4b, 4c, 4d, 4e, and 4f on the thin substrate 2. It is sectional drawing. The multilayer wiring board 10 includes a thin substrate 2 having a thickness of 50 μm or less, wiring layers 3a, 3b, 3c, 3d, 3e, and 3f made of a conductor pattern, and wiring layers 3a, 3b, 3c, 3d, 3e, and 3f. And insulating layers 4a, 4b, 4c, 4d, 4e, and 4f made of an insulating material. On the thin substrate 2, a plurality of sets of wiring layers 3a, 3b, 3c, 3d, 3e, and 3f and insulating layers 4a, 4b, 4c, 4d, 4e, and 4f are provided.
This multilayer wiring board 10 has a thin substrate 2 having a thickness of 50 μm or less, but warps as a difference in thickness between the end and the center of the thin substrate 2 having a length of 4 inches (10.16 cm). It can be 0.5 mm or less. The multilayer wiring board 10 is obtained by the above-described method for manufacturing a multilayer wiring board. The thick substrate 1 is bonded to the thin substrate 2 so that warpage occurs during drying. Because it was able to be suppressed. As seen in the comparative example described later, when the wiring layer and the insulating layer are directly formed on the thin substrate 2 having a thickness of 50 μm or less without using the thick substrate 1, the warp becomes 1 mm or more and becomes multilayered. It becomes difficult. That is, in the multilayer wiring board 10 using the thin substrate 2 having a thickness of 50 μm or less and the thin substrate 2 having a length of 4 inches (10.16 cm), warping as a difference in thickness between the end and the center. If the thickness is 0.5 mm or less, it is presumed that the substrate is manufactured by the method for manufacturing a multilayer wiring board.

(実施例1)
<多層配線基板の製造方法>
以下に、実施例1に係る多層配線基板の製造方法について説明する。
Example 1
<Manufacturing method of multilayer wiring board>
Below, the manufacturing method of the multilayer wiring board based on Example 1 is demonstrated.

(1)感光性ペーストの作製
本実施例において、感光性ペーストの作製に使用する各材料は、以下の材料を用いた。
A.無機粉末
A1.銀粉末:球状、D50:2.0μm
A2.ガラス粉末a:SiO−B−KO系、D50:3.0μm
A3.ガラス粉末b:SiO−B−Li−ZnO−Al系、D50:3.0μm
A4.クォーツ粉末:D50:3.0μm
B.モノマー
B1.モノマーa:ジペンタエリスリトールヘキサアクリレート
B2.モノマーb:エトキシ変性トリメチロールプロパントリアクリレート
C.ポリマー
C1.ポリマーa:メタクリル酸/メタクリル酸メチルを共重合させたのち、メタクリル酸に対して0.2倍モル量のエポキシシクロヘキシルメチルメタクリレートを付加反応させた、エチレン性不飽和2重結合含有アクリル系共重合体。MW=20000、酸価=100mgKOH/g。
C2.ポリマーb:メタクリル酸/メタクリル酸メチルを共重合させたのち、メタクリル酸に対して0.2倍モル量のエポキシエチルベンゼンを付加反応させたアクリル系共重合体。MW=24000、酸価=90mgKOH/g。
D.光重合開始剤
D1.開始剤a:2−メチル−1−[4−(メチルチオ)フェニル]−2−モルフォリノプロパン−1−オン
D2.開始剤b:2,4−ジエチルチオキサントン
D3.開始剤c:エタノン,1−[9−エチル−6−(2−メチルベンゾイル)−9H−カルバゾール−3−イル)−,1−(o−アセチルオキシム)
D4.開始剤d:ビス(2,4,6−トリメチルベンゾイル)−フェニルフォスフィンオキサイド
D5.開始剤e:1−ヒドロキシ−シクロヘキシル−フェニル−ケトン
E.有機溶剤:
E1.有機溶剤a:ペンタメチレングリコール
E2.有機溶剤b:ジプロピレングリコールモノメチルエーテル
F.その他有機成分
F1.分散剤:脂肪族ポリカルボン酸アミン塩(固形分49%)
F2.チクソトロピック剤:ポリアマイド系(固形分70%)
F3.レベリング剤:特殊アクリル系重合物(エチルカルビトールアセテート溶液、固形分50%、SP値8.81)
F4.紫外線吸収剤:アゾ系染料
上記各材料を下記の表1に示す重量比となるように、秤量、混合した。次いで、3本ロールミルによる練肉を行い、感光性導電ペーストと感光性ガラスペーストの試料をそれぞれ得た。
(1) Preparation of photosensitive paste In the present Example, the following materials were used for each material used for preparation of the photosensitive paste.
A. Inorganic powder A1. Silver powder: spherical, D50: 2.0 μm
A2. Glass powder a: SiO 2 —B 2 O 3 —K 2 O system, D50: 3.0 μm
A3. Glass powder b: SiO 2 —B 2 O 3 —Li 2 O 3 —ZnO—Al 2 O 3 system, D50: 3.0 μm
A4. Quartz powder: D50: 3.0 μm
B. Monomer B1. Monomer a: Dipentaerythritol hexaacrylate B2. Monomer b: Ethoxy-modified trimethylolpropane triacrylate C.I. Polymer C1. Polymer a: Ethylenically unsaturated double bond-containing acrylic copolymer obtained by copolymerization of methacrylic acid / methyl methacrylate and then addition reaction of 0.2-fold molar amount of epoxycyclohexylmethyl methacrylate with respect to methacrylic acid Coalescence. MW = 20000, acid value = 100 mg KOH / g.
C2. Polymer b: An acrylic copolymer obtained by copolymerizing methacrylic acid / methyl methacrylate and then adding 0.2 times the molar amount of epoxyethylbenzene to methacrylic acid. MW = 24000, acid value = 90 mg KOH / g.
D. Photoinitiator D1. Initiator a: 2-methyl-1- [4- (methylthio) phenyl] -2-morpholinopropan-1-one D2. Initiator b: 2,4-diethylthioxanthone D3. Initiator c: Ethanone, 1- [9-ethyl-6- (2-methylbenzoyl) -9H-carbazol-3-yl)-, 1- (o-acetyloxime)
D4. Initiator d: bis (2,4,6-trimethylbenzoyl) -phenylphosphine oxide D5. Initiator e: 1-hydroxy-cyclohexyl-phenyl-ketone Organic solvent:
E1. Organic solvent a: pentamethylene glycol E2. Organic solvent b: dipropylene glycol monomethyl ether Other organic components F1. Dispersant: Aliphatic polycarboxylic acid amine salt (solid content 49%)
F2. Thixotropic agent: Polyamide (solid content 70%)
F3. Leveling agent: Special acrylic polymer (ethyl carbitol acetate solution, solid content 50%, SP value 8.81)
F4. Ultraviolet absorber: azo dye The above materials were weighed and mixed so as to have a weight ratio shown in Table 1 below. Next, kneading with a three-roll mill was performed to obtain samples of a photosensitive conductive paste and a photosensitive glass paste, respectively.

Figure 2016134424
Figure 2016134424

(2)厚基板上への薄基板接着
1.5mm厚の4インチアルミナ基板(厚基板)上に加熱硬化型エポキシ樹脂系接着剤を塗布する。その上に、0.03mm厚の4インチアルミナ基板(薄基板)を密着させ、150℃の温度下で1時間硬化させた。
(2) Thin substrate adhesion onto a thick substrate A heat-curable epoxy resin adhesive is applied onto a 1.5 mm thick 4-inch alumina substrate (thick substrate). A 4-inch alumina substrate (thin substrate) having a thickness of 0.03 mm was adhered thereon and cured at a temperature of 150 ° C. for 1 hour.

(3)Ag配線/ガラス層の積層
上記基板上に、感光性Agペーストをスクリーン印刷によって塗布し、これを100℃にて10分間乾燥して、15μm厚の塗膜を形成した。次に、得られた塗膜に露光処理を行った。ここでは、パターン端部に50μm径のパッド部を有するAgパターン(ライン幅/ライン間隔=20μm、2巻コイルパターン)が描画されたマスクを通して、高圧水銀灯からの活性光線を、1200mJ/cmの露光量で照射した。その後、炭酸ナトリウム水溶液による現像処理を行うことにより、パターン端部に50μm径のパッド部を有するAgパターン(ライン幅/ライン間隔=20μm、2巻コイルパターン)を形成した。
次いで、感光性ガラスペーストをスクリーン印刷によって塗布し、これを100℃にて10分間乾燥して、30μm厚の塗膜を形成した。次に、得られた塗膜に露光処理を行った。ここでは、30μm径のビアパターンが描画されたマスクを通して、高圧水銀灯からの活性光線を、100mJ/cmの露光量で照射した。その後、炭酸ナトリウム水溶液による現像処理を行うことにより、前記アルミナ基板上に30μm径のビアパターンを形成した。
上記操作を繰り返すことにより、Ag6層、ガラス6層を有するアルミナ基板を作製した。なお、最下層Agと最上層Agとが導通するよう、適宜、ビアパターンの設計と、露光時のガラスビア部とAgパッド部との位置合わせを行い、最上層Agと最下層Agには外部電極と接続できるような形状とした。なお、各パターンは0.6×0.3mmの中に収まるようにしている。
上記作業を通じて、薄基板の反りは0.5mm以内に収めることができ、Ag層/ガラス層の積層が困難になる事態は生じなかった。
なお、この薄基板の反りとしては、4インチ(10.16cm)の長さの薄基板2について、配線層/絶縁層を積層した側の端部が持ち上がり、積層した側の中央に凹部が生じる。逆に、積層していない側からみると、中央部が端部より持ち上がって凸状になって見える。そこで、薄基板の端と中央との厚さの最大差を測定し、この最大差を薄基板の反りとしている。
(3) Lamination of Ag wiring / glass layer A photosensitive Ag paste was applied on the substrate by screen printing and dried at 100 ° C. for 10 minutes to form a coating film having a thickness of 15 μm. Next, the obtained coating film was exposed. Here, actinic rays from a high-pressure mercury lamp are applied at 1200 mJ / cm 2 through a mask on which an Ag pattern (line width / line interval = 20 μm, 2-winding coil pattern) having a 50 μm-diameter pad at the pattern end is drawn. Irradiated with an exposure dose. Thereafter, an Ag pattern (line width / line interval = 20 μm, 2-winding coil pattern) having a pad portion with a diameter of 50 μm at the pattern end was formed by performing a development treatment with an aqueous sodium carbonate solution.
Next, a photosensitive glass paste was applied by screen printing and dried at 100 ° C. for 10 minutes to form a coating film having a thickness of 30 μm. Next, the obtained coating film was exposed. Here, actinic rays from a high-pressure mercury lamp were irradiated at an exposure amount of 100 mJ / cm 2 through a mask on which a 30 μm diameter via pattern was drawn. Thereafter, a via pattern having a diameter of 30 μm was formed on the alumina substrate by developing with an aqueous sodium carbonate solution.
By repeating the above operation, an alumina substrate having an Ag6 layer and a glass 6 layer was produced. In addition, the via pattern design and the alignment of the glass via portion and the Ag pad portion at the time of exposure are appropriately performed so that the lowermost layer Ag and the uppermost layer Ag are electrically connected, and external electrodes are provided on the uppermost layer Ag and the lowermost layer Ag. It can be connected to the shape. Each pattern is set to be within 0.6 × 0.3 mm.
Through the above operation, the warp of the thin substrate could be kept within 0.5 mm, and there was no situation where the Ag layer / glass layer lamination became difficult.
As for the warp of the thin substrate, with respect to the thin substrate 2 having a length of 4 inches (10.16 cm), the end portion on the side where the wiring layer / insulating layer is laminated is lifted, and a concave portion is formed at the center of the laminated side. . On the contrary, when viewed from the non-laminated side, the central portion is lifted from the end portion and appears convex. Therefore, the maximum difference in thickness between the edge and the center of the thin substrate is measured, and this maximum difference is used as the warp of the thin substrate.

(4)焼成
上記基板に対し、ダイサーにより、厚基板に達しない深さで0.6×0.3mm間隔でカット溝を形成し、各パターンを分離した。なお、ここでは厚基板を切断しないように切断深さを調整したが、個々のチップごとに厚基板を切断してもよい。さらに、脱脂処理を施した後、空気中で850℃で1時間焼成した。これにより、接着剤が焼失して厚基板からカット済み薄基板が分離し、0.6×0.3mmサイズの多層配線基板が形成された。この多層配線基板の両端に外部電極を形成することで、0.6×0.3mmサイズのチップコイルとすることができた。
(4) Firing Cut grooves were formed at intervals of 0.6 × 0.3 mm with a dicer at a depth not reaching the thick substrate with respect to the substrate, and each pattern was separated. Here, the cutting depth is adjusted so as not to cut the thick substrate, but the thick substrate may be cut for each individual chip. Furthermore, after performing a degreasing process, it baked at 850 degreeC in the air for 1 hour. As a result, the adhesive was burned out and the cut thin substrate was separated from the thick substrate, and a 0.6 × 0.3 mm size multilayer wiring substrate was formed. By forming external electrodes on both ends of this multilayer wiring board, a chip coil having a size of 0.6 × 0.3 mm could be obtained.

(比較例)
上記(2)の工程を経ず、(3)の工程について、0.03mm厚の4インチアルミナ基板上に、直接に1層目のAg層と1層目のガラス層の形成後、2層目のAg層の形成のために感光性Agペーストを塗布した。その後、乾燥時に薄基板の端と中央との差としての反りが1mm以上となり、それ以上のAg層及びガラス層の積層が困難となった。
(Comparative example)
After the formation of the first Ag layer and the first glass layer directly on the 0.03 mm-thick 4 inch alumina substrate in the step (3) without passing through the step (2), two layers are formed. A photosensitive Ag paste was applied to form an Ag layer for the eyes. Thereafter, the warp as a difference between the edge and the center of the thin substrate during drying was 1 mm or more, and it was difficult to further laminate the Ag layer and the glass layer.

<作用・効果>
実施例1に係る多層配線基板の製造方法によれば、厚基板を薄基板に接着させることで、薄基板上のガラス絶縁層/配線層の積層数が多くなっても、乾燥時の反りが大きくなることなく積層することができる。これに対して、比較例では、厚基板を薄基板に接着しなかったため、2層目のAg層の形成のためのAgペースト塗布の段階で乾燥時の収縮応力に抗しきれず、薄基板の反りが1mm以上となってそれ以上の積層が困難となった。
<Action and effect>
According to the method for manufacturing a multilayer wiring board according to Example 1, even when the number of laminated glass insulating layers / wiring layers on the thin substrate is increased by adhering the thick substrate to the thin substrate, the warp during drying occurs. Stacking can be performed without increasing the size. On the other hand, in the comparative example, since the thick substrate was not bonded to the thin substrate, the shrinkage stress at the time of drying could not be resisted at the stage of applying the Ag paste for forming the second Ag layer, and the thin substrate The warpage was 1 mm or more, and it was difficult to laminate further.

なお、各実施の形態、各実施例は、例示であり、異なる実施の形態、実施例で示した構成の部分的な置換または組み合わせが可能であることはいうまでもない。本開示においては、前述した様々な実施の形態のうちの任意の実施の形態を適宜組み合わせることを含むものであり、それぞれの実施の形態が有する効果を奏することができる。   In addition, each embodiment and each Example are illustrations, and it cannot be overemphasized that the partial substitution or combination of the structure shown in different embodiment and Example is possible. The present disclosure includes appropriately combining any of the various embodiments described above, and can provide the effects of the respective embodiments.

本発明に係る多層配線基板の製造方法は、配線層/絶縁層を従来より多層化しても反りの発生を抑えることができる。そこで、コイル部品、チップインダクタ、コンデンサ、多層LCフィルタ等の電子部品、VCO(Voltage Controlled Oscillator)、PLL(Phase Locked Loop)等の機能モジュール、及び、セラミック多層基板等を製造するために用いることができる。   The method for manufacturing a multilayer wiring board according to the present invention can suppress the occurrence of warping even if the wiring layer / insulating layer is made multilayer. Therefore, it is used to manufacture electronic components such as coil components, chip inductors, capacitors, multilayer LC filters, functional modules such as VCO (Voltage Controlled Oscillator), PLL (Phase Locked Loop), and ceramic multilayer substrates. it can.

1 厚基板
2 薄基板
3a、3b、3c、3d、3e、3f 配線層
4a、4b、4c、4d、4e、4f 絶縁層
10 多層配線基板
DESCRIPTION OF SYMBOLS 1 Thick board | substrate 2 Thin board | substrates 3a, 3b, 3c, 3d, 3e, 3f Wiring layer 4a, 4b, 4c, 4d, 4e, 4f Insulating layer 10 Multilayer wiring board

Claims (7)

(1)厚さが0.5mm以上の厚基板に厚さが50μm以下の薄基板を接着剤で貼りつけ、
(2)導電性材料を含む導電性ペーストを印刷塗布し、印刷塗布した前記導電性ペーストにパターン形成して導体パターンからなる配線層を形成し、
(3)前記配線層の上に絶縁性材料を含む絶縁性ペーストを印刷塗布して絶縁層を形成し、
(4)上記(2)及び(3)の工程を複数回繰り返し、
(5)前記薄基板から前記厚基板を剥離して、前記薄基板の上に複数の前記配線層及び前記絶縁層を有する多層配線基板を得る、
多層配線基板の製造方法。
(1) A thin substrate with a thickness of 50 μm or less is attached to a thick substrate with a thickness of 0.5 mm or more with an adhesive,
(2) A conductive paste containing a conductive material is printed and applied, and a pattern is formed on the printed conductive paste to form a wiring layer made of a conductor pattern;
(3) An insulating paste containing an insulating material is printed on the wiring layer to form an insulating layer;
(4) The above steps (2) and (3) are repeated a plurality of times,
(5) The thick substrate is peeled from the thin substrate to obtain a multilayer wiring substrate having a plurality of the wiring layers and the insulating layer on the thin substrate.
A method for manufacturing a multilayer wiring board.
前記(1)の前記厚基板に前記薄基板を貼り付ける工程において、加熱によって焼失又は接着力を失う接着剤で前記厚基板に前記薄基板を貼り付け、
前記(5)の前記薄基板から前記厚基板を剥離する工程では、積層した前記配線層及び前記絶縁層を乾燥させた後に、加熱して前記接着剤を焼失又は接着力を失わせて、前記薄基板から前記厚基板を剥離させる、請求項1に記載の多層配線基板の製造方法。
In the step of attaching the thin substrate to the thick substrate of (1), the thin substrate is attached to the thick substrate with an adhesive that burns away or loses adhesive strength by heating,
In the step of peeling the thick substrate from the thin substrate of (5), after drying the laminated wiring layer and the insulating layer, the adhesive is burned out or the adhesive force is lost, The method for manufacturing a multilayer wiring board according to claim 1, wherein the thick substrate is peeled from the thin substrate.
前記絶縁性ペーストは、ガラスペーストからなる、請求項1又は2に記載の多層配線基板の製造方法。   The method for manufacturing a multilayer wiring board according to claim 1, wherein the insulating paste is made of glass paste. 前記薄基板及び前記厚基板は、アルミナ基板である、請求項1から3のいずれか一項に記載の多層配線基板の製造方法。   The method for manufacturing a multilayer wiring board according to claim 1, wherein the thin substrate and the thick substrate are alumina substrates. 厚さが50μm以下の薄基板と、
導体パターンからなる配線層と、
前記配線層の上に設けられ、絶縁性材料からなる絶縁層と、
を備え、
前記薄基板の上に、複数組の前記配線層と前記絶縁層とを有する、多層配線基板。
A thin substrate having a thickness of 50 μm or less;
A wiring layer comprising a conductor pattern;
An insulating layer provided on the wiring layer and made of an insulating material;
With
A multilayer wiring board having a plurality of sets of the wiring layer and the insulating layer on the thin substrate.
前記薄基板は、アルミナ基板である、請求項5に記載の多層配線基板。   The multilayer wiring board according to claim 5, wherein the thin substrate is an alumina substrate. 前記多層配線基板は、コイル部品を構成する、請求項5又は6に記載の多層配線基板。   The multilayer wiring board according to claim 5 or 6, wherein the multilayer wiring board constitutes a coil component.
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WO2019012929A1 (en) * 2017-07-12 2019-01-17 株式会社村田製作所 Composite wiring board and probe card
WO2022186937A1 (en) * 2021-03-04 2022-09-09 Intel Corporation Coreless electronic substrates having embedded inductors

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JP2004273905A (en) * 2003-03-11 2004-09-30 Matsushita Electric Ind Co Ltd Method for manufacturing laminated ceramic electronic component
JP2009238978A (en) * 2008-03-27 2009-10-15 Kyocera Corp Method of manufacturing ceramic substrate

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Publication number Priority date Publication date Assignee Title
WO2019012929A1 (en) * 2017-07-12 2019-01-17 株式会社村田製作所 Composite wiring board and probe card
WO2022186937A1 (en) * 2021-03-04 2022-09-09 Intel Corporation Coreless electronic substrates having embedded inductors

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