JP2016119415A - Semiconductor device and manufacturing method of the same - Google Patents
Semiconductor device and manufacturing method of the same Download PDFInfo
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- JP2016119415A JP2016119415A JP2014259115A JP2014259115A JP2016119415A JP 2016119415 A JP2016119415 A JP 2016119415A JP 2014259115 A JP2014259115 A JP 2014259115A JP 2014259115 A JP2014259115 A JP 2014259115A JP 2016119415 A JP2016119415 A JP 2016119415A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 69
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000004020 conductor Substances 0.000 claims abstract description 44
- 239000011810 insulating material Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims description 58
- 238000000034 method Methods 0.000 claims description 45
- 239000000463 material Substances 0.000 claims description 24
- 238000004544 sputter deposition Methods 0.000 claims description 14
- 238000005229 chemical vapour deposition Methods 0.000 claims description 9
- 238000007740 vapor deposition Methods 0.000 claims description 6
- 230000001678 irradiating effect Effects 0.000 claims description 5
- 230000003213 activating effect Effects 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 4
- 230000001747 exhibiting effect Effects 0.000 abstract 2
- 235000012431 wafers Nutrition 0.000 abstract 1
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 34
- 239000010949 copper Substances 0.000 description 32
- 229910004298 SiO 2 Inorganic materials 0.000 description 28
- 230000008569 process Effects 0.000 description 28
- 238000005259 measurement Methods 0.000 description 19
- 229910021417 amorphous silicon Inorganic materials 0.000 description 17
- 229910052786 argon Inorganic materials 0.000 description 17
- 238000005304 joining Methods 0.000 description 17
- 125000004429 atom Chemical group 0.000 description 16
- 238000010521 absorption reaction Methods 0.000 description 12
- 238000000619 electron energy-loss spectrum Methods 0.000 description 12
- 239000010408 film Substances 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 230000007246 mechanism Effects 0.000 description 8
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000003917 TEM image Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000005430 electron energy loss spectroscopy Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000005275 alloying Methods 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 230000007935 neutral effect Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000001228 spectrum Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000009864 tensile test Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
- B23K20/02—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating by means of a press ; Diffusion bonding
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
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- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
- B23K20/22—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating taking account of the properties of the materials to be welded
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B37/00—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
- B32B37/14—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C3/00—Assembling of devices or systems from individually processed components
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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Abstract
Description
本発明は、複数の基板を接合して形成される半導体装置、及び、半導体装置の製造方法に関する。 The present invention relates to a semiconductor device formed by bonding a plurality of substrates and a method for manufacturing the semiconductor device.
近年、半導体デバイスの高集積化に関し、同種もしくは異種の半導体デバイスを積層化する３次元集積化技術が注目されている。この３次元集積化技術においては、電極や配線となる導電材と絶縁材とが露出した基板の接合面同士を接合する技術が重要となる。一般に、２枚の基板の接合技術として、常温接合が知られている。常温接合とは、接合する２枚の基板の接合面を真空雰囲気で活性化し、活性化された接合面同士を圧接することで接合する技術である。常温接合では、熱処理を必要とせず、接合材（基板）同士を直接接合することができる。このため、熱処理に伴う基板の膨張等の変形を抑えることができ、接合時に、２枚の基板のアライメントを正確に行うことができるという利点がある。 2. Description of the Related Art In recent years, three-dimensional integration technology for stacking semiconductor devices of the same type or different types has been attracting attention for high integration of semiconductor devices. In this three-dimensional integration technique, a technique for joining together the joint surfaces of the substrates from which the conductive material and the insulating material serving as electrodes and wirings are exposed becomes important. Generally, room temperature bonding is known as a bonding technique for two substrates. The room-temperature bonding is a technique in which the bonding surfaces of two substrates to be bonded are activated in a vacuum atmosphere and the activated bonding surfaces are bonded together by pressure welding. In the room temperature bonding, the bonding materials (substrates) can be bonded directly without the need for heat treatment. For this reason, there is an advantage that deformation such as expansion of the substrate accompanying the heat treatment can be suppressed and alignment of the two substrates can be accurately performed at the time of bonding.
ところで、上記した常温接合では、導電材としての金属類同士を直接接合することはできるものの、絶縁材として一般的に用いられている酸化膜や窒化膜などを直接接合することはできない。このため、従来、接合面に付着された極微量金属を利用して、導電材と絶縁材とを同時に接合（ハイブリッド接合）できる常温接合方法が提案されている（例えば、特許文献１参照）。 By the way, in the above-described room temperature bonding, metals as conductive materials can be directly bonded, but an oxide film or a nitride film generally used as an insulating material cannot be directly bonded. For this reason, conventionally, a room temperature bonding method has been proposed in which a very small amount of metal attached to the bonding surface is used to simultaneously bond (hybrid bonding) the conductive material and the insulating material (for example, see Patent Document 1).
しかしながら、基板の接合面には、微細な導電材（電極）が多数形成されているため、従来の接合方法では、接合面に付着された金属により、近接した導電材（電極）間でリーク電流が発生し、デバイスの動作上の問題が懸念された。 However, since a large number of fine conductive materials (electrodes) are formed on the bonding surface of the substrate, in the conventional bonding method, a leakage current is generated between adjacent conductive materials (electrodes) due to the metal adhering to the bonding surface. Occurred and there were concerns about device operation problems.
本発明は、上記に鑑みてなされたものであって、導電材間のリーク電流の発生を防止しつつ、導電材と絶縁材とを同時に接合可能とする半導体装置、及び、半導体装置の製造方法を提供することを目的とする。 The present invention has been made in view of the above, and a semiconductor device capable of simultaneously bonding a conductive material and an insulating material while preventing the occurrence of leakage current between the conductive materials, and a method for manufacturing the semiconductor device The purpose is to provide.
上述した課題を解決し、目的を達成するために、本発明は、半導体基材の接合面に導電材及び絶縁材がそれぞれ露出した一対の基板を備え、基板同士を常温接合した半導体装置であって、一対の接合面の間に、単独では非導電性を示すと共に導電材と結合して導電性を示す接合中間層を備えることを特徴とする。 In order to solve the above-described problems and achieve the object, the present invention is a semiconductor device that includes a pair of substrates with conductive materials and insulating materials exposed on the bonding surface of a semiconductor substrate, and the substrates are bonded at room temperature. In addition, it is characterized in that a bonding intermediate layer that exhibits non-conductivity alone and is coupled with a conductive material to exhibit conductivity is provided between the pair of bonding surfaces.
この構成によれば、一対の接合面の間に接合中間層を備えるため、導電材及び絶縁材をそれぞれ同時に接合することができる。さらに、接合中間層は、単独では非導電性を示すと共に導電材と結合して導電性を示すため、導電材間の導電性を確保しつつ、絶縁材間の非導電性を確保できる。このため、導電材間のリーク電流の発生を防止でき、半導体装置の安定した動作を実現できる。 According to this configuration, since the bonding intermediate layer is provided between the pair of bonding surfaces, the conductive material and the insulating material can be bonded simultaneously. Furthermore, since the bonding intermediate layer exhibits non-conductivity by itself and combines with the conductive material to exhibit conductivity, the non-conductivity between the insulating materials can be ensured while ensuring the conductivity between the conductive materials. For this reason, it is possible to prevent the occurrence of a leakage current between the conductive materials and to realize a stable operation of the semiconductor device.
また、基板の絶縁材同士は、接合中間層を介して接合されても良い。この構成によれば、絶縁材同士を強固に接合することができる。 Moreover, the insulating materials of the substrates may be bonded via a bonding intermediate layer. According to this structure, insulating materials can be joined firmly.
また、接合中間層は、非晶質半導体材料で形成されても良い。この構成によれば、半導体材料を蒸着、スパッタリングまたは化学気相成長により、単独では非導電性を示すと共に導電材と結合して導電性を示す性質を有する接合中間層を基板の接合面に簡単に形成することができる。 Further, the bonding intermediate layer may be formed of an amorphous semiconductor material. According to this configuration, a bonding intermediate layer having a property of showing conductivity by being bonded to a conductive material by simply depositing a semiconductor material by vapor deposition, sputtering, or chemical vapor deposition on the bonding surface of the substrate is simple. Can be formed.
また、少なくとも一方の基板は、接合面における絶縁材の高さ位置が導電材よりも低く形成されても良い。この構成によれば、基板同士を圧接した際に、この圧接荷重が導電材にかかるため、この導電材により接合中間層が破断される。このため、導電材同士が直接的に接合されることにより、導電材間の接合において良好な電気特性及び接合強度を得ることが可能となる。 Further, at least one of the substrates may be formed such that the height of the insulating material on the bonding surface is lower than that of the conductive material. According to this configuration, when the substrates are pressed against each other, the pressure contact load is applied to the conductive material, so that the bonding intermediate layer is broken by the conductive material. For this reason, it becomes possible to obtain favorable electrical characteristics and bonding strength in the bonding between the conductive materials by bonding the conductive materials directly.
また、本発明は、半導体基材の接合面に導電材及び絶縁材がそれぞれ露出した一対の基板同士を常温接合して製造した半導体装置の製造方法であって、基板の接合面をそれぞれ活性化させる工程と、活性化された接合面の少なくとも一方に、単独では非導電性を示すと共に導電材と結合して導電性を示す接合中間層を形成する工程と、接合中間層を介して、一対の基板同士を圧接する工程と、を備えたことを特徴とする。この構成によれば、導電材及び絶縁材をそれぞれ同時に接合するハイブリッド接合を容易に実現することができる。 The present invention also relates to a method of manufacturing a semiconductor device manufactured by room-temperature bonding of a pair of substrates each having a conductive material and an insulating material exposed to a bonding surface of a semiconductor substrate, and each of the bonding surfaces of the substrates is activated. A step of forming a bonding intermediate layer that is electrically non-conductive and bonded to a conductive material and exhibits conductivity on at least one of the activated bonding surfaces; And a step of pressing the substrates together. According to this configuration, it is possible to easily realize hybrid bonding in which the conductive material and the insulating material are simultaneously bonded.
また、接合中間層は、半導体材料の蒸着やスパッタリングまたは化学気相成長により形成されても良い。この構成によれば、基板の接合面に接合中間層を簡単に形成することができる。 Further, the bonding intermediate layer may be formed by vapor deposition, sputtering, or chemical vapor deposition of a semiconductor material. According to this configuration, the bonding intermediate layer can be easily formed on the bonding surface of the substrate.
また、半導体材料に高速原子ビームを照射して、半導体材料をスパッタリングすることにより、一方の基板の接合面に接合中間層を形成した後、該接合面に形成された接合中間層に高速原子ビームを照射して、該接合中間層を形成する半導体材料の一部をスパッタリングすることにより、他方の基板の接合面に接合中間層を形成しても良い。この構成によれば、作業手順を簡素化し、各基板の接合面に接合中間層を簡単に形成することができる。 In addition, by irradiating a semiconductor material with a fast atom beam and sputtering the semiconductor material, a bonding intermediate layer is formed on the bonding surface of one substrate, and then the high-speed atom beam is applied to the bonding intermediate layer formed on the bonding surface. The bonding intermediate layer may be formed on the bonding surface of the other substrate by sputtering a part of the semiconductor material forming the bonding intermediate layer. According to this configuration, the work procedure can be simplified, and the bonding intermediate layer can be easily formed on the bonding surface of each substrate.
また、少なくとも一方の基板は、接合面における絶縁材の高さ位置が導電材よりも低く形成され、接合中間層は、基板同士を圧接する際に導電材により破断され、該導電材同士が直接的に接合されても良い。この構成によれば、導電材同士が直接的に接合されることにより、導電材間の接合において良好な電気特性及び接合強度を得ることが可能となる。 Further, at least one of the substrates is formed such that the height of the insulating material on the bonding surface is lower than that of the conductive material, and the bonding intermediate layer is broken by the conductive material when the substrates are pressed together, and the conductive materials are directly connected to each other. May be joined together. According to this configuration, it is possible to obtain good electrical characteristics and bonding strength in the bonding between the conductive materials by bonding the conductive materials directly.
また、一対の基板を圧接した後に、該基板を所定の温度で加熱する工程を備えてもよい。この構成によれば、導電材間の接合強度及び電気特性の向上を図ることができる。 Further, a step of heating the substrate at a predetermined temperature after the pair of substrates is pressed may be provided. According to this configuration, it is possible to improve the bonding strength and electrical characteristics between the conductive materials.
本発明によれば、導電材間のリーク電流の発生を防止しつつ、導電材と絶縁材とを同時に接合することができる。 According to the present invention, it is possible to simultaneously bond the conductive material and the insulating material while preventing the occurrence of leakage current between the conductive materials.
以下に、本発明に係る実施形態について、図面を参照して説明する。なお、以下の実施形態によりこの発明が限定されるものではない。また、以下の実施形態における構成要素には、当業者が置換可能かつ容易なもの、あるいは実質的に同一のものが含まれる。 Embodiments according to the present invention will be described below with reference to the drawings. In addition, this invention is not limited by the following embodiment. In addition, constituent elements in the following embodiments include those that can be easily replaced by those skilled in the art or those that are substantially the same.
図１は、本実施形態に係る半導体装置が接合される常温接合装置の構成を模式的に示す断面図である。常温接合装置１０は、図１に示すように、真空チャンバ１１と、この真空チャンバ１１内に設置される上側ステージ１２、下側ステージ１３と、高速原子ビーム源（FAB: Fast Atom Beam）１４，１５と、真空排気装置１６とを備えている。 FIG. 1 is a cross-sectional view schematically showing a configuration of a room temperature bonding apparatus to which the semiconductor device according to the present embodiment is bonded. As shown in FIG. 1, the room temperature bonding apparatus 10 includes a vacuum chamber 11, an upper stage 12 and a lower stage 13 installed in the vacuum chamber 11, a fast atom beam source (FAB) 14, 15 and a vacuum exhaust device 16.
真空チャンバ１１は内部を環境から密閉する容器であり、真空排気装置１６は、真空チャンバ１１の内部から気体を排出する。これにより、真空チャンバ１１の内部は、真空雰囲気となる。さらに、真空チャンバ１１は、この真空チャンバ１１の内部空間と外部とを連通させ、または、分離するゲート（不図示）を備える。 The vacuum chamber 11 is a container that seals the inside from the environment, and the vacuum exhaust device 16 discharges gas from the inside of the vacuum chamber 11. Thereby, the inside of the vacuum chamber 11 becomes a vacuum atmosphere. Furthermore, the vacuum chamber 11 includes a gate (not shown) that allows the internal space of the vacuum chamber 11 to communicate with the outside.
上側ステージ１２は、円板状に形成された静電チャック１２Ａと、この静電チャック１２Ａを鉛直方向に上下させる圧接機構１２Ｂとを備えている。静電チャック１２Ａは、円板の下端に誘電層を備え、その誘電層に電圧を印加し、静電力によってその誘電層に第１ウェハ（基板）１７を吸着して支持する。圧接機構１２Ｂは、ユーザの操作により、静電チャック１２Ａを真空チャンバ１１に対して鉛直方向に平行移動させる。 The upper stage 12 includes an electrostatic chuck 12A formed in a disk shape and a pressure contact mechanism 12B that moves the electrostatic chuck 12A up and down in the vertical direction. The electrostatic chuck 12A includes a dielectric layer at the lower end of the disk, applies a voltage to the dielectric layer, and adsorbs and supports the first wafer (substrate) 17 on the dielectric layer by electrostatic force. The pressure contact mechanism 12B translates the electrostatic chuck 12A in the vertical direction with respect to the vacuum chamber 11 by a user operation.
下側ステージ１３は、その上面に第２ウェハ（基板）１８を支持するステージであり、図示されていない移送機構を備えている。その移送機構は、ユーザの操作により下側ステージ１３を水平方向に平行移動させ、下側ステージ１３を鉛直方向に平行な回転軸を中心に回転移動させる。また、下側ステージ１３は、その上端に誘電層を備え、その誘電層に電圧を印加し、静電力によってその誘電層に第２ウェハ１８を吸着して支持する機構を備えても良い。 The lower stage 13 is a stage that supports the second wafer (substrate) 18 on its upper surface, and includes a transfer mechanism (not shown). The transfer mechanism translates the lower stage 13 in the horizontal direction by the user's operation, and rotates the lower stage 13 around a rotation axis parallel to the vertical direction. Further, the lower stage 13 may be provided with a dielectric layer at its upper end, a mechanism for applying a voltage to the dielectric layer, and attracting and supporting the second wafer 18 on the dielectric layer by electrostatic force.
高速原子ビーム源１４，１５は、ウェハの表面の活性化に用いられる中性原子ビーム（例えば、アルゴンＡｒ原子）を出射する。一方の高速原子ビーム源１４は、上側ステージ１２に支持される第１ウェハ１７に向けて配置され、他方の高速原子ビーム源１５は、下側ステージ１３に支持される第２ウェハ１８に向けて配置される。中性原子ビームが照射されることにより、第１ウェハ１７及び第２ウェハ１８の活性化が行われる。また、高速原子ビーム源１４，１５の代わりに、他の活性化手段（例えば、イオンガンまたはプラズマ）が各ウェハの活性化に用いられても良い。 The fast atom beam sources 14 and 15 emit neutral atom beams (for example, argon Ar atoms) used for activating the wafer surface. One fast atom beam source 14 is disposed toward the first wafer 17 supported by the upper stage 12, and the other fast atom beam source 15 is directed toward the second wafer 18 supported by the lower stage 13. Be placed. By irradiating the neutral atom beam, the first wafer 17 and the second wafer 18 are activated. Further, instead of the fast atomic beam sources 14 and 15, other activating means (for example, ion gun or plasma) may be used for activating each wafer.
次に、常温接合装置１０を用いて常温接合される半導体装置２０について説明する。図２は、接合前の第１ウェハと第２ウェハの構成を模式的に示す断面図であり、図３は、第１ウェハと第２ウェハとを接合して形成された半導体装置の構成を模式的に示す断面図である。第１ウェハ１７は、図２に示すように、第１半導体基材２１上に積層して形成された第１絶縁層（絶縁材）２２と、この第１絶縁層２２に形成された第１接合電極（導電材）２３とを備える。第１絶縁層２２及び第１接合電極２３は、それぞれ第１ウェハ１７の表面１７Ａに露出して形成され、この表面１７Ａが接合面として機能する。また、第２ウェハ１８は、第２半導体基材２４上に積層して形成された第２絶縁層（絶縁材）２５と、この第２絶縁層２５に形成された第２接合電極（導電材）２６とを備える。第２絶縁層２５及び第２接合電極２６は、それぞれ第２ウェハ１８の表面１８Ａに露出して形成され、この表面１８Ａが接合面として機能する。これらの表面１７Ａ，１８Ａは平坦面に形成され、表面１７Ａ，１８Ａ同士は密接される。 Next, the semiconductor device 20 that is bonded at room temperature using the room temperature bonding apparatus 10 will be described. FIG. 2 is a cross-sectional view schematically showing the configuration of the first wafer and the second wafer before bonding, and FIG. 3 shows the configuration of the semiconductor device formed by bonding the first wafer and the second wafer. It is sectional drawing shown typically. As shown in FIG. 2, the first wafer 17 includes a first insulating layer (insulating material) 22 formed on the first semiconductor substrate 21 and a first insulating layer 22 formed on the first insulating layer 22. And a bonding electrode (conductive material) 23. The first insulating layer 22 and the first bonding electrode 23 are formed so as to be exposed on the surface 17A of the first wafer 17, and the surface 17A functions as a bonding surface. In addition, the second wafer 18 includes a second insulating layer (insulating material) 25 formed on the second semiconductor substrate 24 and a second bonding electrode (conductive material) formed on the second insulating layer 25. 26). The second insulating layer 25 and the second bonding electrode 26 are respectively exposed on the surface 18A of the second wafer 18, and the surface 18A functions as a bonding surface. These surfaces 17A and 18A are formed as flat surfaces, and the surfaces 17A and 18A are in close contact with each other.
第１半導体基材２１及び第２半導体基材２４は、例えば、単結晶シリコン（Ｓｉ）が用いられるが、他にも単結晶ゲルマニウム（Ｇｅ）、ヒ化ガリウム（ＧａＡｓ）やシリコンカーバイド（ＳｉＣ）などの材料を用いることもできる。また、第１半導体基材２１及び第２半導体基材２４は、同種の材料だけでなく、異種の材料を用いても良い。 For example, single crystal silicon (Si) is used for the first semiconductor substrate 21 and the second semiconductor substrate 24, but single crystal germanium (Ge), gallium arsenide (GaAs), and silicon carbide (SiC) are also used. Such materials can also be used. Further, the first semiconductor substrate 21 and the second semiconductor substrate 24 may use not only the same type of material but also different types of materials.
第１絶縁層２２及び第２絶縁層２５は、表面１７Ａ，１８Ａ側に、半導体基材の酸化物や窒化物で形成される。具体的には、半導体基材として単結晶シリコン（Ｓｉ）が用いられている場合には、第１絶縁層２２及び第２絶縁層２５としてシリコン酸化膜（ＳｉＯ２）やシリコン窒化膜（Ｓｉ３Ｎ４）が、酸化炉、窒化炉、または、化学気相成長（ＣＶＤ：Chemical Vapor Deposition）装置などでの成膜にて形成される。本実施形態では、シリコン酸化膜（ＳｉＯ２）が形成されているものとする。また、第１接合電極２３及び第２接合電極２６は、導電性の優れた材料、例えば銅（Ｃｕ）により形成されている。この第１接合電極２３及び第２接合電極２６には、配線材が接続されて電子回路や各種素子が形成される。 The first insulating layer 22 and the second insulating layer 25 are formed of oxide or nitride of a semiconductor substrate on the surface 17A, 18A side. Specifically, when single crystal silicon (Si) is used as a semiconductor substrate, a silicon oxide film (SiO 2 ) or a silicon nitride film (Si 3 ) is used as the first insulating layer 22 and the second insulating layer 25. N 4 ) is formed by film formation in an oxidation furnace, a nitriding furnace, a chemical vapor deposition (CVD) apparatus, or the like. In the present embodiment, it is assumed that a silicon oxide film (SiO 2 ) is formed. Moreover, the 1st joining electrode 23 and the 2nd joining electrode 26 are formed with the material excellent in electroconductivity, for example, copper (Cu). A wiring material is connected to the first bonding electrode 23 and the second bonding electrode 26 to form an electronic circuit and various elements.
第１ウェハ１７と第２ウェハ１８とを接合する場合には、図２、図３に示すように、接合面としての表面１７Ａ，１８Ａをお互いに対向させ、上記した常温接合装置１０を用いて常温接合がなされる。この場合、第１ウェハ１７の第１接合電極２３と、第２ウェハ１８の第２接合電極２６とが接合され、第１ウェハ１７の第１絶縁層２２と、第２ウェハ１８の第２絶縁層２５とが接合される。常温接合では、第１接合電極２３及び第２接合電極２６の金属類同士は接合できるものの、第１絶縁層２２及び第２絶縁層２５はシリコン酸化膜（ＳｉＯ２）やシリコン窒化膜（Ｓｉ３Ｎ４）であるため、これらを直接接合することはできない。このため、本構成では、図４に示すように、第１ウェハ１７の表面１７Ａと第２ウェハ１８の表面１８Ａとの間に、接合電極と絶縁層とを同時に接合するための接合中間層３０が設けられている。 When bonding the first wafer 17 and the second wafer 18, as shown in FIGS. 2 and 3, the surfaces 17 </ b> A and 18 </ b> A as bonding surfaces are opposed to each other, and the room temperature bonding apparatus 10 described above is used. Room temperature bonding is performed. In this case, the first bonding electrode 23 of the first wafer 17 and the second bonding electrode 26 of the second wafer 18 are bonded, and the first insulation layer 22 of the first wafer 17 and the second insulation of the second wafer 18 are combined. Layer 25 is bonded. In the room temperature bonding, although the metals of the first bonding electrode 23 and the second bonding electrode 26 can be bonded to each other, the first insulating layer 22 and the second insulating layer 25 are formed of a silicon oxide film (SiO 2 ) or a silicon nitride film (Si 3). Since they are N 4 ), they cannot be joined directly. For this reason, in this configuration, as shown in FIG. 4, the bonding intermediate layer 30 for bonding the bonding electrode and the insulating layer simultaneously between the surface 17 </ b> A of the first wafer 17 and the surface 18 </ b> A of the second wafer 18. Is provided.
接合中間層３０は、第１ウェハ１７の表面１７Ａと第２ウェハ１８の表面１８Ａとを接合するための薄膜であり、非晶質半導体材料（例えば、アモルファスシリコン）によって形成されている。発明者の研究によれば、非晶質半導体材料（例えば、アモルファスシリコン）は、単独（単体）では非導電性を示すが、金属類等と結合することにより導電性を示すことが判明した。このため、非晶質半導体材料を接合中間層３０として用いることにより、第１絶縁層２２と第２絶縁層２５との間の非導電性（絶縁性）を保持しつつ第１絶縁層２２と第２絶縁層２５とを強固に接合することができる。さらに、第１接合電極２３と第２接合電極２６との間の電気特性の劣化がなく、第１接合電極２３と第２接合電極２６との間の導電性を確保することができる。すなわち、接合中間層３０は、非導電性（絶縁性）を保持しつつ第１絶縁層２２と第２絶縁層２５とを接合する領域（絶縁接合部３０ａ）と、導電性を有し、第１接合電極２３と第２接合電極２６とを接合する領域（導電接合部３０ｂ）とを備えて形成される。 The bonding intermediate layer 30 is a thin film for bonding the surface 17A of the first wafer 17 and the surface 18A of the second wafer 18 and is formed of an amorphous semiconductor material (for example, amorphous silicon). According to the inventor's research, it has been found that an amorphous semiconductor material (for example, amorphous silicon) exhibits non-conductivity by itself (single substance), but exhibits conductivity by bonding with metals or the like. For this reason, by using an amorphous semiconductor material as the bonding intermediate layer 30, the first insulating layer 22 and the first insulating layer 22 are maintained while maintaining the non-conductivity (insulating property) between the first insulating layer 22 and the second insulating layer 25. The second insulating layer 25 can be firmly bonded. Furthermore, the electrical characteristics between the first bonding electrode 23 and the second bonding electrode 26 are not deteriorated, and the conductivity between the first bonding electrode 23 and the second bonding electrode 26 can be ensured. In other words, the bonding intermediate layer 30 has a region (insulating bonding portion 30a) for bonding the first insulating layer 22 and the second insulating layer 25 while maintaining non-conductivity (insulation), and has conductivity. A region where the first bonding electrode 23 and the second bonding electrode 26 are bonded (conductive bonding portion 30b) is formed.
次に、接合中間層３０を具体的に説明する。図５は、絶縁層としてのＳｉＯ２／ＳｉＯ２の接合界面を示す透過型電子顕微鏡写真であり、図６は、接合電極としてのＣｕ／Ｃｕの接合界面を示す透過型電子顕微鏡写真である。透過型電子顕微鏡（TEM：Transmission Electron Microscope）は、観察対象に電子線をあて、それを透過してきた電子が作り出す干渉像を拡大して観察する形式の電子顕微鏡である。 Next, the bonding intermediate layer 30 will be specifically described. FIG. 5 is a transmission electron micrograph showing a SiO 2 / SiO 2 bonding interface as an insulating layer, and FIG. 6 is a transmission electron micrograph showing a Cu / Cu bonding interface as a bonding electrode. A transmission electron microscope (TEM) is a type of electron microscope in which an electron beam is applied to an observation target and an interference image created by electrons transmitted through the electron beam is magnified and observed.
図５に示すように、第１絶縁層２２及び第２絶縁層２５としてのＳｉＯ２／ＳｉＯ２の接合界面には、接合中間層３０（絶縁接合部３０ａ）としてアモルファスシリコン層が形成されている。また、図６に示すように、第１接合電極２３と第２接合電極２６としてのＣｕ／Ｃｕの接合界面には、同様に、接合中間層３０（導電接合部３０ｂ）としてアモルファスシリコン層が形成されている。これら接合中間層３０は、いずれも厚さが７〜９ｎｍ程度に形成されており、接合中間層３０とＳｉＯ２もしくはＣｕとの間にボイド（空隙）の存在は見られず十分な密着状態が得られている。 As shown in FIG. 5, an amorphous silicon layer is formed as a bonding intermediate layer 30 (insulating bonding portion 30a) at the bonding interface of SiO 2 / SiO 2 as the first insulating layer 22 and the second insulating layer 25. . In addition, as shown in FIG. 6, an amorphous silicon layer is similarly formed as a bonding intermediate layer 30 (conductive bonding portion 30b) at the Cu / Cu bonding interface as the first bonding electrode 23 and the second bonding electrode 26. Has been. These junction intermediate layers 30 are all formed to have a thickness of about 7 to 9 nm, and there is no presence of voids (voids) between the junction intermediate layer 30 and SiO 2 or Cu. Has been obtained.
接合中間層３０は、単結晶シリコンのスパッタリングにより、絶縁層（ＳｉＯ２）及び接合電極（Ｃｕ）の接合面に形成されたものであり、単結晶シリコンから非晶質（アモルファス）シリコンに状態を変えて形成されている。発明者は、接合中間層３０内の測定点１及び絶縁層（ＳｉＯ２）内の測定点２の２か所について、電子エネルギー損失分光法（EELS：Electron Energy-Loss Spectroscopy）による界面近傍の状態分析を行った。電子エネルギー損失分光法とは、電子が薄片試料を透過する際に原子との相互作用により失うエネルギーを測定することによって、物質の構成元素や電子構造を分析する手法である。 The bonding intermediate layer 30 is formed on the bonding surface of the insulating layer (SiO 2 ) and the bonding electrode (Cu) by sputtering of single crystal silicon, and changes the state from single crystal silicon to amorphous silicon. It is formed by changing. The inventor is in the state of the vicinity of the interface by electron energy loss spectroscopy (EELS) at two points of measurement point 1 in the bonding intermediate layer 30 and measurement point 2 in the insulating layer (SiO 2 ). Analysis was carried out. Electron energy loss spectroscopy is a technique for analyzing constituent elements and electronic structures of substances by measuring the energy lost by the interaction of atoms with electrons when they pass through a thin sample.
図７は、測定点におけるＳｉ−Ｌ吸収端のＥＥＬＳスペクトルを示すグラフであり、図８は、測定点におけるＯ−Ｋ吸収端のＥＥＬＳスペクトルを示すグラフである。この図７においては、比較のために、単結晶シリコン（ｃ−Ｓｉ）、アモルファスシリコン（ａ−Ｓｉ）、及びシリコン酸化膜（ＳｉＯ２）における同エネルギー域のスペクトルを示している。図７に示すように、接合中間層３０内の測定点１におけるＳｉ−Ｌ吸収端のＥＥＬＳスペクトルは、単結晶シリコンもしくはアモルファスシリコンに近く、ＳｉＯ２の特徴的なピークは見られなかった。また、Ｏ−Ｋ吸収端におけるＥＥＬＳスペクトルでは、接合中間層３０には、酸素原子Ｏの存在はほとんど確認されなかった。このため、接合中間層３０はＳｉ酸化物を含むものではなく、さらに、図５に示す高分解能像から、第１絶縁層２２と第２絶縁層２５との間に形成される接合中間層３０（絶縁接合部３０ａ）は、アモルファスシリコンであると考えられる。 FIG. 7 is a graph showing the EELS spectrum at the Si-L absorption edge at the measurement point, and FIG. 8 is a graph showing the EELS spectrum at the OK absorption edge at the measurement point. For comparison, FIG. 7 shows spectra in the same energy region in single crystal silicon (c-Si), amorphous silicon (a-Si), and silicon oxide film (SiO 2 ). As shown in FIG. 7, the EELS spectrum of the Si-L absorption edge at the measurement point 1 in the junction intermediate layer 30 is close to single crystal silicon or amorphous silicon, and no characteristic peak of SiO 2 was observed. Further, in the EELS spectrum at the OK absorption edge, the presence of oxygen atoms O was hardly confirmed in the junction intermediate layer 30. For this reason, the junction intermediate layer 30 does not contain Si oxide, and further, the junction intermediate layer 30 formed between the first insulating layer 22 and the second insulating layer 25 from the high resolution image shown in FIG. (Insulating junction 30a) is considered to be amorphous silicon.
続いて、ＳｉＯ２／ＳｉＯ２間に形成された接合中間層３０（絶縁接合部３０ａ）の電気特性を測定した。図９は、ＳｉＯ２／ＳｉＯ２間における電流と電圧との関係を示すグラフである。この図９に示すように、アモルファスシリコンは、単結晶シリコンと比べて電気特性が大きく異なり、単独では電気を通さない非導電性を有することが確認できた。ここで、非導電性とは、抵抗率が１０５Ω・ｃｍ以上の状態をいう。 Subsequently, the electrical characteristics of the bonding intermediate layer 30 (insulating bonding portion 30a) formed between SiO 2 / SiO 2 were measured. FIG. 9 is a graph showing the relationship between current and voltage between SiO 2 / SiO 2 . As shown in FIG. 9, it was confirmed that amorphous silicon has significantly different electrical characteristics from single crystal silicon and has non-conductivity that does not conduct electricity by itself. Here, non-conductive refers to a state where the resistivity is 10 5 Ω · cm or more.
また、接合中間層３０を介して接合されたＳｉＯ２／ＳｉＯ２の接合強度を測定した。接合強度の測定は、接合したＳｉＯ２／ＳｉＯ２の試料を１２ｍｍ×１２ｍｍのサイズのチップにカットし、このチップを引張試験することにより行った。試験に際しては、チップを治具に固定し、この治具への引張荷重を変更しつつ、チップが破断する際の荷重を測定した。引張試験では、破断は生じたものの、この破断はチップと治具とが接着界面で剥離したことにより生じ、ＳｉＯ２／ＳｉＯ２の接合は保持されていた。破断したときの引張強度は２５ＭＰａ以上であったため、接合中間層３０による接合界面の強度はこれ以上と考えられる。 Further, the bonding strength of SiO 2 / SiO 2 bonded through the bonding intermediate layer 30 was measured. The bonding strength was measured by cutting a bonded SiO 2 / SiO 2 sample into a chip having a size of 12 mm × 12 mm and performing a tensile test on the chip. In the test, the tip was fixed to a jig, and the load at which the tip broke was measured while changing the tensile load on the jig. In the tensile test, the fracture occurred, but the fracture occurred when the chip and the jig were peeled off at the adhesive interface, and the SiO 2 / SiO 2 bond was maintained. Since the tensile strength at the time of rupture was 25 MPa or more, the strength of the bonding interface by the bonding intermediate layer 30 is considered to be higher than this.
このように、アモルファスシリコン（非晶質半導体材料）を接合中間層３０として用いた構成では、第１絶縁層２２と第２絶縁層２５との間の非導電性（絶縁性）を保持しつつ第１絶縁層２２と第２絶縁層２５とを強固に接合することができるという結果を得た。 As described above, in the configuration in which amorphous silicon (amorphous semiconductor material) is used as the bonding intermediate layer 30, the non-conductivity (insulating property) between the first insulating layer 22 and the second insulating layer 25 is maintained. The result that the 1st insulating layer 22 and the 2nd insulating layer 25 were able to be joined firmly was obtained.
次に、Ｃｕ／Ｃｕ間に形成された接合中間層３０（導電接合部３０ｂ）について、電子エネルギー損失分光法による界面近傍の状態分析を行った。測定点としては、接合中間層３０とＣｕとの境界近傍に位置する測定点Ａ、接合中間層３０内の厚み方向中央に位置する測定点Ｂ、及び、測定点Ａと測定点Ｂとの厚み方向の間に位置する測定点Ｃの３つである。図１０は、測定点におけるＳｉ−Ｌ吸収端のＥＥＬＳスペクトルを示すグラフであり、図１１は、測定点におけるＣｕ−Ｌ吸収端のＥＥＬＳスペクトルを示すグラフである。この図１１においては、比較のために、銅（Ｃｕ）の同エネルギー域のスペクトルを示している。 Next, a state analysis in the vicinity of the interface by electron energy loss spectroscopy was performed on the bonding intermediate layer 30 (conductive bonding portion 30b) formed between Cu / Cu. As the measurement points, the measurement point A located near the boundary between the bonding intermediate layer 30 and Cu, the measurement point B located in the center of the bonding intermediate layer 30 in the thickness direction, and the thickness between the measurement point A and the measurement point B There are three measurement points C located between the directions. FIG. 10 is a graph showing the EELS spectrum of the Si-L absorption edge at the measurement point, and FIG. 11 is a graph showing the EELS spectrum of the Cu-L absorption edge at the measurement point. In FIG. 11, the spectrum of the same energy region of copper (Cu) is shown for comparison.
図１０に示すように、接合中間層３０内の測定点Ａ〜ＣにおけるＳｉ−Ｌ吸収端におけるＥＥＬＳスペクトルは、いずれも同じような形状であり、シリコンが単独で存在していることを示している。また、図１１に示すように、Ｃｕ−Ｌ吸収端のＥＥＬＳスペクトルでは、接合中間層３０内のいずれの測定点Ａ〜Ｃでも銅の存在が認められる。 As shown in FIG. 10, the EELS spectra at the Si-L absorption edge at the measurement points A to C in the bonding intermediate layer 30 are all the same shape, indicating that silicon is present alone. Yes. Further, as shown in FIG. 11, in the EELS spectrum at the Cu-L absorption edge, the presence of copper is recognized at any measurement point A to C in the bonding intermediate layer 30.
さらに、Ｃｕ／Ｃｕ間に形成された接合中間層３０の電気特性を測定した。図１２は、Ｃｕ／Ｃｕ間における電流と電圧との関係を示すグラフである。この図１２に示すように、接合中間層３０を介して接合された場合であっても、電圧と電流との間には直線的な関係が得られ、Ｃｕ／Ｃｕ間においてオーミックな（オームの法則に従った）接続が得られていると考えられる。また、Ｃｕ／Ｃｕ間を直接接合した際の抵抗値が２０（ｍΩ）以下であったのに対し、接合中間層３０を介した接合では、２５（ｍΩ）以下となり、ほぼ同程度の結果であった。この点は、ＳｉＯ２／ＳｉＯ２間の接合中間層では非導電性を示していたことと比較すると大きく異なる。これは、上述したように、部分的には微量であるが、接合中間層３０（導電接合部３０ｂ）の全域に銅が存在しているためと考えられ、第１接合電極２３と第２接合電極２６との圧接時に、接合中間層３０のアモルファスシリコンと各電極の銅とが結合をしたためと考えられる。 Furthermore, the electrical property of the joining intermediate | middle layer 30 formed between Cu / Cu was measured. FIG. 12 is a graph showing the relationship between current and voltage between Cu / Cu. As shown in FIG. 12, a linear relationship is obtained between the voltage and the current even when bonded via the bonding intermediate layer 30, and ohmic (ohmic) is obtained between Cu / Cu. It is thought that a connection (according to the law) has been obtained. In addition, the resistance value when Cu / Cu was directly joined was 20 (mΩ) or less, whereas in the case of joining via the joining intermediate layer 30, it was 25 (mΩ) or less, and the results were almost the same. there were. This point is greatly different from that in which the bonding intermediate layer between SiO 2 / SiO 2 showed non-conductivity. As described above, this is considered to be due to the presence of copper in the entire region of the bonding intermediate layer 30 (the conductive bonding portion 30b). It is considered that the amorphous silicon of the bonding intermediate layer 30 was bonded to the copper of each electrode during the pressure contact with the electrode 26.
このように、アモルファスシリコン（非晶質半導体材料）を接合中間層３０として用いた構成では、第１接合電極２３と第２接合電極２６との間の導電性を確保できるという結果を得た。従って、本実施形態の半導体装置２０は、接合電極２３，２６及び絶縁層２２，２５がそれぞれ露出した表面１７Ａ，１８Ａの間に接合中間層３０を備えるため、接合電極２３，２６及び絶縁層２２，２５をそれぞれ同時に接合するハイブリッド接合を実現できる。さらに、接合中間層３０は、単独では非導電性を示すと共に接合電極２３，２６と結合して導電性を示すため、第１接合電極２３と第２接合電極２６との間の導電性を確保しつつ、第１絶縁層２２と第２絶縁層２５との間の非導電性を確保できる。このため、第１接合電極２３と第２接合電極２６との間を流れる電流が第１絶縁層２２と第２絶縁層２５との間を流れることを防止できるため、リーク電流の発生を防止することができ、半導体装置２０の安定した動作を実現できる。 As described above, in the configuration using amorphous silicon (amorphous semiconductor material) as the bonding intermediate layer 30, the conductivity between the first bonding electrode 23 and the second bonding electrode 26 can be secured. Therefore, since the semiconductor device 20 of this embodiment includes the bonding intermediate layer 30 between the surfaces 17A and 18A from which the bonding electrodes 23 and 26 and the insulating layers 22 and 25 are exposed, the bonding electrodes 23 and 26 and the insulating layer 22 are provided. , 25 can be hybridized together. Furthermore, since the bonding intermediate layer 30 exhibits non-conductivity by itself and combines with the bonding electrodes 23 and 26 to exhibit conductivity, the conductivity between the first bonding electrode 23 and the second bonding electrode 26 is ensured. However, non-conductivity between the first insulating layer 22 and the second insulating layer 25 can be ensured. For this reason, since it can prevent that the electric current which flows between the 1st junction electrode 23 and the 2nd junction electrode 26 flows between the 1st insulating layer 22 and the 2nd insulating layer 25, generation | occurrence | production of a leakage current is prevented. Therefore, stable operation of the semiconductor device 20 can be realized.
次に、半導体装置２０の製造手順について説明する。図１３−１〜図１３−６は、第１ウェハと第２ウェハとを接合する工程を示す工程説明図である。前提として、第１ウェハ１７と第２ウェハ１８は、それぞれ表面１７Ａ，１８Ａに接合電極２３，２６及び絶縁層２２，２５がそれぞれ露出した状態に、別の作業工程によって事前に製造されている。 Next, a manufacturing procedure of the semiconductor device 20 will be described. FIGS. 13-1 to 13-6 are process explanatory views showing the process of bonding the first wafer and the second wafer. As a premise, the first wafer 17 and the second wafer 18 are pre-manufactured by another work process in a state where the bonding electrodes 23 and 26 and the insulating layers 22 and 25 are exposed on the surfaces 17A and 18A, respectively.
図１３−１に示すように、第１ウェハ１７が常温接合装置１０の真空チャンバ１１内に搬送され、この第１ウェハ１７は、表面１７Ａが鉛直下方を向くように、上側ステージ１２の静電チャック１２Ａに支持される。真空チャンバ１１内は真空雰囲気に維持されている。この状態で、高速原子ビーム源１４から第１ウェハ１７の表面１７Ａに向けて、アルゴンビーム１４ａを出射する。このアルゴンビーム１４ａは、第１ウェハ１７の表面１７Ａに照射され、該表面１７Ａが活性化される。 As shown in FIG. 13A, the first wafer 17 is transferred into the vacuum chamber 11 of the room temperature bonding apparatus 10, and the first wafer 17 is electrostatically connected to the upper stage 12 so that the surface 17 </ b> A faces vertically downward. Supported by the chuck 12A. The inside of the vacuum chamber 11 is maintained in a vacuum atmosphere. In this state, an argon beam 14a is emitted from the fast atom beam source 14 toward the surface 17A of the first wafer 17. The argon beam 14a is applied to the surface 17A of the first wafer 17, and the surface 17A is activated.
続いて、図１３−２に示すように、真空チャンバ１１内にベアウェハ３１が搬送され、このベアウェハ３１は下側ステージ１３の上面に載置される。ベアウェハ３１は、単結晶シリコンで形成されており、接合中間層３０を生成する際のスパッタ源として用いられる。この状態で、高速原子ビーム源１５からベアウェハ３１に向けて、アルゴンビーム１５ａを出射する。これにより、ベアウェハ３１はスパッタリングされ、ベアウェハ３１から弾き出されたシリコン原子が上昇し、第１ウェハ１７の表面１７Ａ上に接合中間層３０が成膜される。本実施形態では、アルゴンビーム１５ａの照射を所定時間（例えば１０ｍｉｎ）行い、第１ウェハ１７の表面１７Ａ上に厚さ１ｎｍ〜５０ｎｍ程度の接合中間層３０を形成する。この接合中間層３０は、上述したように、アモルファス（非晶質）シリコンである。 Subsequently, as shown in FIG. 13B, the bare wafer 31 is transferred into the vacuum chamber 11, and the bare wafer 31 is placed on the upper surface of the lower stage 13. The bare wafer 31 is formed of single crystal silicon, and is used as a sputtering source when the bonding intermediate layer 30 is generated. In this state, an argon beam 15 a is emitted from the fast atom beam source 15 toward the bare wafer 31. As a result, the bare wafer 31 is sputtered, the silicon atoms ejected from the bare wafer 31 rise, and the bonding intermediate layer 30 is formed on the surface 17 </ b> A of the first wafer 17. In the present embodiment, the argon beam 15a is irradiated for a predetermined time (for example, 10 minutes), and the bonding intermediate layer 30 having a thickness of about 1 nm to 50 nm is formed on the surface 17A of the first wafer 17. As described above, the bonding intermediate layer 30 is amorphous (amorphous) silicon.
続いて、図１３−３に示すように、真空チャンバ１１からベアウェハ３１を搬出し、その代わりに第２ウェハ１８が真空チャンバ１１内に搬送される。この第２ウェハ１８は、表面１８Ａが鉛直上方を向くように、下側ステージ１３の上面に載置される。続いて、図１３−４に示すように、高速原子ビーム源１５から第２ウェハ１８の表面１８Ａに向けて、アルゴンビーム１５ａを出射する。このアルゴンビーム１５ａは、第２ウェハ１８の表面１８Ａに照射され、該表面１８Ａが活性化される。 Subsequently, as shown in FIG. 13C, the bare wafer 31 is unloaded from the vacuum chamber 11, and the second wafer 18 is transferred into the vacuum chamber 11 instead. The second wafer 18 is placed on the upper surface of the lower stage 13 so that the surface 18A faces vertically upward. Subsequently, as shown in FIG. 13-4, an argon beam 15 a is emitted from the fast atom beam source 15 toward the surface 18 </ b> A of the second wafer 18. The argon beam 15a is applied to the surface 18A of the second wafer 18, and the surface 18A is activated.
続いて、図１３−５に示すように、高速原子ビーム源１４から第１ウェハ１７の表面に形成された接合中間層３０に向けて、アルゴンビーム１４ａを出射する。この場合、接合中間層３０を形成するアモルファスシリコンの一部がスパッタ源として機能する。アルゴンビーム１４ａの照射により、接合中間層３０がスパッタリングされ、接合中間層３０から弾き出されたシリコン原子が上昇し、第２ウェハ１８の表面１８Ａ上にも接合中間層３０が成膜される。本実施形態では、アルゴンビーム１４ａの照射を所定時間（例えば１０ｍｉｎ）行い、第２ウェハ１８の表面１８Ａ上に厚さ１ｎｍ〜５０ｎｍ程度の接合中間層３０を形成する。この接合中間層３０も、上述したように、アモルファス（非晶質）シリコンである。本実施形態では、第１ウェハ１７の表面に形成された接合中間層３０をスパッタ源として使用するため、第２ウェハ１８の表面１８Ａ用に別途スパッタ源を用意する必要が無いと共に、真空チャンバ１１内へのスパッタ源の出し入れが低減するため、作業手順を簡素化し、第１ウェハ１７及び第２ウェハ１８の各表面１７Ａ，１８Ａに接合中間層３０を簡単に形成することができる。 Subsequently, as shown in FIG. 13-5, the argon beam 14 a is emitted from the fast atom beam source 14 toward the bonding intermediate layer 30 formed on the surface of the first wafer 17. In this case, part of the amorphous silicon forming the bonding intermediate layer 30 functions as a sputtering source. By irradiation with the argon beam 14 a, the bonding intermediate layer 30 is sputtered, the silicon atoms ejected from the bonding intermediate layer 30 rise, and the bonding intermediate layer 30 is also formed on the surface 18 </ b> A of the second wafer 18. In this embodiment, the argon beam 14a is irradiated for a predetermined time (for example, 10 minutes), and the bonding intermediate layer 30 having a thickness of about 1 nm to 50 nm is formed on the surface 18A of the second wafer 18. As described above, the bonding intermediate layer 30 is also amorphous (amorphous) silicon. In this embodiment, since the bonding intermediate layer 30 formed on the surface of the first wafer 17 is used as a sputtering source, it is not necessary to prepare a separate sputtering source for the surface 18A of the second wafer 18, and the vacuum chamber 11 Since the sputter source is reduced in and out, the work procedure is simplified, and the bonding intermediate layer 30 can be easily formed on the surfaces 17A and 18A of the first wafer 17 and the second wafer 18, respectively.
続いて、第１ウェハ１７と第２ウェハ１８とのアライメントを行った後、図１３−６に示すように、上側ステージ１２の圧接機構１２Ｂを動作させることで、第１ウェハ１７を支持した静電チャック１２Ａを鉛直下方に下降させ、第１ウェハ１７と第２ウェハ１８とを圧接する。これにより、第１ウェハ１７の表面１７Ａと第２ウェハ１８の表面１８Ａとが接合中間層３０を介して接合され、半導体装置２０が形成される。続いて、真空チャンバ１１内で半導体装置２０（第１ウェハ１７及び第２ウェハ１８）を所定温度（例えば５０℃〜４００℃程度）で加熱する。これにより、第１接合電極２３及び第２接合電極２６の銅Ｃｕと、接合中間層３０のアモルファスシリコンとの合金化が促進され、第１接合電極２３と第２接合電極２６との接合がより強固となり、電気特性が向上する。 Subsequently, after the alignment of the first wafer 17 and the second wafer 18, as shown in FIG. 13-6, the pressure contact mechanism 12B of the upper stage 12 is operated to operate the static wafer that supports the first wafer 17. The electric chuck 12 </ b> A is lowered vertically and the first wafer 17 and the second wafer 18 are pressed against each other. Thereby, the surface 17A of the first wafer 17 and the surface 18A of the second wafer 18 are bonded via the bonding intermediate layer 30, and the semiconductor device 20 is formed. Subsequently, the semiconductor device 20 (the first wafer 17 and the second wafer 18) is heated in the vacuum chamber 11 at a predetermined temperature (for example, about 50 ° C. to 400 ° C.). As a result, the alloying of the copper Cu of the first bonding electrode 23 and the second bonding electrode 26 and the amorphous silicon of the bonding intermediate layer 30 is promoted, and the bonding of the first bonding electrode 23 and the second bonding electrode 26 is further enhanced. Strengthens and improves electrical properties.
以上説明したように、本実施形態の半導体装置２０の製造方法は、第１ウェハ１７の表面１７Ａと第２ウェハ１８の表面１８Ａをそれぞれ活性化させる工程と、活性化された表面１７Ａ，１８Ａに接合中間層３０を形成する工程と、接合中間層３０を介して、第１ウェハ１７と第２ウェハ１８とを圧接する工程とを備えたため、接合電極２３，２６及び絶縁層２２，２５をそれぞれ同時に接合するハイブリッド接合を容易に実現することができる。 As described above, in the method of manufacturing the semiconductor device 20 according to the present embodiment, the surface 17A of the first wafer 17 and the surface 18A of the second wafer 18 are activated, and the activated surfaces 17A and 18A are activated. Since the bonding intermediate layer 30 and the step of pressing the first wafer 17 and the second wafer 18 through the bonding intermediate layer 30 are provided, the bonding electrodes 23 and 26 and the insulating layers 22 and 25 are respectively formed. Hybrid joining that joins at the same time can be easily realized.
さらに、本実施形態では、ベアウェハ３１にアルゴンビーム１５ａを照射して、ベアウェハ３１をスパッタリングすることにより、第１ウェハ１７の表面１７Ａに接合中間層３０を形成した後、この表面１７Ａに形成された接合中間層３０にアルゴンビーム１４ａを照射して、接合中間層３０を形成するアモルファスシリコンの一部をスパッタリングすることにより、第２ウェハ１８の表面１８Ａに接合中間層３０を形成するため、作業手順を簡素化し、第１ウェハ１７及び第２ウェハ１８の各表面１７Ａ，１８Ａに接合中間層３０を簡単に形成することができる。 Further, in this embodiment, the bare wafer 31 is irradiated with the argon beam 15a and the bare wafer 31 is sputtered to form the bonding intermediate layer 30 on the surface 17A of the first wafer 17, and then formed on the surface 17A. Operation procedure for forming the bonding intermediate layer 30 on the surface 18A of the second wafer 18 by irradiating the bonding intermediate layer 30 with the argon beam 14a and sputtering a part of the amorphous silicon forming the bonding intermediate layer 30. The bonding intermediate layer 30 can be easily formed on the respective surfaces 17A and 18A of the first wafer 17 and the second wafer 18.
次に、半導体装置２０の別の製造手順について説明する。図１４−１〜図１４−４は、第１ウェハと第２ウェハとを接合する別の工程を示す工程説明図である。この場合においても、前提として、第１ウェハ１７と第２ウェハ１８は、それぞれ表面１７Ａ，１８Ａに接合電極２３，２６及び絶縁層２２，２５がそれぞれ露出した状態に、別の作業工程によって事前に製造されている。 Next, another manufacturing procedure of the semiconductor device 20 will be described. 14A to 14D are process explanatory views showing another process of bonding the first wafer and the second wafer. Even in this case, as a premise, the first wafer 17 and the second wafer 18 are preliminarily formed in a state where the bonding electrodes 23 and 26 and the insulating layers 22 and 25 are exposed on the surfaces 17A and 18A, respectively, by another work process. It is manufactured.
図１４−１に示すように、第１ウェハ１７が常温接合装置１０の真空チャンバ１１内に搬送され、この第１ウェハ１７は、表面１７Ａが鉛直下方を向くように、上側ステージ１２の静電チャック１２Ａに支持される。同様に、第２ウェハ１８が真空チャンバ１１内に搬送され、この第２ウェハ１８は、表面１８Ａが鉛直上方を向くように、下側ステージ１３の上面に載置される。真空チャンバ１１内は真空雰囲気に維持されている。この状態で、高速原子ビーム源１４，１５からそれぞれ第１ウェハ１７の表面１７Ａ，第２ウェハ１８の表面１８Ａに向けて、アルゴンビーム１４ａ，１５ａを出射する。このアルゴンビーム１４ａ，１５ａは、第１ウェハ１７の表面１７Ａ，第２ウェハ１８の表面１８Ａにそれぞれ照射され、該表面１７Ａ，１８Ａが活性化される。 As shown in FIG. 14A, the first wafer 17 is transferred into the vacuum chamber 11 of the room temperature bonding apparatus 10, and the first wafer 17 is electrostatically connected to the upper stage 12 so that the surface 17 </ b> A faces vertically downward. Supported by the chuck 12A. Similarly, the second wafer 18 is transferred into the vacuum chamber 11, and this second wafer 18 is placed on the upper surface of the lower stage 13 so that the surface 18A faces vertically upward. The inside of the vacuum chamber 11 is maintained in a vacuum atmosphere. In this state, argon beams 14a and 15a are emitted from the fast atom beam sources 14 and 15 toward the surface 17A of the first wafer 17 and the surface 18A of the second wafer 18, respectively. The argon beams 14a and 15a are applied to the surface 17A of the first wafer 17 and the surface 18A of the second wafer 18, respectively, and the surfaces 17A and 18A are activated.
続いて、図１４−２に示すように、表面１７Ａ，１８Ａが活性化された第１ウェハ１７及び第２ウェハ１８は、真空チャンバ１１から成膜チャンバ４０に移送される。この場合、第１ウェハ１７及び第２ウェハ１８は、外気（酸素）に触れないように、真空の搬送路によって搬送されることが好ましい。成膜チャンバ４０は、第１ウェハ１７の表面１７Ａ及び第２ウェハ１８の表面１８Ａに上記した接合中間層３０を成膜するためのチャンバであり、成膜チャンバ４０内には、化学気相成長装置（不図示）が配置されている。化学気相成長法は、第１ウェハ１７及び第２ウェハ１８を所定条件で加熱した状態で、第１ウェハ１７の表面１７Ａ及び第２ウェハ１８の表面１８Ａに、シリコンを含む原料ガスを供給し、これら表面１７Ａ，１８Ａでの化学反応により接合中間層３０を形成するものである。この化学気相成長法においても、接合中間層３０はアモルファス（非晶質）シリコンにより形成される。この構成では、接合中間層３０を別途形成することができるため、接合工程の処理時間の短縮化を図ることができる。 Subsequently, as shown in FIG. 14B, the first wafer 17 and the second wafer 18 whose surfaces 17 </ b> A and 18 </ b> A are activated are transferred from the vacuum chamber 11 to the film forming chamber 40. In this case, it is preferable that the 1st wafer 17 and the 2nd wafer 18 are conveyed by the vacuum conveyance path so that external air (oxygen) may not be touched. The film forming chamber 40 is a chamber for forming the bonding intermediate layer 30 on the surface 17A of the first wafer 17 and the surface 18A of the second wafer 18, and chemical vapor deposition is performed in the film forming chamber 40. A device (not shown) is arranged. In the chemical vapor deposition method, a source gas containing silicon is supplied to the surface 17A of the first wafer 17 and the surface 18A of the second wafer 18 with the first wafer 17 and the second wafer 18 heated under predetermined conditions. The bonding intermediate layer 30 is formed by a chemical reaction on the surfaces 17A and 18A. Also in this chemical vapor deposition method, the bonding intermediate layer 30 is formed of amorphous (amorphous) silicon. In this configuration, since the bonding intermediate layer 30 can be formed separately, the processing time of the bonding process can be shortened.
続いて、図１４−３に示すように、接合中間層３０が形成された第１ウェハ１７及び第２ウェハ１８を真空チャンバ１１内に搬送する。そして、第１ウェハ１７は、接合中間層３０が鉛直下方を向くように、上側ステージ１２の静電チャック１２Ａに支持され、第２ウェハ１８は、接合中間層３０が鉛直上方を向くように、下側ステージ１３の上面に載置される。真空チャンバ１１内は真空雰囲気に維持されている。この状態で、高速原子ビーム源１４，１５からそれぞれ第１ウェハ１７，第２ウェハ１８に形成された接合中間層３０，３０に向けて、アルゴンビーム１４ａ，１５ａを出射する。このアルゴンビーム１４ａ，１５ａは、第１ウェハ１７，第２ウェハ１８の接合中間層３０，３０の表面にそれぞれ照射され、該接合中間層３０，３０の表面が活性化される。 Subsequently, as shown in FIG. 14C, the first wafer 17 and the second wafer 18 on which the bonding intermediate layer 30 is formed are transferred into the vacuum chamber 11. Then, the first wafer 17 is supported by the electrostatic chuck 12A of the upper stage 12 so that the bonding intermediate layer 30 faces vertically downward, and the second wafer 18 has a bonding intermediate layer 30 facing vertically upward. It is placed on the upper surface of the lower stage 13. The inside of the vacuum chamber 11 is maintained in a vacuum atmosphere. In this state, argon beams 14a and 15a are emitted from the fast atom beam sources 14 and 15 toward the bonding intermediate layers 30 and 30 formed on the first wafer 17 and the second wafer 18, respectively. The argon beams 14a and 15a are applied to the surfaces of the bonding intermediate layers 30 and 30 of the first wafer 17 and the second wafer 18, respectively, and the surfaces of the bonding intermediate layers 30 and 30 are activated.
続いて、第１ウェハ１７と第２ウェハ１８とのアライメントを行った後、図１４−４に示すように、上側ステージ１２の圧接機構１２Ｂを動作させることで、第１ウェハ１７を支持した静電チャック１２Ａを鉛直下方に下降させ、第１ウェハ１７と第２ウェハ１８とを圧接する。これにより、第１ウェハ１７の表面１７Ａと第２ウェハ１８の表面１８Ａとが接合中間層３０を介して接合され、半導体装置２０が形成される。続いて、真空チャンバ１１内で半導体装置２０（第１ウェハ１７及び第２ウェハ１８）を所定温度（例えば５０℃〜４００℃）で加熱する。これにより、第１接合電極２３及び第２接合電極２６の銅Ｃｕと、接合中間層３０のアモルファスシリコンとの合金化が促進され、第１接合電極２３と第２接合電極２６との接合がより強固となり、電気特性が向上する。 Subsequently, after the alignment of the first wafer 17 and the second wafer 18, as shown in FIG. 14-4, the pressure contact mechanism 12B of the upper stage 12 is operated, thereby supporting the static that supports the first wafer 17. The electric chuck 12 </ b> A is lowered vertically and the first wafer 17 and the second wafer 18 are pressed against each other. Thereby, the surface 17A of the first wafer 17 and the surface 18A of the second wafer 18 are bonded via the bonding intermediate layer 30, and the semiconductor device 20 is formed. Subsequently, the semiconductor device 20 (the first wafer 17 and the second wafer 18) is heated in the vacuum chamber 11 at a predetermined temperature (for example, 50 ° C. to 400 ° C.). As a result, the alloying of the copper Cu of the first bonding electrode 23 and the second bonding electrode 26 and the amorphous silicon of the bonding intermediate layer 30 is promoted, and the bonding of the first bonding electrode 23 and the second bonding electrode 26 is further enhanced. Strengthens and improves electrical properties.
次に、別の実施形態について説明する。図１５−１は、別の実施形態に係る第１ウェハと第２ウェハの接合前の構成を模式的に示す断面図であり、図１５−２は、別の実施形態に係る第１ウェハと第２ウェハとを接合した状態の構成を模式的に示す断面図である。上記した構成では、第１ウェハ１７の表面１７Ａ、及び、第２ウェハ１８の表面１８Ａは、それぞれ平坦面に形成され、これら表面１７Ａ，１８Ａ同士は密接するように形成されていた。これに対し、この別の実施形態では、図１５−１に示すように、表面１７Ａには、第１半導体基材１２１上に積層された第１絶縁層１２２と第１接合電極１２３とが露出しており、第１絶縁層１２２の表面１２２Ａの高さ位置が第１接合電極１２３の表面１２３Ａの高さ位置よりも低く形成されている。この高さ位置の差ｔは、接合中間層３０と同程度の１ｎｍ〜１００ｎｍ程度に設定されている。同様に、表面１８Ａには、第２半導体基材１２４上に積層された第２絶縁層１２５と第２接合電極１２６とが露出しており、第２絶縁層１２５の表面１２５Ａの高さ位置が第２接合電極１２６の表面１２６Ａの高さ位置よりも低く形成されている。この高さ位置の差ｔは、接合中間層３０と同程度の１ｎｍ〜１００ｎｍ程度に設定されている。この他の構成については、上記した実施形態の構成と同様であるため説明を省略する。 Next, another embodiment will be described. FIG. 15-1 is a cross-sectional view schematically illustrating a configuration before bonding of the first wafer and the second wafer according to another embodiment, and FIG. 15-2 illustrates the first wafer according to another embodiment. It is sectional drawing which shows typically the structure of the state which joined the 2nd wafer. In the configuration described above, the surface 17A of the first wafer 17 and the surface 18A of the second wafer 18 are each formed as a flat surface, and the surfaces 17A and 18A are formed in close contact with each other. On the other hand, in this other embodiment, as shown in FIG. 15A, the first insulating layer 122 and the first bonding electrode 123 laminated on the first semiconductor substrate 121 are exposed on the surface 17A. The height position of the surface 122A of the first insulating layer 122 is formed lower than the height position of the surface 123A of the first bonding electrode 123. The height position difference t is set to about 1 nm to 100 nm, which is the same as that of the bonding intermediate layer 30. Similarly, the second insulating layer 125 and the second bonding electrode 126 stacked on the second semiconductor substrate 124 are exposed on the surface 18A, and the height position of the surface 125A of the second insulating layer 125 is the height position. It is formed lower than the height position of the surface 126A of the second bonding electrode 126. The height position difference t is set to about 1 nm to 100 nm, which is the same as that of the bonding intermediate layer 30. Since other configurations are the same as the configurations of the above-described embodiment, description thereof will be omitted.
この構成によれば、第１ウェハ１７と第２ウェハ１８とを圧接した際に、この圧接荷重が第１接合電極１２３及び第２接合電極１２６にかかるため、図１５−２に示すように、接合中間層３０は、第１接合電極１２３と第２接合電極１２６とにより破断され、第１接合電極１２３と第２接合電極１２６同士が直接的に接合される。これにより、第１接合電極１２３と第２接合電極１２６との間の接合において良好な電気特性及び接合強度を得ることが可能となる。 According to this configuration, when the first wafer 17 and the second wafer 18 are pressed against each other, this pressure contact load is applied to the first bonding electrode 123 and the second bonding electrode 126. Therefore, as shown in FIG. The bonding intermediate layer 30 is broken by the first bonding electrode 123 and the second bonding electrode 126, and the first bonding electrode 123 and the second bonding electrode 126 are directly bonded to each other. Thereby, it is possible to obtain good electrical characteristics and bonding strength in the bonding between the first bonding electrode 123 and the second bonding electrode 126.
以上、本発明の実施形態について説明したが、本発明は、上記実施形態に限定されるものではない。例えば、上記実施形態では、接合中間層３０を第１ウェハ１７及び第２ウェハ１８の表面１７Ａ，１８Ａの両方に形成したが、一方に形成してもよい。また、上記実施形態では、第１接合電極１２３及び第２接合電極１２６をそれぞれ第１絶縁層１２２及び第２絶縁層１２５よりも突となる形状としたが、第１接合電極１２３または第２接合電極１２６の一方であっても良い。また、上記実施形態では、接合中間層３０をスパッタリングまたは化学気相成長法によって形成する構成を説明したが、蒸着によって接合中間層３０を形成しても良い。蒸着は、真空容器の中で、蒸着材料（例えばシリコン）を加熱し、気化または昇華して、離れた位置に置かれた基板の表面に付着させて薄膜を形成するものである。この方法によっても、接合中間層３０はアモルファス（非晶質）シリコンにより形成される。この構成では、接合中間層３０を別途形成することができるため、接合工程の処理時間の短縮化を図ることができる。 As mentioned above, although embodiment of this invention was described, this invention is not limited to the said embodiment. For example, in the above embodiment, the bonding intermediate layer 30 is formed on both the surfaces 17A and 18A of the first wafer 17 and the second wafer 18, but may be formed on one. Moreover, in the said embodiment, although the 1st joining electrode 123 and the 2nd joining electrode 126 were made into the shape which protrudes rather than the 1st insulating layer 122 and the 2nd insulating layer 125, respectively, the 1st joining electrode 123 or the 2nd joining electrode is used. One of the electrodes 126 may be used. Moreover, although the structure which forms the joining intermediate | middle layer 30 by sputtering or a chemical vapor deposition method was demonstrated in the said embodiment, you may form the joining intermediate | middle layer 30 by vapor deposition. In vapor deposition, a vapor deposition material (for example, silicon) is heated in a vacuum vessel, vaporized or sublimated, and adhered to the surface of a substrate placed at a remote position to form a thin film. Also by this method, the bonding intermediate layer 30 is formed of amorphous (amorphous) silicon. In this configuration, since the bonding intermediate layer 30 can be formed separately, the processing time of the bonding process can be shortened.
１０ 常温接合装置
１１ 真空チャンバ
１２ 上側ステージ
１２Ａ 静電チャック
１２Ｂ 圧接機構
１３ 下側ステージ
１４，１５ 高速原子ビーム源
１４ａ，１５ａ アルゴンビーム
１７ 第１ウェハ（基板）
１７Ａ 表面（接合面）
１８ 第２ウェハ（基板）
１８Ａ 表面（接合面）
２０ 半導体装置
２１，１２１ 第１半導体基材
２２，１２２ 第１絶縁層（絶縁材）
２３，１２３ 第１接合電極（導電材）
２４，１２４ 第２半導体基材
２５，１２５ 第２絶縁層（絶縁材）
２６，１２６ 第２接合電極（導電材）
３０ 接合中間層
３１ ベアウェハ
４０ 成膜チャンバ
１２２Ａ 表面
１２３Ａ 表面
１２５Ａ 表面
１２６Ａ 表面
DESCRIPTION OF SYMBOLS 10 Room temperature bonding apparatus 11 Vacuum chamber 12 Upper stage 12A Electrostatic chuck 12B Pressure welding mechanism 13 Lower stage 14, 15 High-speed atomic beam source 14a, 15a Argon beam 17 First wafer (substrate)
17A Surface (joint surface)
18 Second wafer (substrate)
18A Surface (joint surface)
20 Semiconductor device 21, 121 First semiconductor substrate 22, 122 First insulating layer (insulating material)
23, 123 First joining electrode (conductive material)
24,124 Second semiconductor substrate 25,125 Second insulating layer (insulating material)
26, 126 Second junction electrode (conductive material)
30 Bonding intermediate layer 31 Bare wafer 40 Deposition chamber 122A Surface 123A Surface 125A Surface 126A Surface
Claims (9)
一対の前記接合面の間に、単独では非導電性を示すと共に前記導電材と結合して導電性を示す接合中間層を備えることを特徴とする半導体装置。 A semiconductor device comprising a pair of substrates in which a conductive material and an insulating material are respectively exposed on a bonding surface of a semiconductor base material, wherein the substrates are bonded at room temperature,
A semiconductor device comprising a bonding intermediate layer between the pair of bonding surfaces that exhibits non-conductivity by itself and combines with the conductive material to exhibit conductivity.
前記基板の接合面をそれぞれ活性化させる工程と、
活性化された前記接合面の少なくとも一方に、単独では非導電性を示すと共に前記導電材と結合して導電性を示す接合中間層を形成する工程と、
前記接合中間層を介して、一対の前記基板同士を圧接する工程と、を備えたことを特徴とする半導体装置の製造方法。 A manufacturing method of a semiconductor device manufactured by room-temperature bonding of a pair of substrates each having a conductive material and an insulating material exposed on a bonding surface of a semiconductor substrate,
Activating each bonding surface of the substrate;
Forming at least one of the activated bonding surfaces a bonding intermediate layer that exhibits non-conductivity by itself and combines with the conductive material to exhibit conductivity;
And a step of pressure-contacting the pair of substrates with the bonding intermediate layer interposed therebetween.
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| JPH01133341A (en) * | 1987-11-19 | 1989-05-25 | Hitachi Ltd | Manufacture of semiconductor device and manufacturing equipment therefor |
| JPH0684733A (en) * | 1992-09-03 | 1994-03-25 | Hitachi Ltd | Semiconductor integrated circuit device, its manufacture, and semiconductor integrated circuit manufacturing device |
| JPH1092702A (en) * | 1996-09-18 | 1998-04-10 | Agency Of Ind Science & Technol | Method for normal-temperature junction of silicon wafer |
| JPH10256263A (en) * | 1997-03-11 | 1998-09-25 | Nec Corp | Soi substrate and manufacture therefor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP7222493B2 (en) | 2021-04-28 | 2023-02-15 | 日本電産マシンツール株式会社 | Semiconductor device manufacturing method and room temperature bonding apparatus |
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| Publication number | Publication date |
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| TW201635338A (en) | 2016-10-01 |
| EP3240015A1 (en) | 2017-11-01 |
| EP3240015B1 (en) | 2022-11-23 |
| US20170355040A1 (en) | 2017-12-14 |
| KR20170086619A (en) | 2017-07-26 |
| TWI596651B (en) | 2017-08-21 |
| CN107112199A (en) | 2017-08-29 |
| CN107112199B (en) | 2021-08-17 |
| JP6165127B2 (en) | 2017-07-19 |
| WO2016103846A1 (en) | 2016-06-30 |
| KR101994011B1 (en) | 2019-06-27 |
| EP3240015A4 (en) | 2018-08-01 |
| US10486263B2 (en) | 2019-11-26 |
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