JP7222493B2 - Semiconductor device manufacturing method and room temperature bonding apparatus - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor device in which a plurality of semiconductor substrates are room temperature bonded, and a room temperature bonding apparatus.

2. Description of the Related Art In recent years, with regard to high integration of semiconductor devices (semiconductor devices), a three-dimensional integration technique for stacking semiconductor devices of the same type or different types has attracted attention. In this three-dimensional integration technology, it is important to bond the bonding surfaces of the substrates where the conductive material and the insulating material, which serve as electrodes and wirings, are exposed. Room temperature bonding is generally known as a technique for bonding two substrates. Room-temperature bonding is a technique for bonding by activating the bonding surfaces of two substrates to be bonded in a vacuum atmosphere and pressing the activated bonding surfaces together. In room-temperature bonding, substrates can be directly bonded without requiring heat treatment. Therefore, there is an advantage that deformation such as expansion of the substrates due to heat treatment can be suppressed, and the alignment of the two substrates can be accurately performed at the time of bonding.

By the way, in the room-temperature bonding described above, although it is possible to directly bond metals as conductive materials, it is not possible to directly bond oxide films and nitride films that are generally used as insulating materials. For this reason, conventionally, a technology has been proposed in which a semiconductor material (silicon) is sputtered to form a bonding intermediate layer made of an amorphous semiconductor material (amorphous silicon) on the bonding surface, and a conductive material and an insulating material are simultaneously bonded (hybrid bonding). It has been proposed (see Patent Document 1, for example).

Japanese Patent No. 6165127

However, the conventional configuration requires a step of forming a bonding intermediate layer on the bonding surface by sputtering silicon in the bonding chamber, which complicates the process and increases the tact time (process work time) when bonding the substrates. There is the problem of lengthening. In addition, in the conventional structure, since the bonding intermediate layer (amorphous silicon) is also formed on the surface of the conductive material that constitutes the electrode, the bonding intermediate layer is interposed between the conductive materials after bonding, and the electric current between the conductive materials is reduced. There is a problem that resistance increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and is a method of manufacturing a semiconductor device that reduces the number of steps in bonding substrates and shortens the tact time while reducing the electrical resistance between conductive materials. and a room temperature bonding apparatus.

In order to solve the above-described problems and achieve the object, the present invention provides a method for manufacturing a semiconductor device manufactured by room-temperature bonding of a plurality of semiconductor substrates, wherein the semiconductor substrates are manufactured by atomic deposition. forming a film of aluminum oxide as an insulating layer on each surface of each of the plurality of semiconductor substrates; polishing the insulating layer until the conductive material disposed on each surface of the plurality of semiconductor substrates is exposed; irradiating the bonding surfaces of the plurality of semiconductor substrates, where the insulating layers are exposed, with a neutral atom beam to activate the conductive material and the insulating layer exposed on the bonding surfaces; The conductive materials and the insulating layers exposed on the bonding surfaces of the plurality of semiconductor substrates are opposed to each other, and the plurality of semiconductor substrates are press-contacted to each other, and the conductive materials and the insulating layers are respectively bonded to each other. and a room temperature bonding step.

According to this configuration, aluminum oxide is deposited as an insulating layer on each of the surfaces of the plurality of semiconductor substrates using an atomic deposition method, so that silicon is sputtered in the bonding chamber to form the bonding intermediate layer. process becomes unnecessary. Therefore, it is possible to shorten the tact time by reducing the number of steps in bonding the semiconductor substrates.

In this configuration, the thickness of the insulating layer is preferably 1 [nm] or more in the film forming step. Further, after the step of forming the film, a step of polishing the insulating layer may be provided until the conductive material arranged on the surface of the semiconductor substrate is exposed to the bonding surface. Moreover, after bonding a plurality of semiconductor substrates, a step of heating the semiconductor substrates to a predetermined temperature may be provided.

The present invention also provides a room-temperature bonding apparatus for room-temperature bonding of a plurality of semiconductor substrates, and a film forming unit that forms an insulating layer of aluminum oxide on each of the surfaces of the plurality of semiconductor substrates by using an atomic deposition method. a polishing unit for polishing the insulating layer until the conductive material disposed on each surface of the plurality of semiconductor substrates is exposed; an activation unit for irradiating a bonding surface with a neutral atom beam to activate the conductive material and the insulating layer exposed on the bonding surface; and a plurality of activated semiconductor substrates exposed on the bonding surfaces. a bonding portion for press-contacting a plurality of semiconductor substrates with the conductive materials and the insulating layers facing each other, and bonding the conductive materials and the insulating layers at room temperature . do. According to this configuration, by using the atomic deposition method to form a film of aluminum oxide as an insulating layer on the surface of each of the plurality of semiconductor substrates, silicon is sputtered in the bonding chamber to form an intermediate bonding layer. A step of forming a layer becomes unnecessary. Therefore, it is possible to shorten the tact time by reducing the number of steps in bonding the semiconductor substrates.

Moreover, it is preferable that the film-forming part forms the insulating layer with a thickness of 1 [nm] or more. Further, the semiconductor substrate has a conductive material disposed on the surface thereof, and the semiconductor substrate on which the insulating layer is formed may be provided with a polishing unit for polishing the insulating layer until the conductive material is exposed on the bonding surface. preferable.

According to the present invention, it is possible to shorten the tact time by reducing the number of processes when bonding semiconductor substrates. In addition, it is possible to reduce the electrical resistance between the conductive members as compared with the conventional configuration in which the bonding intermediate layer is interposed.

FIG. 1 is a block diagram showing a schematic configuration of a room temperature bonding apparatus according to this embodiment. FIG. 2 is a schematic diagram of a film forming unit that constitutes a part of the room temperature bonding apparatus. FIG. 3 is a schematic diagram of a polishing unit forming part of the room temperature bonding apparatus. FIG. 4 is a schematic diagram of a bonding unit forming part of the room temperature bonding apparatus. FIG. 5 is a cross-sectional view schematically showing the configuration of a pair of wafers before bonding. FIG. 6 is a cross-sectional view schematically showing the structure of a semiconductor device formed by bonding a pair of wafers. FIG. 7 is a cross-sectional view schematically showing the structure of a wafer before film formation. FIG. 8 is a cross-sectional view schematically showing the structure of a wafer after film formation. FIG. 9 is a cross-sectional view schematically showing the configuration of the wafer after polishing. FIG. 10 is an explanatory diagram showing the process of joining a pair of wafers. FIG. 11 is an explanatory view showing the process of joining a pair of wafers. FIG. 12 is a transmission electron micrograph showing a joint surface of aluminum oxide as the second insulating layer. FIG. 13 is a table showing the film thickness, bonding state, and bonding strength when aluminum oxide films formed by different film forming methods are bonded together.

EMBODIMENT OF THE INVENTION Below, embodiment which concerns on this invention is described with reference to drawings. In addition, this invention is not limited by the following embodiment. In addition, components in the following embodiments include components that can be easily replaced by those skilled in the art, or components that are substantially the same.

FIG. 1 is a block diagram showing a schematic configuration of a room temperature bonding apparatus according to this embodiment. FIG. 2 is a schematic diagram of a film forming unit that constitutes a part of the room temperature bonding apparatus. FIG. 3 is a schematic diagram of a polishing unit forming part of the room temperature bonding apparatus. FIG. 4 is a schematic diagram of a bonding unit forming part of the room temperature bonding apparatus.

As shown in FIG. 1, the room temperature bonding apparatus 10 includes a film forming unit (film forming section) 11, a polishing unit (polishing section) 12, and a bonding unit (bonding section) 13. As shown in FIG. The room-temperature bonding apparatus 10 forms an insulating layer (second insulating layer 18 to be described later) on the surface of a disk-shaped wafer 15 (semiconductor substrate; FIG. 2) in the film forming unit 11, and polishes the insulating layer in the polishing unit 12. After polishing the surfaces (bonding surfaces) of the wafers 15, the bonding unit 13 bonds the bonding surfaces of the pair (plurality) of wafers 15 to each other. Between the film forming unit 11 and the polishing unit 12, and between the polishing unit 12 and the bonding unit 13, a transfer mechanism 14 for automatically transferring the processed wafer 15 to the next unit may be provided. Alternatively, a plurality of wafers may be collectively transported to the next unit manually. Also, the arrangement of the film forming unit 11, the polishing unit 12, and the bonding unit 13 can be changed as appropriate. You can also place them individually.

The film forming unit 11 forms an insulating layer (second insulating layer 18) made of an oxide film (aluminum oxide film; Al ₂ O ₃ ) on the surface of the wafer 15 by atomic layer deposition (ALD). It is a device. Atomic deposition is one type of chemical vapor deposition (CVD) method, in which a metal raw material such as an organometallic compound and a raw material (oxidizing agent) containing an element to be chemically bonded to the metal raw material are combined. This is a method of forming a film by alternately supplying to the surface of the wafer 15 .

The film forming unit 11 has a film forming chamber 21, as shown in FIG. The support table 22 has a dielectric layer (not shown) on its upper end surface 22A, and has a mechanism for applying a voltage to the dielectric layer to attract and support the wafer 15 on the dielectric layer by electrostatic force. The support table 22 also incorporates a heater (heating mechanism) 23 for heating the supported wafer 15 to a predetermined temperature. Further, the support table 22 may have a mechanism for rotating the support table 22 around the axis.

The film forming unit 11 also has a metal raw material supply source 24 for supplying a metal raw material into the film forming chamber 21 and an oxidizing agent supply source 25 for supplying an oxidizing agent. These supply sources 24 and 25 are connected in parallel with the film forming chamber 21 via supply pipes 26 and 27, respectively. Tip portions 26A and 27A of the supply pipes 26 and 27 are exposed inside the film forming chamber 21, respectively. The supply pipes 26 and 27 are provided with supply valves 26B and 27B, respectively. supply becomes possible. Note that the metal source material and the oxidizing agent are preferably supplied into the film forming chamber 21 together with, for example, an inert gas.

In this embodiment, for example, trimethyl aluminum (TMA), which is an organometallic compound, is used as the metal raw material, and for example, water vapor (H ₂ O) is used as the oxidizing agent. As the oxidizing agent, oxygen (O ₂ ), ozone (O ₃ ) and hydrogen peroxide (H ₂ O ₂ ) may be used in addition to water vapor.

The film forming unit 11 also includes a vacuum pump 28 . The vacuum pump 28 is for discharging (purging) excess metal raw material and oxidizing agent supplied into the film forming chamber 21 . It is connected. One end 29 A of the discharge pipe 29 is exposed inside the film forming chamber 21 . By operating the vacuum pump 28 while the supply valves 26B and 27B are closed, excess metal raw material and oxidant supplied into the film forming chamber 21 are discharged to the outside.

The polishing unit 12 is a device that polishes the surface of the wafer 15 . By polishing the insulating layer formed on the surface of the wafer 15 by the polishing unit 12, an electrode (conductive material), which is arranged on the surface of the wafer 15 and will be described later, can be exposed on the surface.

As shown in FIG. 3, the polishing unit 12 includes a circular support table 31 that supports the wafer 15 and a polishing wheel 32 that faces the support table 31 . The support table 31 has a dielectric layer (not shown) on its upper end surface 31A, and has a mechanism for applying a voltage to the dielectric layer to attract and support the wafer 15 on the dielectric layer by electrostatic force. The support table 31 also has a drive mechanism (not shown) that rotates the support table 31 about its axis.

The grinding wheel 32 has a circular drive mechanism (not shown) that rotates the grinding wheel 32 about its axis, and a lifting mechanism (not shown) that moves the grinding wheel 32 up and down with respect to the support table 31 . Prepare.

A disk-shaped polishing pad 33 is attached to the lower surface of the polishing wheel 32 . The polishing pad 33 is made by dispersing and fixing abrasive grains in a base material such as urethane or non-woven fabric. A polishing liquid supply nozzle 34 for supplying polishing liquid to the surface of the wafer 15 is arranged near the polishing wheel 32 . The polishing liquid is a liquid that is supplied when polishing the insulating layer formed on the surface of the wafer 15, and may contain a substance that causes a chemical reaction with the insulating layer to perform CMP.

The grinding wheel 32 is arranged with a large eccentricity with respect to the support table 31 . Specifically, the polishing pad 33 is arranged so as to cover at least the center of the wafer 15 and extend (protrude) in the radial direction of the wafer 15 . In this state, by rotating the support table 31 and the polishing wheel 32 while supplying the polishing liquid, the polishing pad 33 partially presses the surface of the wafer 15 to perform polishing.

As shown in FIG. 4, the bonding unit 13 includes a bonding chamber 41, an upper stage 42 and a lower stage 43 installed in the bonding chamber 41, fast atom beam sources (activation units) 44 and 45, A vacuum evacuation device 46 is provided.

The bonding chamber 41 is a container that seals the interior from the environment, and the evacuation device 46 exhausts gas from the interior of the bonding chamber 41 . As a result, the interior of the bonding chamber 41 becomes a vacuum atmosphere. Furthermore, the bonding chamber 41 has a gate (not shown) that communicates or separates the inner space of the bonding chamber 41 from the outside.

The upper stage 42 includes a disk-shaped electrostatic chuck 42A and a press-contact mechanism 42B that vertically moves the electrostatic chuck 42A up and down. The electrostatic chuck 42A has a dielectric layer on the lower end of a disk, and a voltage is applied to the dielectric layer to attract and support the wafer 15 on the dielectric layer by electrostatic force. The pressure contact mechanism 42B translates the electrostatic chuck 42A in the vertical direction with respect to the lower stage 43 by user's operation.

The lower stage 43 is a stage that supports the wafer 15 on its upper surface, and has a transfer mechanism (not shown). The transfer mechanism horizontally translates the lower stage 43 by user's operation, and rotates the lower stage 43 around a rotation axis parallel to the vertical direction. Further, the lower stage 43 may have a dielectric layer on its upper end, apply a voltage to the dielectric layer, and have a mechanism for attracting and supporting the wafer 15 to the dielectric layer by electrostatic force.

Fast Atom Beam (FAB) sources 44 and 45 emit neutral atomic beams (eg, argon Ar atoms) used to activate the surface of the wafer. One fast atom beam source 44 is arranged to face the wafer 15 supported by the upper stage 42 , and the other fast atom beam source 45 is arranged to face the wafer 15 supported by the lower stage 43 . The wafer 15 is activated by being irradiated with the neutral atom beam. Also, instead of the fast atom beam sources 44, 45, other activation means (eg, ion gun or plasma) may be used to activate each wafer. In the example of FIG. 4, a pair of upper and lower fast atom beam sources 44 and 45 are provided in association with the upper stage 42 and the lower stage 43, respectively. The irradiation may be directed toward each supported wafer.

Next, the semiconductor device 50 formed by room temperature bonding in the bonding unit 13 will be described. The semiconductor device 50 is formed by stacking and bonding a plurality of wafers 15, and is used for, for example, a stacked LSI (Large Scale Integration) or a CMOS (Complementary MOS) image sensor. In this embodiment, a configuration in which the semiconductor device 50 is formed by bonding a pair of (two) wafers 15 will be described, but the number of wafers 15 is not limited to this.

FIG. 5 is a cross-sectional view schematically showing the structure of a pair of wafers before bonding, and FIG. 6 is a cross-sectional view schematically showing the structure of a semiconductor device formed by bonding the pair of wafers. As shown in FIG. 5, the wafer 15 includes a semiconductor substrate 16, an electrode 17 and a second insulating layer (insulating layer) 18 which are arranged on the semiconductor substrate 16 with a first insulating layer (oxide film) 19 interposed therebetween. Prepare. The electrodes 17 and the second insulating layer 18 are formed to be exposed on the surface 15A of the wafer 15, and the surface 15A functions as a bonding surface. The surface 17A of each wafer 15 is formed flat, and the surfaces 15A, 15A are brought into close contact with each other.

Single crystal silicon (Si), for example, is used for the semiconductor substrate 16 . In addition to single crystal silicon (Si), materials such as single crystal germanium (Ge), gallium arsenide (GaAs), and silicon carbide (SiC) may also be used as the semiconductor base material 16 .

The first insulating layer 19 is a silicon oxide film (SiO ₂ ) formed by natural oxidation on the surface side of the semiconductor substrate 16 . As the first insulating layer 19, for example, a silicon oxide film (SiO ₂ ) or a silicon nitride film (Si ₃ N ₄ ) is deposited in an oxidation furnace, a nitridation furnace, a chemical vapor deposition (CVD) apparatus, or the like. good too.

Also, the electrode 17 is made of a highly conductive material such as copper (Cu). Wiring materials are connected to the electrodes 17 to form electronic circuits and various elements.

The second insulating layer 18 is composed of an oxide film (aluminum oxide film; Al ₂ O ₃ ) laminated on the first insulating layer 19 . It is known that an aluminum oxide film is generally not bonded at room temperature, like a silicon oxide film. However, as a result of intensive research, the inventors have found that an aluminum oxide film formed by atomic deposition can be directly bonded by room-temperature bonding.

As a result, as shown in FIG. 6, when bonding a pair of wafers 15, 15, the surfaces 15A, 15A as bonding surfaces are opposed to each other, and room temperature bonding is performed using the room temperature bonding apparatus 10 described above. be. In this case, the electrodes 17 of each wafer 15 are joined because they are metals. Moreover, since the second insulating layer 18 of each wafer 15 is an aluminum oxide film formed by atomic deposition, the second insulating layers 18 can be bonded to each other.

Next, a method for manufacturing the semiconductor device 50 will be described. FIG. 7 is a cross-sectional view schematically showing the structure of a wafer before film formation. FIG. 8 is a cross-sectional view schematically showing the structure of a wafer after film formation. FIG. 9 is a cross-sectional view schematically showing the configuration of the wafer after polishing. 10 and 11 are explanatory diagrams showing the process of bonding a pair of wafers.

As shown in FIG. 7, the wafer 15 is prefabricated in a separate work process with the electrode 17 and the first insulating layer 19 exposed on the surface of the semiconductor substrate 16 . Here, the height position of the surface 17A of the electrode 17 is formed higher than the height position of the surface 19A of the first insulating layer 19 . This height position difference t corresponds to the thickness (height) of the second insulating layer 18, which will be described later.

[Film formation process]
A second insulating layer 18 is deposited on the target wafer 15 described above using an atomic deposition method. The wafer 15 has a first insulating layer (for example, SiO ₂ ) 19 made of a natural oxide film and an electrode 17 exposed on the surface of the semiconductor substrate 16 . A second insulating layer 18 is overlaid.

Specifically, when forming an aluminum oxide film as the second insulating layer 18 on the wafer 15, as shown in FIG. . Then, the supply valve 26B is opened, trimethylaluminum (TMA) is supplied from the metal raw material supply source 24 into the film formation chamber 21 through the supply pipe 26, and the surface of the wafer 15 (the surface of the first insulating layer 19 and the electrode 17) is to adsorb TMA.

TMA has the property that once the surface of the wafer 15 is completely covered, no more TMA is deposited. Therefore, a monomolecular film of TMA or its decomposition product is formed on the surface of the wafer 15 . Here, it is preferable to heat the wafer 15 by the heater 23 and keep it at a predetermined temperature (for example, 200 to 400.degree. C.). As a result, oxidation and detachment of methyl groups, which will be described later, can be stably caused on the wafer 15 .

Next, the supply valve 26B is closed to stop the supply of TMA, and the vacuum pump 28 is operated. As a result, excess TMA supplied into the film forming chamber 21 is discharged to the outside. After that, the vacuum pump 28 is stopped, the supply valve 27B is opened, and water vapor (H ₂ O) as an oxidant is supplied from the oxidant supply source 25 into the film forming chamber 21 through the supply pipe 27 . As a result, the aluminum atoms contained in the monomolecular film of TMA or its decomposition product are oxidized on the surface of the wafer 15 and methyl groups are eliminated. When all the aluminum atoms in the monomolecular film are oxidized, the oxygen atoms contained in the oxidant are no longer adsorbed to the surface of the wafer 15 . Therefore, a monomolecular film of aluminum oxide can be formed on the surface of the wafer 15 (surfaces of the first insulating layer 19 and the electrode 17).

The supply valve 27B is closed to stop the supply of water vapor, and the vacuum pump 28 is operated. As a result, excess water vapor supplied into the film forming chamber 21 is discharged to the outside. After the water vapor is removed from the deposition chamber 21 in this manner, the supply valve 26B is opened again to supply TMA into the deposition chamber 21. As a result, the aluminum oxide monomolecular film formed on the surface of the wafer 15 is , TMA or its decomposition products are deposited. By repeating this process to alternately deposit an aluminum atomic layer and an oxygen atomic layer, it is possible to obtain a dense aluminum oxide film with no oxygen defects and good quality. Also, by adjusting the number of repetitions of these steps, the thickness of the aluminum oxide film (the number of atomic layers) can be easily adjusted. This makes it possible to control the film thickness of the aluminum oxide film in units of atomic layers. Further, in the atomic layer deposition method, even if the surface has unevenness, the film can be formed along the unevenness. For this reason, the second insulating layer 18 as shown in FIG. 8 is formed on the surfaces of the first insulating layer 19 and the electrodes 17 . In this case, it is preferable that at least the thickness of the second insulating layer 18 to be formed is 1 [nm] or more so that the respective surfaces of the first insulating layer 19 and the electrodes 17 are covered.

[Polishing process]
Subsequently, a portion of the deposited second insulating layer 18 is polished to expose the surface 17A of the electrode 17 . Specifically, the wafer 15 is supported on the support table 31 as shown in FIG. Then, the polishing wheel 32 is lowered to a predetermined position with respect to the support table 31 .

Next, the support table 31 and the polishing wheel 32 are rotated about their respective axes, and the polishing pad 33 is brought into contact with the wafer 15 to polish the surface of the wafer 15 (that is, the second insulating layer 18). At this time, it is preferable to supply the polishing liquid to the surface of the wafer 15 through the polishing liquid supply nozzle 34 .

By polishing the second insulating layer 18, the surface 15A of the wafer 15 is flattened and the surface 17A of the electrode 17 is exposed on the surface (bonding surface) 15A of the wafer 15, as shown in FIG. In this embodiment, the thickness t1 of the second insulating layer 18 formed on the first insulating layer 19 after polishing is preferably set within the range of 1 [nm]≦t1. By setting the film thickness of the second insulating layer 18 within this range, it is possible to maintain the bonding force when the pair of wafers 15 are bonded at room temperature to a predetermined threshold value (0.8 J/m ² ) or more. In addition, in this configuration, the upper limit value of the thickness t1 of the second insulating layer 18 is not defined. However, if the thickness t1 of the second insulating layer 18 is too large, the film formation time becomes long, and the polishing time until the surface of the electrode 17 is exposed becomes long. be.

[Joining process]
Subsequently, the bonding unit 13 bonds the pair of wafers 15 formed and polished as described above. Specifically, as shown in FIG. 10, a pair of wafers 15 are transferred into the bonding chamber 41 of the bonding unit 13, and one of the wafers 15 is placed on the upper stage 42 so that the front surface 15A faces vertically downward. It is supported by the electric chuck 42A. The other wafer 15 is mounted on the upper surface of the lower stage 43 so that the front surface 15A faces vertically upward. The interior of the bonding chamber 41 is maintained in a vacuum atmosphere. In this state, argon beams 44a and 45a are emitted from the fast atom beam sources 44 and 45 toward the surface 15A of each wafer 15, respectively. These argon beams 44a and 45a are irradiated to the surfaces 15A of the pair of wafers 15, respectively, to activate the surfaces 15A (bonding surfaces of the second insulating layer 18).

Next, the upper stage 42 is lowered to a position where the distance between the pair of wafers 15 respectively supported by the upper stage 42 and the lower stage 43 is a predetermined distance (eg, 50 μm to 500 μm). After the pair of wafers 15 are aligned at this position, the pressure contact mechanism 42B of the upper stage 42 is operated as shown in FIG. As a result, the electrostatic chuck 42A supporting one of the wafers 15 descends vertically downward, and the one wafer 15 and the other wafer 15 are pressed against each other, so that the pair of wafers 15 are bonded to form the semiconductor device 50. It is formed. In this bonding process, since the pair of wafers 15 can be bonded at room temperature in two steps (activation and bonding), the number of steps can be reduced and the tact time can be shortened. Moreover, since the electrodes 17 can be joined together with the surfaces 17A of the electrodes 17 exposed, foreign matter (the second insulating layer 18) can be prevented from intervening between the electrodes 17. FIG. Therefore, by reducing the electrical resistance between the electrodes 17 (0.02Ω or less), the power loss of the semiconductor device 50 (semiconductor device) can be reduced.

[Heating process]
Subsequently, the bonded semiconductor device 50 (pair of wafers 15) is heated at a predetermined temperature (for example, about 50.degree. C. to 400.degree. C.). This heating step may be performed, for example, by a heat treatment unit that includes a heating chamber, a support table that is housed in the heating chamber and supports the semiconductor device 50, and a heater (heating mechanism) that heats the semiconductor device 50. can be done. In this heating step, by heating the bonded semiconductor device 50, residual stress generated during bonding can be removed, and deformation of the semiconductor device 50 can be suppressed (annealing). Moreover, it has been found that the bonding strength of the semiconductor device 50 bonded at room temperature is improved by the heating process. Note that the function of the heat treatment unit may be provided in the film forming unit 11 or the bonding unit 13, for example, instead of the structure in which the heat treatment unit is provided separately.

FIG. 12 is a transmission electron micrograph showing a joint surface of aluminum oxide as the second insulating layer. A transmission electron microscope (TEM) is a type of electron microscope that magnifies and observes an interference image created by electrons that pass through an object under observation by illuminating it with an electron beam.

As shown in FIG. 12, the second insulating layer 18 of each wafer 15 is formed to have a film thickness of 1 [nm] or more. No voids (air gaps) are observed on the joint surfaces between the layers 18, and a sufficient adhesion state is obtained. It is considered that this is because the aluminum oxide film formed by the atomic deposition method as the second insulating layer 18 has a good surface shape and crystallinity, so that the room-temperature bonding can be performed.

FIG. 13 is a table showing the film thickness, bonding state, and bonding strength when aluminum oxide films formed by different film forming methods are bonded together. In FIG. 13, aluminum oxide films formed by mist CVD and sputtering in addition to the atomic deposition method described in this embodiment are compared.

In the atomic deposition method (ALD), an aluminum oxide film is formed on the surface 15A of the wafer 15 by the film forming process described above, and the electrode 17 is exposed on the surface 15A by the polishing process described above. The film thickness of the aluminum oxide film (second insulating layer 18) formed on the first insulating layer 19 is 2.0 [nm]. Here, the film thickness is the film thickness of the aluminum oxide film (second insulating layer) in a state before bonding, that is, after the polishing process, and is measured using, for example, a spectroscopic ellipsometer.

Mist CVD is a method of forming a film in a non-vacuum process by making a mist of a liquid raw material and transporting it onto a substrate heated to a high degree of sound. Specifically, while the wafer 15 was supported on a support table arranged in the deposition chamber, aluminum acetylacetonate (Al(C ₅ H ₇ O ₂ ) ₃ ) was used as a solute, and methanol (CH ₃ OH) and distilled water as solvents are atomized and fed into the deposition chamber. After that, the temperature of the wafer 15 is heated to 300° C. to 450° C. to form an aluminum oxide film on the surface of the wafer 15 . The film thickness in this example is 50 [nm].

Sputtering is a method of forming a film on a substrate by bombarding a target, which is a film raw material, with a rare gas element or the like that has been ionized by applying a high voltage in a vacuum space. . Specifically, a target made of aluminum oxide and the wafer 15 are placed in a vacuum chamber, a rare gas is introduced into the vacuum chamber, high-frequency power is applied to the target, and an aluminum oxide film is formed on the surface of the wafer 15 by sputtering. to form a film. The film thickness in this example is 50 [nm].

The bonding state refers to the bonding state between the aluminum oxide layers (the second insulating layers). Here, the wafers having the second insulating layer formed by each film forming method are bonded by the polishing process and the bonding process described above, and the bonded state is determined. Specifically, a semiconductor device of a predetermined size (for example, 10 cm square) tape-mounted is half-cut into 5 mm×5 mm squares using a dicing machine, and the remaining 5 mm square chips are cut. Judgment is based on the percentage of the number of chips. Half-cut refers to cutting to such an extent that the rotating circular blade of the dicing machine does not reach the tape below the bonding surface. If the bonding state is insufficient, the upper wafer separates when the wafer is half-cut, leaving no chips (only the lower side remains). Therefore, half-cutting is generally used to determine the joining state. In this embodiment, the ratio of the number of remaining chips to the total number of chips is expressed as a percentage.

The bonding strength was measured by cutting the bonded semiconductor device into a chip of 12 mm×12 mm size and subjecting the chip to a tensile test. During the test, the chip was fixed to a jig, and the load at which the chip broke was measured while changing the tensile load applied to this jig. No measurement was possible with sputtering. The mist CVD fractured at 0.3 (J/m ² ). In addition, the atomic deposition method broke at 1.0 (J/m ² ). As a result, since the atomic deposition method sufficiently exceeds the threshold value of 0.8 J/m ² of the bonding strength required for a semiconductor device, a bonding strength that can withstand use can be realized.

As described above, the method of manufacturing a semiconductor device according to the present embodiment is a method of manufacturing a semiconductor device manufactured by bonding a plurality of wafers 15 at room temperature. a step of forming a film of aluminum oxide as a second insulating layer 18; a step of activating the joint surfaces of the formed second insulating layer 18; and a step of pressing and joining them together. Therefore, unlike the conventional method, the step of forming a bonding intermediate layer by sputtering silicon in a bonding chamber is not required, so the number of steps in bonding the wafers 15 can be reduced and the takt time can be shortened. can be done.

In addition, in the film formation step, the thickness of the second insulating layer is formed to be 1 [nm] or more, so that bonding strength equal to or greater than a predetermined threshold can be exhibited.

After the film forming step, the second insulating layer 18 is polished until the electrodes 17 arranged on the surface of the wafer 15 are exposed on the surface (bonding surface) 15A. Interposition of foreign matter (second insulating layer 18) can be prevented. Therefore, by reducing the electrical resistance between the electrodes 17 (0.02Ω or less), the power loss of the semiconductor device 50 (semiconductor device) can be reduced.

In addition, since a step of heating the wafers 15 (semiconductor devices 50) to a predetermined temperature after bonding the pair of wafers 15 is provided, residual stress generated during bonding can be removed, and deformation of the semiconductor devices 50 can be suppressed. In addition, it is possible to improve the bonding strength of the semiconductor device 50 bonded at room temperature.

Further, the room temperature bonding apparatus 10 according to the present embodiment is for room temperature bonding of a plurality of wafers 15, and aluminum oxide is formed as the second insulating layer 18 on the surface 15A of each of the wafers 15 using the atomic deposition method. A film forming unit 11 for forming a film, fast atom beam sources 44 and 45 for activating the bonding surfaces of the deposited second insulating layer 18, and a pair of wafers 15 with the activated bonding surfaces facing each other. Since the bonding unit 13 for bonding by pressure bonding is provided, the conventional step of forming a bonding intermediate layer by sputtering silicon in the bonding chamber is not required. It is possible to shorten the tact time by reducing it.

In addition, since the film forming unit 11 forms the second insulating layer with a thickness of 1 [nm] or more, the semiconductor device 50 can exhibit bonding strength of a predetermined threshold value or more.

In addition, the wafer 15 has an electrode 17 arranged on the surface thereof, and the second insulating layer 18 is polished until the electrode 17 is exposed on the bonding surface of the wafer 15 on which the second insulating layer 18 is formed. Since the polishing unit 12 is provided, it is possible to prevent foreign matter (the second insulating layer 18) from intervening between the electrodes 17 when they are joined. Therefore, by reducing the electrical resistance between the electrodes 17 (0.02Ω or less), the power loss of the semiconductor device 50 (semiconductor device) can be reduced.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments.

10 room temperature bonding apparatus 11 film forming unit (film forming section)
12 polishing unit (polishing section)
13 joining unit (joint)
15 Wafer (semiconductor substrate)
15A surface (joint surface)
17 electrode (conductive material)
18 Second insulating layer (insulating layer)
19 first insulating layer 21 deposition chamber 22 support table 23 heater (heating mechanism)
31 support table 32 polishing wheel 33 polishing pad 41 bonding chamber 42 upper stage 43 lower stage 44 fast atom beam source (activation section)
45 fast atom beam source (activation part)
50 semiconductor devices

Claims (5)

A method for manufacturing a semiconductor device manufactured by bonding a plurality of semiconductor substrates at room temperature,
forming a film of aluminum oxide as an insulating layer on each of the surfaces of the plurality of semiconductor substrates using an atomic deposition method;
polishing the insulating layer until the conductive material disposed on each surface of the plurality of semiconductor substrates is exposed;
A neutral atom beam is applied to each of the bonding surfaces of the plurality of semiconductor substrates where the conductive material and the deposited insulating layer are exposed, thereby activating the conductive material and the insulating layer exposed on the bonding surfaces. process and
The conductive materials exposed on the joint surfaces of the plurality of activated semiconductor substrates and the insulating layers are opposed to each other, and the plurality of semiconductor substrates are press-contacted to each other, and the conductive materials and the insulating layers are pressed to each other. and a step of room temperature bonding , respectively;
A method of manufacturing a semiconductor device, comprising : 2. The method of manufacturing a semiconductor device according to claim 1, wherein in said film forming step, said insulating layer is formed to have a thickness of 1 [nm] or more. 3. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of heating the semiconductor substrates to a predetermined temperature after room temperature bonding of the plurality of semiconductor substrates. A room temperature bonding apparatus for room temperature bonding of a plurality of semiconductor substrates,
a deposition unit that deposits aluminum oxide as an insulating layer on each of the surfaces of the plurality of semiconductor substrates using an atomic deposition method;
a polishing unit that polishes the insulating layer until the conductive material disposed on each surface of the plurality of semiconductor substrates is exposed;
A neutral atom beam is applied to each of the bonding surfaces of the plurality of semiconductor substrates where the conductive material and the deposited insulating layer are exposed, thereby activating the conductive material and the insulating layer exposed on the bonding surfaces. an activation unit;
The conductive materials exposed on the joint surfaces of the plurality of activated semiconductor substrates and the insulating layers are opposed to each other, and the plurality of semiconductor substrates are press-contacted to each other, and the conductive materials and the insulating layers are pressed to each other. a junction for room temperature bonding of each of the
A room temperature bonding apparatus comprising: 5. The room-temperature bonding apparatus according to claim 4, wherein the film forming section forms the insulating layer with a thickness of 1 [nm] or more.

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