TW202242966A - Semiconductor device manufacturing method, and room temperature bonding device - Google Patents

Abstract

A room temperature bonding device (10) according to the present embodiment comprises: a film forming unit (11) that forms, as a second insulating layer, a film of aluminum oxide on a surface of a wafer (15), by atomic deposition; a high-speed atom beam source that activates a bonding surface of the formed second insulating layer; and a bonding unit which arranges a pair of wafers (15) such that the activated bonding surfaces face each other, and joins the pair of wafers together by pressure contact.

Description

Semiconductor device manufacturing method and room temperature bonding device

The present invention relates to a method of manufacturing a semiconductor device and a room temperature bonding device for bonding a plurality of semiconductor substrates at room temperature.

In recent years, with regard to the high integration of semiconductor devices (semiconductor devices), three-dimensional integration technology that stacks semiconductor devices of the same type or different types has attracted attention. In this three-dimensional volume technology, it is important to bond the conductive material serving as an electrode or wiring and the bonding surface of the substrate where the insulating material is exposed. In general, room temperature bonding is known as a bonding technique for two substrates. The so-called room temperature bonding refers to a technique of bonding the bonding surfaces of two substrates to be bonded by activating them in a vacuum environment and press-bonding the activated bonding surfaces to each other. In room temperature bonding, substrates can be directly bonded without heat treatment. Therefore, there are advantages in that deformation such as expansion of substrates accompanying heat treatment can be suppressed, and alignment of two substrates can be accurately performed during bonding.

In addition, in the above-mentioned room temperature bonding, although metals as conductive materials can be directly bonded to each other, it is not possible to directly bond oxide films, nitride films, etc., which are generally used as insulating materials. Therefore, the following technology has been proposed in the past: sputtering a semiconductor material (silicon) to form a bonding intermediate layer containing an amorphous semiconductor material (amorphous silicon) on the bonding surface, and bonding a conductive material and an insulating material simultaneously (hybrid bonding) ) (for example, refer to Patent Document 1). [Prior Art Literature] [Patent Document]

[Patent Document 1] Japanese Patent No. 6165127

[Problem to be solved by the invention]

However, in the conventional configuration, it is necessary to sputter silicon in the bonding chamber to form a bonding intermediate layer on the bonding surface, so the steps are complicated and lead to a longer lead time (step operation time) when bonding the substrates. question. Also, in the previous configuration, since the bonding intermediate layer (amorphous silicon) is also formed on the surface of the conductive material constituting the electrode, the bonding intermediate layer is interposed between the conductive materials after bonding, and the resistance between the conductive materials changes. big problem.

The present invention was made in view of the above problems, and an object thereof is to provide a semiconductor device manufacturing method and a room temperature bonding device that reduce the resistance between conductive materials and reduce the number of steps for bonding substrates to shorten lead times. [Technical means to solve the problem]

In order to solve the above problems and achieve the purpose, the present invention is a method of manufacturing a semiconductor device, which is characterized in that it is a method of manufacturing a semiconductor device manufactured by bonding a plurality of semiconductor substrates at room temperature, and has the following steps: using the atomic layer deposition method , respectively forming a film of aluminum oxide on the surface of the semiconductor substrate as an insulating layer; activating the joint surface of the film-formed insulating layer;

According to this configuration, by using the atomic layer deposition method, aluminum oxide is formed as an insulating layer on the surface of the plurality of semiconductor substrates, so that the step of sputtering silicon in the bonding chamber to form the bonding intermediate layer is not required. Therefore, it is possible to reduce the number of steps when bonding semiconductor substrates to shorten the lead time.

In this configuration, preferably, in the film forming step, the thickness of the insulating layer is formed to be 1 [nm] or more. In addition, after the film forming step, a step of polishing the insulating layer until the conductive material arranged on the surface of the semiconductor substrate is exposed on the bonding surface may be provided. In addition, after bonding a plurality of semiconductor substrates, a step of heating the semiconductor substrates to a specific temperature may be provided.

Also, the present invention is a room temperature bonding device, which is characterized in that it is a room temperature bonding device for bonding a plurality of semiconductor substrates at room temperature, and includes: a film forming section for forming films on the surfaces of the semiconductor substrates using an atomic layer deposition method. Alumina is used as an insulating layer; an activation part activates the bonding surface of the insulating layer after film formation; and a bonding part makes the activated bonding surfaces face each other and press-bonds a plurality of semiconductor substrates to join. According to this configuration, by having a film formation section for forming an insulating layer of aluminum oxide on the surface of a plurality of semiconductor substrates by atomic layer deposition, it is not necessary to sputter silicon in the bonding chamber to form the bonding intermediate layer. the steps. Therefore, it is possible to reduce the number of steps when bonding semiconductor substrates to shorten the lead time.

Moreover, it is preferable that the thickness of the insulating layer is formed in the film formation part to be 1 [nm] or more. In addition, it is preferable that the semiconductor substrate has a conductive material arranged on the surface, and the room temperature bonding apparatus includes a grinding unit for grinding the insulating layer on the semiconductor substrate on which the insulating layer is formed until the conductive material is exposed on the bonding surface. until. [Effect of Invention]

According to the present invention, it is possible to reduce the number of steps for bonding semiconductor substrates to shorten the lead time. In addition, compared with the conventional structure in which the bonding intermediate layer is interposed, the resistance between the conductive materials can be reduced.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, this invention is not limited by the following embodiment. In addition, the components in the following embodiments include those that can be easily and easily replaced by a manufacturer, or those that are substantially the same.

FIG. 1 is a block diagram showing a schematic configuration of a room temperature bonding apparatus according to this embodiment. Fig. 2 is a schematic diagram of a film forming unit constituting a part of the room temperature bonding apparatus. Fig. 3 is a schematic diagram of a polishing unit constituting a part of the room temperature bonding apparatus. Fig. 4 is a schematic diagram of a bonding unit constituting a part of the room temperature bonding device.

As shown in FIG. 1 , the room temperature bonding apparatus 10 is configured to include a film forming unit (film forming unit) 11 , a polishing unit (polishing unit) 12 , and a bonding unit (bonding unit) 13 . The room temperature bonding apparatus 10 uses a film forming unit 11 to form an insulating layer (second insulating layer 18 below) on the surface of a disk-shaped wafer 15 (semiconductor substrate in FIG. After grinding the surfaces (joint surfaces) of the wafers 15 , the joint surfaces of a pair (plurality) of wafers 15 are bonded to each other by the bonding unit 13 . Also between the film forming unit 11 and the polishing unit 12, and between the polishing unit 12 and the bonding unit 13, a transport mechanism 14 that automatically transports the processed wafer 15 to the next unit can be respectively provided, and it can also be set as A configuration that manually collects multiple wafers and transfers them to the next unit. In addition, the arrangement of the film forming unit 11, the polishing unit 12, and the bonding unit 13 can be appropriately changed. For example, these units can be collectively arranged in one room, or they can be arranged in different rooms or different buildings.

The film forming unit 11 forms an insulating layer (second insulating layer 18 ) including an oxide film (aluminum oxide film; Al ₂ O ₃ ) on the surface of the wafer 15 by atomic layer deposition (ALD: atomic layer deposition). device. Atomic layer deposition is a type of chemical vapor deposition (CVD: chemical vapor deposition), in which metal raw materials such as organometallic compounds and raw materials (oxidants) containing elements chemically bonded to the metal raw materials are alternately supplied to the wafer The method of forming a film on the surface of 15.

As shown in FIG. 2 , the film forming unit 11 has a film forming chamber 21 , and a circular support table 22 for supporting the wafer 15 is accommodated in the film forming chamber 21 . The support table 22 has a dielectric layer (not shown) on its upper end surface 22A, and has a mechanism for applying a voltage to the dielectric layer to attract and support the wafer 15 on the dielectric layer by electrostatic force. Moreover, the support table 22 incorporates a heater (heating mechanism) 23 for heating the supported wafer 15 to a predetermined temperature. In addition, the support stand 22 may be provided with a mechanism for rotating the support stand 22 around the axis.

Furthermore, the film forming unit 11 has: a metal raw material supply source 24 for supplying the metal raw material into the film forming chamber 21; and an oxidizing agent supply source 25 for supplying an oxidizing agent. These respective supply sources 24 and 25 are connected in parallel to the film formation chamber 21 via supply pipes 26 and 27 , respectively. Front ends 26A, 27A of the respective supply pipes 26 , 27 are respectively exposed in the film forming chamber 21 . Supply valves 26B and 27B are respectively provided in the supply pipes 26 and 27 , and by alternately opening and closing the supply valves 26B and 27B, the metal raw material and the oxidizing agent can be alternately supplied into the film formation chamber 21 . Furthermore, the metal raw material and the oxidizing agent are preferably supplied into the film forming chamber 21 together with, for example, an inert gas.

In this embodiment, as a metal raw material, for example, trimethylaluminum (TMA: trimethyl aluminum) which is an organometallic compound is used, and as an oxidizing agent, for example, water vapor (H ₂ O) is used. As the oxidizing agent, other than water vapor, oxygen (O ₂ ), ozone (O ₃ ), and hydrogen peroxide (H ₂ O ₂ ) can also be used.

In addition, the film forming unit 11 includes a vacuum pump 28 . The vacuum pump 28 is used to discharge (flush) excess metal raw materials and oxidizing agents supplied into the film forming chamber 21 , and is connected to the vacuum pump 28 and the film forming chamber 21 through a discharge pipe 29 . One end 29A of the discharge pipe 29 is exposed in the film forming chamber 21 . By operating the vacuum pump 28 while the supply valves 26B and 27B are closed, the excess metal raw material and oxidizing agent supplied into the film formation chamber 21 are discharged to the outside.

The grinding unit 12 is a device for grinding the surface of the wafer 15 . The insulating layer formed on the surface of the wafer 15 is polished by the polishing unit 12, so that the following electrodes (conductive materials) arranged on the surface of the wafer 15 can be exposed on the surface.

As shown in FIG. 3 , the polishing unit 12 includes: a circular support table 31 that supports the wafer 15 ; and a grinding wheel 32 that is disposed facing the support table 31 . The support table 31 has a dielectric layer (not shown) on its upper end surface 31A, and has a mechanism for applying a voltage to the dielectric layer and attracting and supporting the wafer 15 on the dielectric layer by electrostatic force. Moreover, the support stand 31 is equipped with the drive mechanism (not shown) which rotates this support stand 31 around an axis|shaft.

The grinding wheel 32 has: a driving mechanism (not shown), which is formed in a circular shape and rotates the grinding wheel 32 around the axis; .

A disc-shaped grinding pad 33 is installed on the lower surface of the grinding wheel 32 . As the polishing pad 33, for example, one in which abrasive grains are dispersed and fixed in a base material such as urethane or non-woven fabric is used. Further, near the grinding wheel 32, a polishing liquid supply nozzle 34 for supplying a polishing liquid to the surface of the wafer 15 is disposed. The polishing liquid is a liquid supplied when polishing the insulating layer formed on the surface of the wafer 15 , and may contain substances capable of chemically reacting with the insulating layer to perform CMP (Chemical Mechanical Polishing).

The grinding wheel 32 is arranged largely eccentrically with respect to the support table 31 . Specifically, the polishing pad 33 is disposed so as to cover at least the center of the wafer 15 and extend (expose) in the radial direction of the wafer 15 . In this state, by rotating the support table 31 and the grinding wheel 32 while supplying the polishing liquid, the polishing pad 33 partially presses the surface of the wafer 15 to perform polishing.

As shown in FIG. 4, the bonding unit 13 includes a bonding chamber 41, an upper stage 42, a lower stage 43, high-speed atomic beam sources (activation parts) 44, 45, and a vacuum exhaust. Gas device 46.

The bonding chamber 41 is a container that seals the inside to isolate it from the environment, and the vacuum exhaust device 46 exhausts gas from the inside of the bonding chamber 41 . Thereby, the inside of the bonding chamber 41 becomes a vacuum environment. Furthermore, the junction chamber 41 is equipped with the shutter (not shown) which connects or separates the internal space of this junction chamber 41 from the outside.

The upper stage 42 includes: an electrostatic chuck 42A formed in a disc shape; and a crimping mechanism 42B that moves the electrostatic chuck 42A up and down in the vertical direction. The electrostatic chuck 42A has a dielectric layer at the lower end of the circular plate, and a voltage is applied to the dielectric layer to attract and support the wafer 15 on the dielectric layer by electrostatic force. The crimping mechanism 42B moves the electrostatic chuck 42A parallel to the vertical direction relative to the lower stage 43 by the operation of the user.

The lower stage 43 is a stage that supports the wafer 15 on its upper surface, and is equipped with a transfer mechanism not shown. The transfer mechanism moves the lower stage 43 in parallel in the horizontal direction and rotates the lower stage 43 around a rotation axis parallel to the vertical direction by the user's operation. In addition, the lower stage 43 may have a dielectric layer on its upper end, and may have a mechanism for applying a voltage to the dielectric layer to attract and support the wafer 15 on the dielectric layer by electrostatic force.

High-speed atomic beam sources (FAB: Fast Atom Beam) 44 and 45 emit activated neutral atomic beams (for example, argon (Ar) atoms) on the wafer surface. One high-speed atomic beam source 44 is arranged toward the wafer 15 supported on the upper stage 42 , and the other high-speed atomic beam source 45 is arranged toward the wafer 15 supported on the lower stage 43 . The wafer 15 is activated by irradiating a neutral atom beam. In addition, instead of the high-speed atomic beam sources 44 and 45, other activation means (for example, an ion gun or plasma) may be used to activate each wafer. Also, in the example of FIG. 4 , it is configured to set up a pair of upper and lower high-speed atomic beam sources 44, 45 respectively corresponding to the upper side stage 42 and the lower side stage 43, but it may also be directed from one high-speed atomic beam source to each other. Support wafer irradiation on each stage.

Next, the semiconductor device 50 formed by bonding at room temperature using the bonding unit 13 will be described. The semiconductor device 50 is formed by stacking and bonding a plurality of wafers 15, for example, for stacking LSI (Large Scale Integration, large-scale integrated circuit) or CMOS (Complementary MOS, complementary metal oxide semiconductor) image sensing device. In the present embodiment, the structure in which the semiconductor device 50 is formed by joining a pair (two) of wafers 15 is described, but the number of wafers 15 is not limited to this.

FIG. 5 is a cross-sectional view schematically showing the structure before bonding a pair of wafers, and FIG. 6 is a cross-sectional view schematically showing the structure of a semiconductor device formed by bonding a pair of wafers. As shown in FIG. 5 , wafer 15 includes semiconductor base 16 , and electrodes 17 and second insulating layer (insulating layer) 18 disposed on semiconductor base 16 via first insulating layer (oxide film) 19 . The electrodes 17 and the second insulating layer 18 are respectively formed to be exposed on the surface 15A of the wafer 15, and the surface 15A functions as a bonding surface. The surface 17A of each wafer 15 is formed as a flat surface, and the surfaces 15A, 15A are in close contact with each other.

For the semiconductor substrate 16, for example, single crystal silicon (Si) is used. In addition, as the semiconductor substrate 16, materials such as single crystal germanium (Ge), gallium arsenide (GaAs), silicon carbide (SiC) and the like may be used instead of single crystal silicon (Si).

The first insulating layer 19 is a silicon oxide film (SiO ₂ ) formed by natural oxidation on the surface side of the semiconductor substrate 16 . In addition, as the first insulating layer 19, a silicon oxide film (SiO ₂ ) or a silicon nitride film (Si ₃ N ₄ ) may be formed using, for example, an oxidation furnace, a nitriding furnace, or a chemical vapor deposition (CVD) device. .

In addition, the electrode 17 is formed of a material having excellent electrical conductivity, for example, copper (Cu). Wiring materials are connected to the electrodes 17 to form electronic circuits or various elements.

The second insulating layer 18 includes an oxide film (aluminum oxide film, Al ₂ O ₃ ) laminated on the first insulating layer 19 . It is known that aluminum oxide films generally cannot be bonded by room temperature bonding like silicon oxide films. However, the knowledge gained by the inventors through intensive research shows that aluminum oxide films formed by atomic layer deposition can be directly bonded by bonding at room temperature.

Thereby, as shown in FIG. 6 , when bonding a pair of wafers 15 , 15 , the surfaces 15A, 15A serving as bonding surfaces face each other, and room temperature bonding is performed using the above-mentioned room temperature bonding apparatus 10 . In this case, the electrodes 17 of the respective wafers 15 are joined to each other because they are metals. Also, since the second insulating layer 18 of each wafer 15 is an aluminum oxide film formed by atomic layer deposition, the second insulating layers 18 can be bonded to each other.

Next, a method of manufacturing the semiconductor device 50 will be described. FIG. 7 is a cross-sectional view schematically showing the structure of a wafer before film formation. FIG. 8 is a cross-sectional view schematically showing the structure of a wafer after film formation. FIG. 9 is a cross-sectional view schematically showing the structure of a polished wafer. 10 and 11 are explanatory diagrams showing steps of bonding a pair of wafers.

As shown in FIG. 7 , the wafer 15 is manufactured in advance through other working steps in a state where the electrodes 17 and the first insulating layer 19 are respectively exposed on the surface of the semiconductor substrate 16 . Here, the height position of the surface 17A of the electrode 17 is formed higher than the height position of the surface 19A of the first insulating layer 19 . This height position difference t corresponds to the thickness (height) of the second insulating layer 18 described below.

[Film Formation Step] The second insulating layer 18 was formed on the wafer 15 to be described above by atomic layer deposition. In the wafer 15, the first insulating layer (such as SiO ₂ ) 19 and the electrode 17 including the natural oxide film are exposed on the surface of the semiconductor substrate 16, so the second insulating layer is formed on the first insulating layer 19 and the electrode 17. 18 overlapping films.

Specifically, when forming an aluminum oxide film as the second insulating layer 18 on the wafer 15 , the wafer 15 is housed in the film forming chamber 21 and supported on the support table 22 as shown in FIG. 2 . Then, the supply valve 26B is opened, and trimethylaluminum (TMA) is supplied from the metal raw material supply source 24 to the film formation chamber 21 through the supply pipe 26, so that the surface of the wafer 15 (the surface of the first insulating layer 19 and the surface of the electrode 17 ) to adsorb TMA.

TMA has the property of not over-depositing when completely covering the surface of the wafer 15 . Therefore, a monomolecular film of TMA or its decomposition product is formed on the surface of the wafer 15 . Here, preferably, the wafer 15 is heated by the heater 23 and kept at a specific temperature (for example, 200˜400° C.). Thereby, the following oxidation and detachment of methyl groups can be stably generated on the wafer 15 .

Next, the supply valve 26B is closed to stop the supply of TMA, and the vacuum pump 28 is operated. Thereby, excess TMA supplied into the film formation chamber 21 is discharged to the outside. Then, the vacuum pump 28 is stopped, the supply valve 27B is opened, and water vapor (H ₂ O) is supplied as an oxidizing agent from the oxidizing agent supply source 25 into the film forming chamber 21 through the supply pipe 27 . Thereby, on the surface of the wafer 15, the aluminum atoms contained in the monomolecular film of TMA or its decomposition product are oxidized and the methyl group is detached. After all the aluminum atoms in the monomolecular film are oxidized, the oxygen atoms contained in the oxidizing agent will not be excessively adsorbed on the surface of the wafer 15 . Therefore, a monomolecular film of aluminum oxide can be formed on the surface of the wafer 15 (the surface of the first insulating layer 19 and the electrode 17).

With respect to the supply valve 27B, the supply of water vapor is stopped, and the vacuum pump 28 is operated. Thereby, excess water vapor supplied into the film forming chamber 21 is discharged to the outside. In this way, after water vapor is removed from the film-forming chamber 21, the supply valve 26B is opened again to supply TMA to the film-forming chamber 21, and a monomolecular film of TMA or its decomposition product is deposited on the surface of the wafer 15. on the alumina monolayer. By repeating this step, aluminum atomic layers and oxygen atomic layers are alternately deposited, so that a high-quality aluminum oxide film that is dense and free of oxygen defects can be obtained. Also, by adjusting the number of repetitions of these steps, the film thickness of the aluminum oxide film (number of atomic layers) can be easily adjusted. Thereby, the film thickness of the aluminum oxide film can be controlled in units of atomic layers. In addition, in the atomic layer deposition method, even if there are irregularities on the surface, a film can be formed along the irregularities. Therefore, the second insulating layer 18 as shown in FIG. 8 is formed on the surfaces of the first insulating layer 19 and the electrode 17 . In this case, it is preferable to set the thickness of the second insulating layer 18 to be formed to at least 1 [nm] so as to cover the respective surfaces of the first insulating layer 19 and the electrode 17 .

[grinding procedure] Next, a part of the formed second insulating layer 18 is polished to expose the surface 17A of the electrode 17 . Specifically, the wafer 15 is supported on the support table 31 as shown in FIG. 3 with the side on which the second insulating layer 18 is formed as the upper surface. Then, the grinding wheel 32 is lowered to a specific position relative to the support table 31 .

Next, the support table 31 and the grinding wheel 32 are respectively rotated around the axis, and the polishing pad 33 is brought into contact with the wafer 15 to grind the surface of the wafer 15 (that is, the second insulating layer 18 ). At this time, it is preferable to supply the polishing liquid to the surface of the wafer 15 through the polishing liquid supply nozzle 34 .

By polishing the second insulating layer 18 , as shown in FIG. 9 , the surface 15A of the wafer 15 becomes flat and the surface 17A of the electrode 17 is exposed on the surface (bonding surface) 15A of the wafer 15 . In this embodiment, preferably, the thickness t1 of the second insulating layer 18 formed on the first insulating layer 19 after polishing is set within the range of 1 [nm]≦t1. By setting the film thickness of the second insulating layer 18 within this range, the bonding force when the pair of wafers 15 are bonded at room temperature can be maintained at or above a specific threshold (0.8 J/m ² ). In addition, in this structure, the upper limit of the thickness t1 of the 2nd insulating layer 18 is not prescribed|regulated. However, if the thickness t1 of the second insulating layer 18 is too thick, the film formation time becomes longer, and the polishing time until the surface of the electrode 17 is exposed becomes longer, so the upper limit value is appropriately determined taking into account these two conditions. .

[joining procedure] Next, the pair of wafers 15 formed and polished as described above are bonded by the bonding unit 13 . Specifically, as shown in FIG. 10 , a pair of wafers 15 are transported into the bonding chamber 41 of the bonding unit 13 , and one wafer 15 is supported on the electrostatic surface of the upper stage 42 with the surface 15A facing vertically downward. Suction cup 42A. Further, another wafer 15 is placed on the upper surface of the lower stage 43 so that the surface 15A faces vertically upward. The inside of the bonding chamber 41 is maintained in a vacuum environment. In this state, argon beams 44a, 45a are emitted from high-speed atomic beam sources 44, 45 toward the surface 15A of each wafer 15, respectively. These argon beams 44a, 45a are respectively irradiated to the surface 15A of the pair of wafers 15, and the surface 15A (joint surface of the second insulating layer 18) is activated.

Next, the upper stage 42 is lowered to a position where the interval between the pair of wafers 15 supported by the upper stage 42 and the lower stage 43 becomes a predetermined interval (for example, 50 μm to 500 μm). Then, after the pair of wafers 15 are aligned at this position, as shown in FIG. 11 , the pressure bonding mechanism 42B of the upper stage 42 is operated. Thereby, the electrostatic chuck 42A supporting one wafer 15 descends vertically downward, and the one wafer 15 is pressed against the other wafer 15 , so that the pair of wafers 15 are bonded together to form the semiconductor device 50 . In this bonding step, since the pair of wafers 15 are bonded at room temperature in two steps (activation and bonding), the number of steps can be reduced and lead time can be shortened. Moreover, since the electrodes 17 can be bonded to each other with the surfaces 17A of the electrodes 17 exposed, it is possible to prevent interposition of foreign matter (second insulating layer 18 ) between the electrodes 17 . Therefore, the resistance between the electrodes 17 is reduced (0.02 Ω or less), and the power loss of the semiconductor device 50 (semiconductor device) can be reduced.

[Heating step] Next, the bonded semiconductor device 50 (a pair of wafers 15 ) is heated at a predetermined temperature (for example, about 50° C. to 400° C.). This heating step can be performed, for example, by using a heat treatment unit that includes: a heating chamber; a support table that is housed in the heating chamber and supports the semiconductor device 50; and a heater (heating mechanism) that holds the semiconductor device 50 heating. In this heating step, by heating the bonded semiconductor device 50, residual stress generated during bonding can be removed, and deformation of the semiconductor device 50 can be suppressed (annealing treatment). Also, it is clear that the bonding strength of the semiconductor device 50 bonded at room temperature is improved by the heating step. In addition, instead of having the above-mentioned heat treatment unit separately, for example, the film forming unit 11 or the bonding unit 13 may have the function of the heat treatment unit.

Fig. 12 is a transmission electron micrograph showing the bonding surface of alumina as the second insulating layer. Transmission Electron Microscope (TEM: Transmission Electron Microscope) is an electron microscope in the form of irradiating electron beams to the observation object, magnifying the interference image formed by the electrons passing through the observation object, and observing it.

As shown in FIG. 12 , the second insulating layer 18 of each wafer 15 is formed with a film thickness of 1 [nm] or more, between the first insulating layer 19 and the second insulating layer 18, and between the second insulating layers 18. No voids were observed on the joint surface, and it was in a state of sufficient close contact. It is considered that aluminum oxide as the second insulating layer 18 is formed by atomic layer deposition, and the surface shape and crystallinity are good, so bonding by room temperature bonding is possible.

FIG. 13 is a graph showing the film thickness, bonding state, and bonding strength when aluminum oxide films formed by different film-forming methods are bonded together. In this FIG. 13 , in addition to the atomic layer deposition method described in this embodiment mode, the case of forming an aluminum oxide film by spray CVD and sputtering is shown for comparison.

In the atomic layer deposition (ALD), an aluminum oxide film is formed on the surface 15A of the wafer 15 through the above-mentioned film-forming step, and the electrodes 17 are exposed on the surface 15A through the above-mentioned polishing step. Also, the film thickness of the aluminum oxide film (second insulating layer 18 ) formed on the first insulating layer 19 was 2.0 [nm]. Here, the film thickness refers to the state before joining, that is, the film thickness of the aluminum oxide film (second insulating layer) after the polishing step, and is measured, for example, using a spectroscopic ellipsometer.

The so-called spray CVD refers to a method in which a liquid material is made into a mist (spray) and transported to a substrate heated to a high temperature, and a film is formed by a non-vacuum process. Specifically, aluminum acetylacetonate (Aluminum acetylacetonate: Al( _{C5H7O2 ) 3 )} The liquid raw material (raw material solution) in which methanol (CH ₃ OH) and distilled water are solvents is supplied into the film forming chamber in the form of mist. Then, the temperature of the wafer 15 is heated to 300° C. to 450° C., and an aluminum oxide film is formed on the surface of the wafer 15 . The film thickness in this example is 50 [nm].

The so-called sputtering refers to a method of forming a film on a substrate by splashing atoms on the surface of the target by applying a high voltage to cause the ionized rare gas elements to collide with the target used as the film material. Specifically, an aluminum oxide target and a wafer 15 are placed in a vacuum chamber, a rare gas is introduced into the vacuum chamber, high-frequency power is applied to the target, and an aluminum oxide film is formed on the surface of the wafer 15 by sputtering. . The film thickness in this example is 50 [nm].

The joined state refers to the joined state between aluminum oxides (the second insulating layers). Here, the wafers having the second insulating layer formed by the respective film-forming methods were bonded by the aforementioned grinding step and bonding step, and the bonding state was determined. Specifically, in the state where a semiconductor device of a specific size (for example, 10 cm square) is tape-mounted, using a dicing device, half-cut into a 5 mm×5 mm square, and the number of remaining chips is compared to the cut out 5 mm. The ratio of the total number of wafers per square is judged. The so-called half-cut means that the rotary circular knife of the cutting device cuts to the extent that it is lower than the joint surface and does not reach the tape. If the bonding state is not sufficient, the wafer on the upper side will be detached during half-cutting and the wafer will not remain (only the lower side will remain). Therefore, half-cut is generally used for judging the joining state. In this embodiment, the ratio of the number of remaining wafers to the total number of wafers is expressed in %. For example, if it is less than 20%, it is judged as x, if it is more than 20% and less than 100%, it is judged as △, and 100% is judged as 〇.

The bonding strength was measured by dicing the bonded semiconductor device into wafers with a size of 12 mm×12 mm, and performing a tensile test on the wafers. During the test, the wafer is fixed on the jig, and the tensile load on the jig is changed while the load when the wafer breaks is measured. It cannot be measured by the sputtering method. If the spray CVD method is used, it breaks at 0.3 (J/m ² ). Also, when the atomic layer deposition method is used, it breaks at 1.0 (J/m ² ). Thereby, in the atomic layer deposition method, since the threshold value 0.8 J/m ² of the bonding strength required as a semiconductor device is sufficiently exceeded, durable bonding strength can be realized.

As described above, the method for manufacturing a semiconductor device in this embodiment is a method for manufacturing a semiconductor device by bonding a plurality of wafers 15 at room temperature, and includes the following steps: using the atomic layer deposition method to form wafers on the surfaces of the wafers. A film of aluminum oxide is used as the second insulating layer 18; the bonding surfaces of the formed second insulating layer 18 are activated; Therefore, there is no need to sputter silicon in the bonding chamber to form the bonding intermediate layer as before, so the number of steps when bonding the wafer 15 can be reduced to shorten the lead time.

In addition, since the thickness of the second insulating layer is formed to be 1 [nm] or more in the film forming step, it is possible to exhibit a bonding strength of more than a certain threshold value.

After the film forming step, there is a step of polishing the second insulating layer 18 until the electrodes 17 arranged on the surface of the wafer 15 are exposed on the surface (bonding surface) 15A, so that it is possible to prevent interference between the electrodes 17 during bonding. foreign matter (second insulating layer 18). Therefore, the resistance between the electrodes 17 is reduced (0.02 Ω or less), and the power loss of the semiconductor device 50 (semiconductor device) can be reduced.

In addition, since the wafer 15 (semiconductor device 50 ) is heated to a specific temperature after the pair of wafers 15 are bonded, residual stress generated during bonding can be removed and deformation of the semiconductor device 50 can be suppressed. , and the improvement of the bonding force of the semiconductor device 50 bonded at room temperature can be realized.

In addition, the room temperature bonding apparatus 10 of this embodiment is for bonding a plurality of wafers 15 at room temperature, and includes: a film forming unit 11 for forming a film of aluminum oxide on the surface 15A of the wafer 15 as the first film by atomic layer deposition. 2 insulating layer 18; high-speed atomic beam sources 44, 45, which activate the bonding surface of the second insulating layer 18 after film formation; and a bonding unit 13, which makes the activated bonding surfaces face each other and separates a pair of wafers 15 are bonded by pressing each other; therefore, there is no need to sputter silicon in the bonding chamber to form a bonding intermediate layer as before, so the number of steps when bonding the wafers 15 can be reduced and the lead time can be shortened.

In addition, since the film forming unit 11 forms the thickness of the second insulating layer to be 1 [nm] or more, the semiconductor device 50 can exhibit a junction strength of a certain threshold or more.

In addition, the wafer 15 has electrodes 17 disposed on the surface, and is equipped with a polishing unit 12 for polishing the second insulating layer 18 on the wafer 15 on which the second insulating layer 18 is formed until the electrodes 17 are exposed on the wafer 15. Therefore, it is possible to prevent foreign matter (second insulating layer 18 ) from being interposed between electrodes 17 at the time of bonding. Therefore, the resistance between the electrodes 17 is reduced (0.02 Ω or less), and the power loss of the semiconductor device 50 (semiconductor device) can be reduced.

As mentioned above, although embodiment of this invention was described, this invention is not limited to the said embodiment.

10:Room temperature bonding device 11: Film forming unit (film forming part) 12: Grinding unit (grinding part) 13: Joining unit (Joint part) 15: Wafer (semiconductor substrate) 15A: Surface (Joint Surface) 16: Semiconductor substrate 17: Electrode (conductive material) 17A: Surface 18: The second insulation layer (insulation layer) 19: The first insulating layer 21: Film forming chamber 22: Support Desk 22A: Upper end face 23: heater (heating mechanism) 24: Metal raw material supply source 25: Oxidant supply source 26: Supply piping 26A: front end 26B: supply valve 27: Supply piping 27A: front end 27B: supply valve 28: Vacuum pump 29: discharge pipe 29A: one end 31: Support Desk 31A: Upper end face 32: Grinding wheel 33: Grinding pad 41: Bonding chamber 42: Upper side stage 42A: Electrostatic Chuck 42B: crimping mechanism 43: lower side loading platform 44: High-speed atomic beam source (activation part) 45: High-speed atomic beam source (activation part) 46: Vacuum exhaust device 50:Semiconductor device

FIG. 1 is a block diagram showing a schematic configuration of a room temperature bonding apparatus according to this embodiment. Fig. 2 is a schematic diagram of a film forming unit constituting a part of the room temperature bonding apparatus. Fig. 3 is a schematic diagram of a polishing unit constituting a part of the room temperature bonding apparatus. Fig. 4 is a schematic diagram of a bonding unit constituting a part of the room temperature bonding device. FIG. 5 is a cross-sectional view schematically showing the configuration of a pair of wafers before bonding. FIG. 6 is a cross-sectional view schematically showing the configuration of a semiconductor device formed by bonding a pair of wafers. FIG. 7 is a cross-sectional view schematically showing the structure of a wafer before film formation. FIG. 8 is a cross-sectional view schematically showing the structure of a wafer after film formation. FIG. 9 is a cross-sectional view schematically showing the structure of a polished wafer. FIG. 10 is an explanatory view showing a step of bonding a pair of wafers. FIG. 11 is an explanatory view showing a step of bonding a pair of wafers. Fig. 12 is a transmission electron micrograph showing the bonding surface of alumina as the second insulating layer. FIG. 13 is a graph showing the film thickness, bonding state, and bonding strength when aluminum oxide films formed by different film-forming methods are bonded together.

11: Film forming unit (film forming part)

15: Wafer (semiconductor substrate)

21: Film forming chamber

22: Support Desk

22A: Upper end face

23: heater (heating mechanism)

24: Metal raw material supply source

25: Oxidant supply source

26: Supply piping

26A: front end

26B: supply valve

27: Supply piping

27A: front end

27B: supply valve

28: Vacuum pump

29: discharge pipe

29A: one end

Claims (8)

A method of manufacturing a semiconductor device, characterized in that it is a method of manufacturing a semiconductor device manufactured by bonding a plurality of semiconductor substrates at room temperature, and includes the following steps: Using the atomic layer deposition method to form a film of aluminum oxide on the surface of the above-mentioned semiconductor substrate as an insulating layer; activating the bonding surface of the above insulating layer after film formation; and A plurality of the above-mentioned semiconductor substrates are pressure-bonded to each other and bonded by making the above-mentioned bonding surfaces after activation face each other. The method of manufacturing a semiconductor device according to claim 1, wherein in the film forming step, the thickness of the insulating layer is formed to be 1 [nm] or more. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of polishing the insulating layer until the conductive material arranged on the surface of the semiconductor substrate is exposed on the bonding surface after the film forming step. The method of manufacturing a semiconductor device according to claim 2, further comprising a step of polishing the insulating layer until the conductive material arranged on the surface of the semiconductor substrate is exposed on the bonding surface after the film forming step. The method of manufacturing a semiconductor device according to any one of claims 1 to 4, which includes the step of heating the semiconductor substrates to a specific temperature after joining the plurality of semiconductor substrates. A room temperature bonding device, characterized in that it is a room temperature bonding device for bonding a plurality of semiconductor substrates at room temperature, and includes: The film forming part, which uses atomic layer deposition method to form films of aluminum oxide on the surface of the above-mentioned semiconductor substrate as insulating layers; an activation part for activating the bonding surface of the insulating layer after film formation; and The bonding part is such that the activated bonding surfaces face each other, and the plurality of semiconductor substrates are pressure-bonded and bonded. The room temperature bonding device according to claim 6, wherein the film forming section forms the insulating layer to a thickness of 1 [nm] or more. The room temperature bonding device according to claim 6 or 7, wherein the above-mentioned semiconductor substrate has a conductive material disposed on the surface, and This room temperature bonding apparatus includes a polishing unit for polishing the insulating layer on the semiconductor substrate on which the insulating layer is formed until the conductive material is exposed on the bonding surface.

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