JP2016090827A - Electro-optic device, method for manufacturing electro-optic device, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electro-optic device having a light-shielding structure which can surely suppress occurrence of a light leakage current in a thin film transistor; a method for manufacturing an electro-optic device; and electronic equipment.SOLUTION: An element substrate 10 in an electro-optic device includes: a second interlayer insulation film 11c provided on an upper layer side of a thin film transistor (TFT 30) on a substrate 10s; a recessed portion 11e which is provided on the second interlayer insulation film 11c, is recessed toward a semiconductor layer 30a of the TFT 30, and includes a reversely-tapered side wall 11d arranged on the outside in a region having the semiconductor layer 30a provided therein; a light-shielding layer 41 provided on the second interlayer insulation film 11c so as to cover at least the side wall 11d; and a relay layer 4 which is laminated on the region having the semiconductor layer 30a provided therein and the recessed portion 11e having the light-shielding layer 41 provided therein in a planar manner, and acts as a light-shielding wiring layer. Diffraction light generated by making light incident on the end of the relay layer 4 is shielded by the light-shielding layer 41 provided on the side wall 11d of the recessed portion 11e.SELECTED DRAWING: Figure 7

Description

  The present invention relates to an electro-optical device, a method for manufacturing the electro-optical device, and an electronic apparatus.

  As an electro-optical device, an active drive type liquid crystal device including a transistor that controls switching of a pixel electrode can be given. Since the liquid crystal device is a light receiving type, an illumination device is used to make the display easier to see. On the other hand, it is known that when light emitted from a lighting device is incident on a semiconductor layer (particularly a channel region) constituting a transistor, the semiconductor layer is excited by incident light and a light leakage current flows. Since the electrical characteristics of the transistor change due to the occurrence of light leakage current and a desired switching state cannot be obtained, various light shielding structures for shielding unnecessary light incident on the transistor have been proposed.

For example, in Patent Document 1, on a substrate, an interlayer insulating film stacked on at least one of an upper layer side and a lower layer side with respect to a semiconductor layer of a thin film transistor, and a semiconductor layer of the interlayer insulating film are stacked on the opposite side of the semiconductor layer. A light-shielding film that shields the channel region, and a recess that is locally depressed toward the semiconductor layer is formed on the surface of the semiconductor layer of the interlayer insulating film in a region where at least the edge of the channel region can be shielded An electro-optical device in which the light shielding film is formed at least in the recess is disclosed.
According to Patent Document 1, the film thickness of the interlayer insulating film between the light shielding film and the channel region becomes thinner than other portions by providing the recess, and the light shielding property is improved because the light shielding film approaches the channel region. If so.

JP 2006-10859 A

  However, it is said that the occurrence of light leakage current may not be reliably suppressed only by arranging the light shielding film so as to face the channel region in the semiconductor layer with the interlayer insulating film interposed therebetween as in Patent Document 1. There was a problem.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

  [Application Example] An electro-optical device according to this application example includes a substrate, a transistor provided on the substrate, a pixel electrode provided on the substrate and driven by the transistor, and an upper layer side of the transistor. An interlayer insulating film provided, a recess provided in the interlayer insulating film, recessed toward the semiconductor layer of the transistor, and having a reverse-tapered sidewall disposed outside the region where the semiconductor layer is provided; A light-shielding wiring layer laminated on the light-shielding layer provided on the interlayer insulating film so as to cover at least the side wall, the region in which the semiconductor layer is provided in a plan view, and the recess in which the light-shielding layer is provided. It is characterized by having.

  According to this application example, even if light enters the end portion of the wiring layer and diffracted light is generated, and the diffracted light is refracted toward the semiconductor layer side of the transistor, the refracted diffracted light is a recess located immediately below the wiring layer. Incident on the side wall. Since the light shielding layer is provided on the side wall, the diffracted light hardly enters the semiconductor layer of the transistor. In addition, the wiring layer is provided by being laminated in a planar area where the semiconductor layer is provided and a recess provided with a light shielding layer on the side wall, and has a light shielding property. Is also reliably shielded from light. That is, it is possible to provide an electro-optical device capable of suppressing a light leakage current from flowing through the transistor due to diffracted light at the end of the wiring layer and realizing a stable driving state.

In the electro-optical device according to the application example, the concave portion is provided to include a region where the semiconductor layer is provided in a plane.
According to this configuration, the light incident on the semiconductor layer can be reliably shielded by the wiring layer covering the recess.

In the electro-optical device according to the application example, the recess may be provided in a portion along an outer edge of a region where the wiring layer is provided.
According to this configuration, it is possible to suppress the influence of diffracted light generated at all outer edges of the wiring layer.

In the electro-optical device according to the application example, it is preferable that the wiring layer includes a layer made of metal, and the light shielding layer is made of a nitride of the metal.
According to this configuration, since the nitride of the metal is more excellent in light absorption than the metal, the light incident on the light shielding layer can be prevented from being reflected and directed to the semiconductor layer.

In the electro-optical device according to the application example, the wiring layer includes a first layer made of a metal and a second layer made of the metal nitride, and the light shielding layer is constituted by the second layer. It may be.
According to this configuration, since the light shielding layer is included in the wiring layer, it is not necessary to provide a special light shielding layer that covers the side wall of the recess, and the light shielding structure can be simplified.

  [Application Example] A method for manufacturing an electro-optical device according to this application example is a method for manufacturing an electro-optical device having a transistor and a pixel electrode driven by the transistor on a substrate. A step of forming a transistor; a step of forming an interlayer insulating film covering the transistor; and a recess having a reverse-tapered sidewall disposed outside a region overlapping the semiconductor layer of the transistor in plan view. A step of forming a light shielding layer covering at least the side wall, and a planarly laminated light-shielding wiring layer in the region where the semiconductor layer is formed and the concave portion where the light-shielding layer is formed And a step of forming the structure.

  According to this application example, light enters the end of the wiring layer to generate diffracted light, and the refracted diffracted light is formed directly under the wiring layer even if the diffracted light is refracted to the semiconductor layer side of the transistor. The light enters the side wall of the recess. Since the light shielding layer is formed on the side wall, the diffracted light does not easily enter the semiconductor layer of the transistor. In addition, the wiring layer is formed by laminating the planarly formed region of the semiconductor layer and the recess having the light shielding layer formed on the side wall, and has a light shielding property. Therefore, the light incident on the wiring layer itself Is also reliably shielded from light. That is, it is possible to manufacture an electro-optical device capable of suppressing a light leakage current from flowing through the transistor due to diffracted light at the end of the wiring layer and realizing a stable driving state.

In the electro-optical device manufacturing method according to the application example, the step of forming the recess includes forming the recess in a region including a region where the semiconductor layer is planarly formed.
According to this method, light incident on the semiconductor layer can be reliably shielded by the wiring layer formed so as to cover the recess.

In the method of manufacturing the electro-optical device according to the application example, the step of forming the concave portion may form the concave portion in a portion along an outer edge of a region where the wiring layer is formed.
According to this method, since the recesses are formed along all the outer edges of the wiring layer, the influence of diffracted light generated at the end of the wiring layer can be reliably suppressed.

In the method for manufacturing the electro-optical device according to the application example, it is preferable that the light shielding layer is formed using a metal nitride in the step of forming the light shielding layer.
According to this method, the nitride of the metal is more excellent in light absorption than the metal, so that an electro-optical device capable of suppressing the light incident on the light shielding layer from being reflected and directed to the semiconductor layer is manufactured. be able to.

In the method of manufacturing the electro-optical device according to the application example, the step of forming the wiring layer includes a step of forming the light shielding layer using a metal nitride, and a step of laminating the light shielding layer using the metal. And a step of forming a metal layer.
According to this method, since the light shielding layer is also formed in the step of forming the wiring layer, the light shielding structure can be formed efficiently. Further, since the nitride of the metal is more excellent in light absorption than the metal, the light incident on the light shielding layer can be prevented from being reflected and directed to the semiconductor layer, and the light shielding which is a metal nitride is also possible. Since the metal layer of the metal is stacked on the layer, an electrically stable and low resistance wiring layer can be formed.

  [Application Example] An electronic apparatus according to this application example includes the electro-optical device according to the application example described above.

[Application Example] An electronic apparatus according to this application example includes an electro-optical device manufactured using the method of manufacturing an electro-optical device described in the application example.
According to these application examples, since the electro-optical device having the light-shielding structure that can suppress the generation of the light leakage current in the transistor is provided, an electronic apparatus that can obtain a stable driving state in display can be provided.

(A) is a schematic plan view which shows the structure of a liquid crystal device, (b) is a schematic sectional drawing in alignment with the H-H 'line | wire of the liquid crystal device shown to (a). FIG. 3 is an equivalent circuit diagram illustrating an electrical configuration of the liquid crystal device. The schematic plan view which shows arrangement | positioning of a pixel. FIG. 2 is a schematic plan view showing the arrangement of thin film transistors, electrodes related to the thin film transistors, and scanning lines in the pixel. FIG. 3 is a schematic plan view showing an arrangement of data lines, storage capacitors and the like in a pixel. FIG. 6 is a schematic cross-sectional view showing the structure of an element substrate taken along line A-A ′ in FIG. 5. FIG. 5 is a schematic cross-sectional view showing the structure of an element substrate taken along line B-B ′ in FIG. 4. (A)-(c) is a schematic sectional drawing which shows the manufacturing method of an element substrate. (D)-(f) is a schematic sectional drawing which shows the manufacturing method of an element substrate. (A)-(c) is a schematic sectional drawing which shows the manufacturing method of the element substrate of a modification. The schematic plan view which shows arrangement | positioning of the relay layer and recessed part in the element substrate of 2nd Embodiment. FIG. 12 is a schematic cross-sectional view showing the structure of an element substrate taken along line C-C ′ in FIG. 11. Schematic which shows the structure of a projection type display apparatus.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described with reference to the drawings. Note that the drawings to be used are appropriately enlarged or reduced so that the part to be described can be recognized.

  In the present embodiment, an active drive type liquid crystal device including a thin film transistor (hereinafter referred to as TFT) for each pixel will be described as an example of an electro-optical device. This liquid crystal device can be suitably used, for example, as a light modulation element (liquid crystal light valve) of a projection display device (liquid crystal projector) described later.

(First embodiment)
<Electro-optical device>
First, the configuration of a liquid crystal device as an electro-optical device of the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1A is a schematic plan view showing the configuration of the liquid crystal device, and FIG. 1B is a schematic cross-sectional view along the line HH ′ of the liquid crystal device shown in FIG. FIG. 2 is an equivalent circuit diagram showing an electrical configuration of the liquid crystal device.

  As shown in FIGS. 1A and 1B, a liquid crystal device 100 according to the present embodiment includes an element substrate 10 and a counter substrate 20 that are arranged to face each other, and a liquid crystal layer 50 that is sandwiched between the pair of substrates. Have. As the base material 10s of the element substrate 10 and the base material 20s of the counter substrate 20, for example, a quartz substrate or a glass substrate having translucency is used. Note that translucency in this specification refers to a property of transmitting light having a wavelength in the visible light region by at least 85%.

  The element substrate 10 is slightly larger than the counter substrate 20. The element substrate 10 and the counter substrate 20 are bonded together via a sealing material 40 arranged in a frame shape along the outer edge portion of the counter substrate 20, and liquid crystal having positive or negative dielectric anisotropy is enclosed in the gap. Thus, the liquid crystal layer 50 is configured. As the sealing material 40, for example, an adhesive such as a thermosetting or ultraviolet curable epoxy resin is employed. A spacer (not shown) is mixed in the sealing material 40 to keep the distance between the pair of substrates constant.

  Inside the sealing material 40, a display region E in which a plurality of pixels P are arranged in a matrix is provided. The counter substrate 20 is provided with a parting portion 21 that surrounds the display area E between the sealing material 40 and the display area E. The parting portion 21 is made of, for example, a light shielding metal or metal oxide. Note that the display area E may include dummy pixels arranged so as to surround the plurality of pixels P in addition to the plurality of pixels P contributing to display.

  The element substrate 10 is provided with a terminal portion in which a plurality of external connection terminals 104 are arranged. A data line driving circuit 101 is provided between the first side portion along the terminal portion of the element substrate 10 and the sealing material 40. In addition, an inspection circuit 103 is provided between the sealing material 40 and the display area E along the second side facing the first side. Further, a scanning line driving circuit 102 is provided between the seal material 40 and the display region E along the third side and the fourth side that are orthogonal to the first side and face each other. A plurality of wirings 105 that connect the two scanning line driving circuits 102 are provided between the sealing material 40 on the second side and the inspection circuit 103.

  Wirings connected to the data line driving circuit 101 and the scanning line driving circuit 102 are connected to a plurality of external connection terminals 104 arranged along the first side portion. Hereinafter, the direction along the first side is referred to as the X direction, and the direction along the third and fourth sides is referred to as the Y direction. Further, in this specification, viewing from the normal direction of the counter substrate 20 orthogonal to the X direction and the Y direction is referred to as “planar view” or “planar”.

  As shown in FIG. 1B, the element substrate 10 includes a base material 10s, a TFT 30 formed on the surface of the base material 10s on the liquid crystal layer 50 side, the pixel electrode 15, and an alignment film 18 that covers the pixel electrode 15 and the like. have. The TFT 30 and the pixel electrode 15 are components of the pixel P. Details of the pixel P will be described later.

  The counter substrate 20 includes a base material 20s, a parting portion 21, a planarization layer 22, a counter electrode 23, an alignment film 24, and the like, which are sequentially stacked on the surface of the base material 20s on the liquid crystal layer 50 side.

  The parting part 21 surrounds the display area E as shown in FIG. 1A, and is provided at a position overlapping the scanning line driving circuit 102 and the inspection circuit 103 in plan view. Thus, the light incident on the peripheral circuit including these drive circuits from the counter substrate 20 side is blocked, and the peripheral circuit has a role of preventing malfunction due to the light. Further, unnecessary stray light is shielded so as not to enter the display area E, and a high contrast in the display of the display area E is ensured.

  The planarization layer 22 is made of an inorganic material such as silicon oxide, for example, and is provided so as to cover the parting portion 21 with translucency. Such a planarization layer 22 is a silicon oxide film formed by using, for example, a plasma CVD method, and has a thickness that can relax the surface unevenness of the counter electrode 23 formed on the planarization layer 22. Have.

  The counter electrode 23 is made of a transparent conductive film such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), for example, covers the planarization layer 22 and is formed at the four corners of the counter substrate 20 as shown in FIG. The vertical conduction portion 106 provided is electrically connected to the wiring on the element substrate 10 side.

  The alignment film 18 that covers the pixel electrode 15 and the alignment film 24 that covers the counter electrode 23 are set based on the optical design of the liquid crystal device 100, and an oblique deposition film (inorganic alignment film) of an inorganic material such as silicon oxide is used. It has been adopted. The alignment films 18 and 24 may employ an organic alignment film such as polyimide in addition to the inorganic alignment film.

  Such a liquid crystal device 100 is a transmission type, and adopts an optical design of a normally white mode in which the pixel P is brightly displayed when not driven and a normally black mode in which the pixel P is darkly displayed when not driven. Polarizing elements are arranged and used according to the optical design on the light incident side and the light exit side, respectively.

  Next, the electrical configuration of the liquid crystal device 100 will be described with reference to FIG. The liquid crystal device 100 includes a plurality of scanning lines 3 and a plurality of data lines 6 a as signal lines that are insulated and orthogonal to each other at least in the display region E, and a capacitor line 7. In FIG. 2, the capacitor line 7 is shown so as to be parallel to the data line 6a. However, in this embodiment, one capacitor electrode of a pair of capacitor electrodes of the storage capacitor 16 described later is the capacitor line 7. It is comprised so that the function of may be fulfilled.

  A pixel electrode 15, a TFT 30, and a storage capacitor 16 are provided in a region divided by the scanning line 3 and the data line 6a, and these constitute a pixel circuit of the pixel P.

  The scanning line 3 is electrically connected to the gate of the TFT 30, the data line 6 a is electrically connected to the first source / drain region of the TFT 30, and the pixel electrode 15 is electrically connected to the second source / drain region of the TFT 30. Has been.

  The data line 6a is connected to the data line driving circuit 101 (see FIG. 1). Image signals D1, D2,..., Dn are supplied from the data line driving circuit 101 to each pixel P via the data line 6a. The scanning line 3 is connected to the scanning line driving circuit 102 (see FIG. 1). The scanning signals SC1, SC2,..., SCm are supplied to each pixel P from the scanning line driving circuit 102 via the scanning line 3.

  The image signals D1 to Dn supplied from the data line driving circuit 101 may be supplied to the data lines 6a in the order of lines in this order, or may be supplied for each of a plurality of adjacent data lines 6a for each group. Good. The scanning line driving circuit 102 supplies the scanning signals SC <b> 1 to SCm to the scanning line 3 in a pulse-sequential manner at a predetermined timing.

  In the liquid crystal device 100, the TFT 30 that is a switching element is turned on for a certain period by the input of the scanning signals SC1 to SCm, so that the image signals D1 to Dn supplied from the data line 6a are supplied to the pixel electrode 15 at a predetermined timing. It is the structure written in. The predetermined level of image signals D1 to Dn written to the liquid crystal layer 50 via the pixel electrode 15 is held between the pixel electrode 15 and the counter electrode 23 for a certain period.

  In order to prevent the held image signals D1 to Dn from leaking, the holding capacitor 16 is connected in parallel with the liquid crystal capacitor formed between the pixel electrode 15 and the counter electrode 23. The storage capacitor 16 is provided between the second source / drain region of the TFT 30 and the capacitor line 7.

  Note that a data line 6a is connected to the inspection circuit 103 shown in FIG. 1A, and an operation defect or the like of the liquid crystal device 100 is confirmed by detecting the image signal in the manufacturing process of the liquid crystal device 100. Although it can be configured, it is omitted in the equivalent circuit of FIG.

  The inspection circuit 103 includes a sampling circuit that samples the image signal and supplies it to the data line 6a, and a precharge circuit that supplies a precharge signal of a predetermined voltage level to the data line 6a prior to the image signal. Also good.

Next, the configuration of the pixel P in the liquid crystal device 100 will be described with reference to FIG. FIG. 3 is a schematic plan view showing the arrangement of pixels.
As shown in FIG. 3, the pixel P in the liquid crystal device 100 has, for example, a substantially square (substantially square) opening region in a plan view. The opening area is surrounded by a light-shielding non-opening area extending in the X direction and the Y direction and provided in a lattice shape.

  A scanning line 3 shown in FIG. 2 is provided in the non-opening region extending in the X direction. The scanning line 3 uses a light-shielding conductive member, and the scanning line 3 constitutes a part of the non-opening region.

  Similarly, a data line 6a shown in FIG. 2 is provided in the non-opening region extending in the Y direction. The data line 6a also uses a light-shielding conductive member, and these constitute a part of the non-opening region.

  The non-opening region is constituted not only by the signal lines provided on the element substrate 10 side, but also by a light shielding film provided in the same layer as the parting portion 21 and patterned in a lattice pattern on the counter substrate 20 side. Has been.

  The TFT 30 shown in FIG. 2 is provided near the intersection of the non-opening regions. By providing the TFT 30 in the vicinity of the intersection of the non-opening areas having light shielding properties, the aperture ratio in the opening areas is secured. Although the detailed structure of the pixel P will be described later, the width of the non-opening region in the vicinity of the intersecting portion is wider than that in other portions due to the provision of the TFT 30 near the intersecting portion.

  A pixel electrode 15 is provided for each pixel P. The pixel electrode 15 is substantially square in plan view, and is provided in the opening region so that the outer edge of the pixel electrode 15 overlaps the non-opening region. Although not shown in FIG. 3, a translucent storage capacitor 16 is disposed in the opening region.

  The liquid crystal device 100 of the present embodiment is a transmissive type, and on the premise that light enters from the counter substrate 20 side, the element substrate 10 not only shields light directly incident on the TFT 30 but also enters the element substrate 10. A light shielding structure is adopted that can also block the diffracted light generated by the diffracted light being diffracted at the edge of the non-opening region (in other words, the edge of the opening region) and suppress the generation of light leakage current of the TFT 30. . Hereinafter, the light shielding structure of the element substrate 10 will be described.

<Light shielding structure of element substrate>
The light shielding structure in the element substrate 10 will be described with reference to FIGS. FIG. 4 is a schematic plan view showing the arrangement of thin film transistors in the pixel, electrodes and scanning lines related to the thin film transistor, and FIG. 5 is a schematic plan view showing the arrangement of data lines, storage capacitors, etc. in the pixel. 6 is a schematic cross-sectional view showing the structure of the element substrate cut along the line AA ′ in FIG. 5, and FIG. 7 is a schematic cross-sectional view showing the structure of the element substrate cut along the line BB ′ in FIG.

  As shown in FIG. 4, the scanning line 3 is provided for each pixel P, extending in the X direction across the plurality of pixels P, and protrudes from the first part 3 a in the Y direction. It has the 2nd part 3b and the 3rd part 3c. Further, the scanning line 3 has a fourth portion 3d whose width is expanded in the X direction and the Y direction as compared with the first portion 3a and the second portion 3b (third portion 3c). The second portion 3b and the third portion 3c protruding in the Y direction are arranged so as to overlap with a data line 6a (see FIG. 5) to be described later in a plane.

  On the scanning line 3, the semiconductor layer 30a of the TFT 30 is disposed in a region extending between the second portion 3b and the third portion 3c with the fourth portion 3d interposed therebetween. The semiconductor layer 30a is made of, for example, high-temperature polysilicon, and has a channel region 30c, a first source / drain region 30s, and a second source / drain region 30d. The first source / drain region 30s is disposed at a position overlapping the third portion 3c of the scanning line 3, and the second source / drain region 30d is disposed at a position overlapping the second portion 3b of the scanning line 3. Yes. A channel region 30c sandwiched between the first source / drain region 30s and the second source / drain region 30d is mainly disposed at a position overlapping the fourth portion 3d of the scanning line 3.

  A contact hole CNT1 for electrical connection with the data line 6a (see FIG. 5) is provided at the end of the first source / drain region 30s. Specifically, the relay layer 5 for providing electrical connection with the data line 6a is provided at a position overlapping the first source / drain region 30s in plan view, and the contact hole CNT1 is connected to the relay layer 5. A contact hole CNT3 is provided between the relay layer 5 and the data line 6a. At the end of the second source / drain region 30d, a contact hole CNT2 for electrical connection with the storage capacitor 16 and the pixel electrode 15 is provided. That is, in the present embodiment, the contact hole CNT1 functions as the source electrode 31 of the TFT 30, and the contact hole CNT2 functions as the drain electrode 32 of the TFT 30.

  A gate electrode 30g is arranged at a position overlapping the channel region 30c of the semiconductor layer 30a. The gate electrode 30g has a portion that overlaps the channel region 30c at a position that overlaps the fourth portion 3d of the scanning line 3, and a portion that faces the channel region 30c in the X direction and extends in the Y direction. ing. In the portion extending in the Y direction, a contact hole 33 and a contact hole 34 reaching the lower scanning line 3 are provided. That is, the gate electrode 30g is electrically connected to the scanning line 3 via the two contact holes 33 and 34 provided with the channel region 30c interposed therebetween.

  The TFT 30 includes the semiconductor layer 30a and the gate electrode 30g described above. A relay layer 4 for electrical connection between the drain electrode 32 of the TFT 30 and the storage capacitor 16 or the pixel electrode 15 is provided at the intersection of the scanning line 3 where the TFT 30 is disposed and the data line 6a. . The relay layer 4 includes a first portion 4a and a fourth portion 4c that protrude in the X direction from the intersecting portion, and a second portion 4b and a third portion 4d that protrude in the Y direction from the intersecting portion. doing.

  The second portion 4b protruding in the Y direction of the relay layer 4 is disposed and electrically connected so as to overlap the contact hole CNT2 functioning as the drain electrode 32. The other third portion 4d protruding in the Y direction of the relay layer 4 is arranged so as not to overlap the relay layer 5 in plan view. As will be described in detail later, the relay layer 4 and the relay layer 5 are provided in the same wiring layer on the base material 10s.

  A contact hole CNT4 for electrical connection with a relay layer 6b (see FIG. 5) described later is provided at a position near the end of the first portion 4a protruding in the X direction of the relay layer 4. . In FIG. 4, the shape of the contact holes CNT1, CNT2, CNT3, and CNT4 is square in plan view, but is not limited to this, and may be circular or elliptical.

  Each of the scanning line 3, the relay layer 4, and the relay layer 5 illustrated in FIG. 4 is one of the elements constituting the non-opening region illustrated in FIG.

  As shown in FIG. 5, the data line 6a is provided so as to extend in the Y direction at a position overlapping the contact hole CNT1 (source electrode 31), CNT2 (drain electrode 32) and the contact hole CNT3 of the TFT 30. An independent relay layer 6b is provided for each pixel P between adjacent data lines 6a in the X direction. The relay layer 6b is substantially rectangular in plan view, and a contact hole CNT4 is provided in the middle of the longitudinal direction extending in the X direction. As described above, the relay layer 6b is electrically connected to the lower relay layer 4 through the contact hole CNT4.

  As will be described in detail later, the data line 6a and the relay layer 6b are provided in the same wiring layer on the base material 10s. On the base material 10s, the lower electrode 16a of the pair of capacitor electrodes of the storage capacitor 16 is provided on the upper layer of the wiring layer provided with the data line 6a and the relay layer 6b so as to straddle the plurality of pixels P. ing. The lower electrode 16a functions as the capacitor line 7 common to the plurality of pixels P. The upper electrode 16b of the pair of capacitor electrodes of the storage capacitor 16 is provided independently for each pixel P between the adjacent data lines 6a. The upper electrode 16b is substantially square in plan view, and the outer edges of the two sides facing each other in the X direction overlap the data line 6a in plan view. In addition, one of the two sides facing the Y direction of the upper electrode 16b overlaps the relay layer 6b in plan view. The lower electrode 16a and the upper electrode 16b are formed using a transparent conductive film such as ITO or IZO, for example.

  In the relay layer 6b, contact holes CNT5 and CNT6 are arranged on both sides in the X direction with the contact hole CNT4 interposed therebetween. The contact hole CNT5 and the contact hole CNT6 are provided through the lower electrode 16a so as not to contact the lower electrode 16a. The contact hole CNT5 is provided at a position where the relay layer 6b and the upper electrode 16b overlap in plan view, and electrically connects the relay layer 6b and the upper electrode 16b. The upper electrode 16b is cut away so as not to contact the contact hole CNT6. The contact hole CNT6 is provided for electrical connection between the relay layer 6b and the pixel electrode 15 (see FIG. 6). The shape of the contact holes CNT5 and CNT6 in plan view is a substantially rectangular shape whose longitudinal direction is along the X direction. The term “substantially rectangular” includes those whose corners are arcuate.

  Each of the data line 6a and the relay layer 6b shown in FIG. 5 is one of the elements constituting the non-opening region shown in FIG.

  Next, a cross-sectional structure in electrical connection between the pixel electrode 15 and the TFT 30 will be described with reference to FIG. As shown in FIG. 6, on the base material 10 s of the element substrate 10, a first layer including the scanning line 3, a second layer including the TFT 30, a third layer including the relay layers 4 and 5, and a data line are sequentially arranged. A fourth layer including 6a and the like, a fifth layer including storage capacitor 16 and the like, and a sixth layer (uppermost layer) including pixel electrode 15 and the like are formed. A first interlayer insulating film 11a is formed between the first layer and the second layer, and a second interlayer insulating film 11c is formed between the second layer and the third layer. A third interlayer insulating film 12 is formed between the third layer and the fourth layer, a fourth interlayer insulating film 13 is formed between the fourth layer and the fifth layer, and the fifth layer and the sixth layer are formed. A fifth interlayer insulating film 14 is formed between the layers. This prevents a short circuit between the aforementioned elements. Further, in these interlayer insulating films, contact holes for electrical connection between the aforementioned elements are formed. Hereinafter, each of these elements will be described in order. FIG. 4 shows a planar arrangement of each element from the first layer to the third layer, and FIG. 5 shows a planar arrangement of each element from the fourth layer to the fifth layer.

  First, in the first layer, for example, a metal simple substance, an alloy, a metal silicide, a polysilicide, or a laminate of these containing at least one of refractory metals such as Ti, Cr, Mo, Ta, W, etc. Alternatively, the scanning line 3 made of conductive polysilicon or the like is formed. In particular, the scanning line 3 is preferably formed using metal silicide from the viewpoint of shielding the return light incident from the base material 10s side and not reflecting the incident light incident from the counter substrate 20 side. In the embodiment, the scanning line 3 is formed using WSi (tungsten silicide). The film thickness of the scanning line 3 is about 200 nm, for example.

Next, a first interlayer insulating film 11a that covers the scanning lines 3 is formed. The first interlayer insulating film 11a is formed using, for example, silicon oxide. The film thickness of the first interlayer insulating film 11a is, for example, about 400 nm.
Subsequently, a semiconductor layer 30a is formed on the first interlayer insulating film 11a as a second layer. The semiconductor layer 30a is made of, for example, polysilicon, and impurity ions are selectively implanted, and the LDD including the first source / drain region 30s, the junction region 30e, the channel region 30c, the junction region 30f, and the second source / drain region 30d. (Lightly Doped Drain) structure is built. The film thickness of the semiconductor layer 30a is approximately 40 nm, for example.

  Next, a gate insulating film 11b covering the semiconductor layer 30a is formed. The gate insulating film 11b is formed using, for example, silicon oxide. The film thickness of the gate insulating film 11b is about 50 nm, for example.

  Next, a groove-shaped through hole is formed in the first interlayer insulating film 11a and the gate insulating film 11b. A gate electrode 30g and a pair of contact holes 33 and 34 are formed by forming and patterning a conductive film so as to fill the through hole. In FIG. 6, the contact hole 34 of the pair of contact holes 33 and 34 is illustrated, and the contact hole 33 is not illustrated. Thereby, a part of the semiconductor layer 30a of the TFT 30 is covered with the contact holes 33 and 34 from the side in a plan view, as shown in FIG. As shown in FIG. 4, the contact holes 33 and 34 are provided in parallel from the channel region 30c to the second source / drain region 30d in the semiconductor layer 30a extending in the Y direction in plan view. . Therefore, although light incident from the pair of contact holes 33 and 34 between which the semiconductor layer 30a is sandwiched can be shielded, it does not have a function of shielding all sides of the semiconductor layer 30a.

  The contact holes 33 and 34 are formed so that the lower ends thereof are in contact with the scanning line 3. Accordingly, the gate electrode 30g and the scanning line 3 existing in a certain row (X direction) are always at the same potential as long as the row is focused.

An example of the conductive film used for the gate electrode 30g is a conductive polysilicon film. The film thickness of the gate electrode 30g is about 100 nm, for example.
Then, a second interlayer insulating film 11c that covers the gate electrode 30g and the gate insulating film 11b of the TFT 30 is formed. The second interlayer insulating film 11c is formed using, for example, silicon oxide and has a thickness of about 300 nm, for example.

  A through hole is formed in the gate insulating film 11b and the second interlayer insulating film 11c at a position overlapping the first source / drain region 30s and the second source / drain region 30d of the semiconductor layer 30a, and fills the inside of the through hole. As described above, the relay layer 5, the contact hole CNT1, the relay layer 4, and the contact hole CNT2 are formed by forming and patterning a conductive film on the second interlayer insulating film 11c. The relay layer 4 as the third layer is formed so as to overlap the gate electrode 30g in plan view (see FIG. 4). Examples of the conductive film used for the relay layer 4 and the relay layer 5 as the third layer include metals such as Al (aluminum) and Ti (titanium), which are low resistance wiring materials, and metal compounds thereof. In the present embodiment, the relay layers 4 and 5 have a four-layer structure of Ti (titanium) layer / TiN (titanium nitride) layer / Al (aluminum) layer / TiN (titanium nitride) layer. The relay layers 4 and 5 include a Ti layer and an Al layer that are metal layers. The thickness of the Ti layer is, for example, about 20 nm, the thickness of the previous TiN layer is, for example, 50 nm, the thickness of the Al layer is, for example, 350 nm, and the thickness of the subsequent TiN layer is, for example, 150 nm.

  Of the gate insulating film 11b and the second interlayer insulating film 11c, a region overlapping with the relay layer 4 and the relay layer 5 as the third layer (wiring layer) in a plan view is recessed toward the semiconductor layer 30a and has an inversely tapered shape. A recess 11e having a side wall 11d is provided. A light shielding layer 41 is provided between the side wall 11d and the relay layer 4 (the relay layer 5). The light shielding layer 41 is made of TiN (titanium nitride) which is a nitride of Ti (titanium) which is a metal. That is, the light shielding layer 41 covering the side wall 11d of the recess 11e and the Ti layers of the relay layers 4 and 5 are in contact with each other. Since the recess 11e is provided over the area where the relay layer 4 and the relay layer 5 are provided, the area where the semiconductor layer 30a is provided in a plane is included in the area where the recess 11e is provided. The side wall 11d of the recess 11e is located outside the region where the semiconductor layer 30a is provided. Since the light shielding layer 41 provided so as to cover the side wall 11d is made of TiN (titanium nitride), it is easier to absorb light in the visible light wavelength region than when Ti (titanium) which is a metal is used. It has the property of In addition, the “reverse taper shape” in the present embodiment means that the angle of the side wall 11d with respect to the bottom surface of the recess 11e is 90 degrees or more. In other words, the angle of the side wall 11d with respect to the bottom surface of the recess 11e is 90 degrees.

  Next, a third interlayer insulating film 12 covering the relay layers 4 and 5 is formed. The third interlayer insulating film 12 is formed using, for example, silicon oxide and has a thickness of about 400 nm, for example. A through hole penetrating the third interlayer insulating film 12 is formed at a position overlapping the relay layer 5 of the third interlayer insulating film 12. In addition, a through-hole penetrating the third interlayer insulating film 12 is formed at a position overlapping the first portion 4 a in the relay layer 4 of the third interlayer insulating film 12. A conductive film is formed on the third interlayer insulating film 12 and patterned so as to fill the inside of these through holes, whereby the data line 6a and the relay layer 6b as the fourth layer, the contact hole CNT3 and the contact are formed. Hole CNT4 is formed. As the conductive film used for the fourth layer, the same metal or metal compound as that for the third layer can be used. In the present embodiment, the fourth layer has a two-layer structure of Al (aluminum) / TiN (titanium nitride).

  Next, a fourth interlayer insulating film 13 is formed to cover the data line 6a and the relay layer 6b as the fourth layer. The fourth interlayer insulating film 13 is formed using, for example, silicon oxide. The film thickness of the fourth interlayer insulating film 13 is about 400 nm, for example. Since the fourth interlayer insulating film 13 has irregularities on the surface after film formation due to the lower wiring structure, for example, a planarization process such as a CMP (Chemical Mechanical Polishing) process is performed.

  Next, the storage capacitor 16 that is the fifth layer is formed on the fourth interlayer insulating film 13 that has been subjected to the planarization process. Specifically, first, the lower electrode 16a of the storage capacitor 16 is formed by forming a transparent conductive film such as ITO or IZO on the fourth interlayer insulating film 13 and patterning it. The film thickness of the lower electrode 16a is about 140 nm, for example. As shown in FIG. 5, the lower electrode 16 a is formed over at least the display region E as a common capacitance line 7 in the plurality of pixels P. The lower electrode 16a is a contact hole CNT5 for electrical connection between the upper electrode 16b of the storage capacitor 16 and the relay layer 6b, and a contact hole CNT6 for electrical connection between the pixel electrode 15 and the relay layer 6b. In order to avoid contact with the contact holes CNT, patterning is performed so as to have openings in portions overlapping the contact holes CNT5 and CNT6.

Next, a dielectric layer 16c that covers the lower electrode 16a is formed. The dielectric layer 16c is composed of a plurality of layers formed using dielectric materials having different dielectric constants. The film thickness of the dielectric layer 16c is approximately 30 nm, for example. Examples of the dielectric material include hafnium oxide, aluminum oxide, a silicon oxide film, a silicon nitride film, and tantalum oxide (Ta ₂ O ₅ ). By combining these layers having different dielectric constants, a larger electric capacity can be realized while ensuring translucency.

  Next, a through-hole penetrating the fourth interlayer insulating film 13 and the dielectric layer 16c is formed at a position overlapping the relay layer 6b in plan view. The upper electrode 16b of the storage capacitor 16 and the contact hole CNT5 are formed by patterning a transparent conductive film such as ITO or IZO that covers the dielectric layer 16c so as to cover the inside of the through hole. It is formed. The film thickness of the upper electrode 16b is approximately 140 nm, for example.

  Next, a fifth interlayer insulating film 14 covering the upper electrode 16b and the contact hole CNT5 is formed. The fifth interlayer insulating film 14 includes a first insulating film 14a and a second insulating film 14b stacked on the first insulating film 14a. More specifically, first, an NSG (Non doped Silicate Glass) film covering the upper electrode 16b and the contact hole CNT5 is formed by a plasma CVD method, for example, so as to have a film thickness of about 400 nm. Then, for the purpose of alleviating the unevenness of the surface of the NSG film generated by covering the contact holes CNT5 and the like, a planarization process such as a CMP process is performed. The film thickness of the NSG film on the upper electrode 16b after the planarization process, that is, the first insulating film 14a is, for example, about 100 nm. And the 2nd insulating film 14b which covers the 1st insulating film 14a is formed. The second insulating film 14b is formed using a material different from that of the first insulating film 14a so as to be thinner than the first insulating film 14a. The second insulating film 14b is, for example, a BSG (Boron doped Silicate Glass) film, and is formed by using, for example, a plasma CVD method. The film thickness of the second insulating film 14b is approximately 75 nm, for example.

  Next, a through-hole penetrating the fourth interlayer insulating film 13, the dielectric layer 16c, and the fifth interlayer insulating film 14 is formed at a position overlapping the relay layer 6b in plan view. The pixel electrode 15 and the contact hole CNT6 are formed by forming and patterning a transparent conductive film such as ITO covering the fifth interlayer insulating film 14 so as to cover the inside of the through hole. As shown in FIG. 3, the pixel electrode 15 is formed so as to overlap with the storage capacitor 16 in the opening region of the pixel P, and to overlap the outer edge portion of the pixel electrode 15 with the non-opening region. In the present embodiment, light incident from the counter substrate 20 side is transmitted through the counter substrate 20 and the liquid crystal layer 50, and is transmitted through the pixel electrode 15 and the storage capacitor 16 disposed in the opening region of the pixel P. It is injected from the side. In the present embodiment, the film thickness of each of the pixel electrode 15, the lower electrode 16a, and the upper electrode 16b made of a transparent conductive film is about 140 nm. Accordingly, the optical attenuation of the incident light by passing through the pixel electrode 15 and the storage capacitor 16 is suppressed. Further, by setting the film thickness of the pixel electrode 15 to approximately 140 nm, the coverage of the contact hole CNT6 deeper than the contact hole CNT5 is improved, and the electrical connection between the pixel electrode 15 and the relay layer 6b is stabilized. Yes.

  In this embodiment, the base material 10s corresponds to the “substrate” of the present invention, and the second interlayer insulating film 11c corresponds to the “interlayer insulating film” of the present invention. The relay layers 4 and 5 correspond to the “wiring layer” of the present invention.

  As shown in FIG. 7, the scanning line 3, the semiconductor layer 30a, the gate electrode 30g, the relay layer 4, the data line 6a, the storage capacitor 16, and the pixel electrode 15 are arranged in this order on the base 10s. The gate electrode 30g is provided so as to face the channel region of the semiconductor layer 30a, and is electrically connected to the scanning line 3 by contact holes 33 and 34 penetrating the gate insulating film 11b and the first interlayer insulating film 11a. Yes. The TFT 30 including the gate electrode 30g and the semiconductor layer 30a is disposed between the scanning line 3 and the relay layer 4 each having a light shielding property on the base material 10s.

  In the second interlayer insulating film 11c provided between the gate electrode 30g and the relay layer 4, a recess 11e is provided immediately above the gate electrode 30g. The width of the recess 11e in the X direction is substantially equal to the width of the gate electrode 30g in the X direction. The depth of the recess 11e that is recessed toward the semiconductor layer 30a is approximately 100 nm. Since the thickness of the second interlayer insulating film 11c is approximately 300 nm, the distance between the bottom of the recess 11e and the gate electrode 30g is approximately 200 nm. The light shielding layer 41 is provided so as to cover the reverse tapered side wall 11d of the recess 11e. The relay layer 4 is provided so as to fill the recess 11e in which the light shielding layer 41 is provided. The width of the relay layer 4 in the X direction is wider than the width of the recess 11e in the X direction, and is also wider than the width of the gate electrode 30g and the scanning line 3 in the X direction. The side wall 11d of the recess 11e provided with the light shielding layer 41 is located outside the region where the semiconductor layer 30a is provided in the X direction. In other words, the light shielding layer 41 is located outside the region where the semiconductor layer 30a is provided in the X direction.

  In such an element substrate 10, the light L1 incident on the central portion of the pixel P along the optical axis from the counter substrate 20 side passes through the translucent pixel electrode 15 and the storage capacitor 16, and passes through the scanning line 3 and the relay. It passes through the opening area surrounded by the non-opening area constituted by the layer 4 and the like, and is injected from the base material 10s.

The light L2 incident on the edge of the non-opening region of the element substrate 10, in other words, the edge of the opening region, is diffracted at the end of the relay layer 4 and becomes diffracted light. A portion of the second interlayer insulating film 11c located immediately below the relay layer 4 is dug down, and a light shielding layer 41 is provided on the side wall 11d of the dug down recess 11e. The recess 11e is provided over a region including the region where the semiconductor layer 30a is provided in plan view, and the light shielding layer 41 is disposed outside the region where the semiconductor layer 30a is provided. The diffracted light generated at the portion is shielded by the light shielding layer 41 and is not incident on the semiconductor layer 30a.
When the diffracted light is incident on the semiconductor layer 30a, light leakage current may occur in the TFT 30, and thus it is effective to shield the diffracted light. In particular, in order to realize a bright display by increasing the aperture ratio of the pixel P, that is, the ratio of the area of the opening area per unit area, the width of the non-opening area (in this embodiment, the X-direction of the relay layers 4 and 5). When the (width) is narrowed, the diffracted light is likely to enter the semiconductor layer 30a. Therefore, it is more effective to dispose the light shielding layer 41 that shields the diffracted light directly below the relay layers 4 and 5 as the width of the relay layers 4 and 5 is narrowed in the X direction. Hereinafter, a specific method for forming a light shielding structure capable of reliably shielding light incident on the semiconductor layer 30a of the TFT 30 will be described.

<Method of manufacturing electro-optical device>
As a method for manufacturing the electro-optical device according to the present embodiment, a method for manufacturing the element substrate 10 of the liquid crystal device 100 will be described with reference to FIGS. 8A to 8C and FIGS. 9D to 9F are schematic cross-sectional views showing a method for manufacturing an element substrate. 10A to 10C are schematic cross-sectional views showing a method for manufacturing an element substrate according to a modification. 8 to 10 are sectional views showing the structure of the element substrate corresponding to the main part in the schematic sectional view of FIG.

  The manufacturing method of the element substrate 10 of the present embodiment includes a transistor formation step (Step S1), an interlayer insulating film formation step (Step S2), a recess formation step (Step S3), and a light shielding layer formation step (Step S4). And a wiring layer forming step (step S5). In addition, as described above, a known forming method can be used as a method for forming the scanning line 3, the first interlayer insulating film 11a, and the TFT 30 (semiconductor layer 30a, gate electrode 30g, etc.) in the element substrate 10. Therefore, here, the process after step S2 including the characteristic part will be described.

In step S2, as shown in FIG. 8A, the second interlayer insulating film 11c covering the TFT 30 (substantially including the region where the semiconductor layer 30a and the gate electrode 30g are formed) is formed on the base material 10s. Form. Examples of the method of forming the second interlayer insulating film 11c include a method of forming a silicon oxide film by a plasma CVD method using water (H ₂ O) and TEOS (tetraethoxysilane) as processing gases. The film thickness of the silicon oxide film is approximately 300 nm, for example.

  In step S3, as shown in FIG. 8B, a recess 11e is formed in a portion of the second interlayer insulating film 11c immediately above the gate electrode 30g. As a method for forming the recess 11e, there is a method in which the second interlayer insulating film 11c is subjected to dry etching using, for example, a fluorine-based processing gas. The region where the recess 11e is formed extends over a region where the relay layer 4 and the relay layer 5 which are wiring layers later are formed. Although not shown in FIG. 8B, the surface of the second interlayer insulating film 11c other than the region where the recess 11e is formed is covered with an etching resist. As the dry etching proceeds in the second interlayer insulating film 11c, a recess 11e having a flat bottom surface and a side wall 11d having a reverse taper with respect to the bottom surface is formed.

  In step S4, first, as shown in FIG. 8C, a titanium nitride film (TiN film) 41a covering at least the recess 11e is formed. Examples of the method of forming the TiN film 41a include a method of sputtering using titanium nitride (TiN) as a target, and a method of sputtering, vacuum deposition, and ion plating in a nitrogen atmosphere using metal Ti as a target. In the present embodiment, sputtering was performed using titanium nitride (TiN) as a target to form a TiN film 41a having a thickness of 100 nm. Next, the TiN film 41a is patterned by photolithography so as to leave only a portion corresponding to the side wall 11d of the recess 11e as shown in FIG.

  In step S5, first, as shown in FIG. 9E, a plurality of conductive films covering at least the recess 11e in which the light shielding layer 41 is formed are stacked. Specifically, for example, a sputtering method using, for example, each material as a target in the order of a titanium film (Ti film) 42a, a TiN film 43a, an aluminum film (Al film) 44a, and a TiN film 45a can be mentioned. The thickness of the Ti film 42a is, for example, 20 nm, the thickness of the TiN film 43a is, for example, 50 nm, the thickness of the Al film 44a is, for example, 350 nm, and the thickness of the TiN film 45a is, for example, 150 nm. These laminated films are collectively patterned by, for example, dry etching using a photolithography method to form a relay layer 4 made of the laminated film as shown in FIG. The relay layer 5 that is the same layer as the relay layer 4 is similarly patterned. The planar arrangement of the relay layer 4 and the relay layer 5 includes a region where the semiconductor layer 30a is arranged and a region where the gate electrode 30g is arranged as shown in FIG. Further, it includes a region where contact holes CNT1, CNT2, CNT3, and CNT4 are formed. That is, the relay layers 4 and 5 are formed in a region including the semiconductor layer 30a and a portion related to its electrical connection. Further, a recess 11e is formed in the second interlayer insulating film 11c immediately below the relay layers 4 and 5.

<Modification in Method for Manufacturing Element Substrate>
Next, with reference to FIG. 10, a method for manufacturing the element substrate 10B according to the modification will be described. In addition, the same code | symbol is attached | subjected to the same structure as the manufacturing method of the previous element substrate 10, and detailed description is abbreviate | omitted. In the method of manufacturing the element substrate 10B according to the modification, the wiring layer including the light shielding layer is formed in the wiring layer forming step.

  Specifically, as shown in FIG. 10A, a recess 11e having a reverse-tapered side wall 11d is formed in the second interlayer insulating film 11c (step S3). Thereafter, as shown in FIG. 10B, a TiN film 41a, a Ti film 42a, a TiN film 43a, an Al film 44a, and a TiN film 45a are sequentially stacked so as to cover at least the recess 11e. These laminated films are collectively patterned by, for example, wet etching using a photolithography method to form a relay layer 4 made of the laminated film as shown in FIG. The relay layer 5 that is the same layer as the relay layer 4 is similarly patterned. The relay layer 4 of the modification includes a light shielding layer 41 that covers the bottom surface of the recess 11e and the side wall 11d. Further, a Ti layer 42 which is a metal layer laminated in contact with the light shielding layer 41 is included.

  According to the manufacturing method of the element substrate 10B of such a modification, the light shielding layer 41 and the relay layer 4 can be efficiently formed because it is not necessary to form the light shielding layer 41 individually.

Effects in the manufacturing method of the liquid crystal device 100 and the element substrate 10 of the first embodiment are as follows.
(1) The TFT 30 which is the switching element of the pixel P in the element substrate 10 is formed between the light-shielding scanning line 3 and the relay layer 4 on the base material 10 s. In the second interlayer insulating film 11 c covering the TFT 30, a recess 11 e is formed immediately above the TFT 30. The recess 11e is formed to have a reverse-tapered side wall 11d outside the region where the semiconductor layer 30a of the TFT 30 is provided, and the side wall 11d is covered with a light shielding layer 41. Light-shielding relay layers 4 and 5 are laminated and formed in the recess 11e. In other words, the recess 11e is formed over the region where the relay layers 4 and 5 are formed. According to such a light shielding structure of the element substrate 10, light incident from directly above the TFT 30 is shielded by the relay layers 4 and 5. Further, the diffracted light generated when the light enters the end portions of the relay layers 4 and 5 is shielded by the light shielding layer 41 that covers the side wall 11d of the recess 11e provided immediately below the relay layers 4 and 5. That is, not only the light incident from directly above the TFT 30 but also the diffracted light generated at the end of the wiring layer formed immediately above the TFT 30 is shielded, so that it is possible to reliably suppress the occurrence of light leakage current in the TFT 30. The liquid crystal device 100 as an optical device can be provided or manufactured.
(2) Since the light shielding layer 41 is formed using TiN (titanium nitride), it is easier to absorb light in the visible light wavelength region than when formed using Ti (titanium) which is a metal. . Therefore, re-reflection of the light incident on the light shielding layer 41 can be suppressed. That is, it is possible to suppress the occurrence of light leakage current of the TFT 30 due to stray light generated by re-reflection.
(3) The relay layers 4 and 5 that are wiring layers include a Ti layer 42 that is the same kind of metal layer as the light shielding layer 41, and the light shielding layer 41 and the Ti layer 42 are in contact with each other. Therefore, the relay layers 4 and 5 are low resistance wirings and have excellent adhesion to the light shielding layer 41.

(Second Embodiment)
<Electro-optical device and manufacturing method thereof>
Next, a liquid crystal device as an electro-optical device according to the second embodiment will be described with reference to FIGS. FIG. 11 is a schematic plan view showing the arrangement of relay layers and recesses in the element substrate of the second embodiment, and FIG. 12 is a schematic cross-sectional view showing the structure of the element substrate taken along the line CC ′ of FIG. . In the liquid crystal device as the electro-optical device according to the second embodiment, the arrangement of the recesses is different from the element substrate 10 of the liquid crystal device 100 according to the first embodiment. Therefore, the same components as those of the element substrate 10 are denoted by the same reference numerals and detailed description thereof is omitted.

  As shown in FIG. 11, the element substrate 10 </ b> C of the liquid crystal device according to the present embodiment includes the relay layers 4 and 5 constituting the non-opening region of the pixel P and the second interlayer insulating film 11 c immediately below the relay layers 4 and 5. A recess 11g is provided in a portion along the outer edge of the area where the relay layers 4 and 5 are provided in a plane. In this case, the recess 11g is provided so as to go around the outer edge in each of the relay layers 4 and 5. The width of the recess 11g is, for example, 0.5 μm.

  As illustrated in FIG. 12, the element substrate 10 </ b> C includes the scanning line 3, the TFT 30, the relay layer 4 (relay layer 5), the data line 6 a, the storage capacitor 16, and the pixel electrode 15 that are sequentially provided on the base material 10 s. . In the second interlayer insulating film 11 c between the TFT 30 and the relay layers 4 and 5, a recess 11 g is provided in a portion along the outer edge of the relay layers 4 and 5. The recess 11g has a substantially V-shaped cross section, and has a reverse-tapered side wall 11d. The relay layers 4 and 5 are formed so as to fill the recess 11g, and are sequentially stacked from the surface side of the second interlayer insulating film 11c, the TiN layer 41, the Ti layer 42, the TiN layer 43, the Al layer 44, and the TiN layer. 45. The TiN layer 41 covering the side wall 11d of the recess 11g functions as a light shielding layer.

  As a method for forming the recess 11g in the second interlayer insulating film 11c, a method similar to the recess forming step (step S3) in the first embodiment can be used. That is, the recess 11g is formed by dry etching the second interlayer insulating film 11c. As a method of forming the relay layers 4 and 5 that fill the recess 11g, the method employed in the modification of the first embodiment is used. That is, the TiN layer 41 functioning as a light shielding layer is formed as a part of the relay layers 4 and 5.

  According to the element substrate 10C of the second embodiment and the manufacturing method thereof, as in the element substrate 10 of the first embodiment, not only the directly incident light but also a relay that is a wiring layer formed above the TFT 30. Diffracted light generated by the light L2 incident on the ends of the layers 4 and 5 is also shielded by the TiN layer 41. Therefore, it is possible to provide or manufacture a liquid crystal device as an electro-optical device that can reliably suppress the occurrence of light leakage current in the TFT 30.

  Further, the recess 11g is formed so as to make a round along the outer edge of the region where the relay layers 4 and 5 are formed in a plan view. Accordingly, the surface 11f of the second interlayer insulating film 11c between the recesses 11g adjacent in the X direction is not recessed toward the semiconductor layer 30a. Therefore, as compared with the concave portion 11e of the first embodiment, the portion where the distance between the gate electrode 30g and the relay layers 4 and 5 is increased increases. That is, the parasitic capacitance between the gate electrode 30g and the relay layer 4 through the second interlayer insulating film 11c is smaller than that in the first embodiment, and the characteristic change of the TFT 30 due to the parasitic capacitance can be suppressed.

  In addition, although it is preferable that the recessed part 11g is arrange | positioned so that it may wrap around along the outer edge of the relay layers 4 and 5 planarly, it is not limited to this. It is sufficient that the diffracted light does not easily enter the semiconductor layer 30a of the TFT 30, and the recess 11g is disposed at least in the outer edge of the relay layers 4 and 5 along the extending direction of the semiconductor layer 30a (Y direction in this embodiment). It only has to be done.

(Third embodiment)
<Electronic equipment>
Next, a projection display device as an electronic apparatus to which the liquid crystal device 100 as an electro-optical device according to this embodiment is applied will be described with reference to FIG. FIG. 13 is a schematic diagram showing the configuration of the projection display device.

  As shown in FIG. 13, a projection display apparatus 1000 as an electronic apparatus according to the present embodiment includes a polarization illumination apparatus 1100 arranged along the system optical axis L, and two dichroic mirrors 1104 and 1105 as light separation elements. And. In addition, three reflection mirrors 1106, 1107, 1108 and five relay lenses 1201, 1202, 1203, 1204, 1205 are provided. Further, it includes transmissive liquid crystal light valves 1210, 1220, and 1230 as three light modulation means, a cross dichroic prism 1206 as a light combining element, and a projection lens 1207.

  The polarized light illumination device 1100 is generally configured by a lamp unit 1101 as a light source composed of a white light source such as an ultra-high pressure mercury lamp or a halogen lamp, an integrator lens 1102, and a polarization conversion element 1103.

  The dichroic mirror 1104 reflects red light (R) and transmits green light (G) and blue light (B) among the polarized light beams emitted from the polarization illumination device 1100. Another dichroic mirror 1105 reflects the green light (G) transmitted through the dichroic mirror 1104 and transmits the blue light (B).

The red light (R) reflected by the dichroic mirror 1104 is reflected by the reflection mirror 1106 and then enters the liquid crystal light valve 1210 via the relay lens 1205.
Green light (G) reflected by the dichroic mirror 1105 enters the liquid crystal light valve 1220 via the relay lens 1204.
The blue light (B) transmitted through the dichroic mirror 1105 enters the liquid crystal light valve 1230 via a light guide system including three relay lenses 1201, 1202, 1203 and two reflection mirrors 1107, 1108.

  The liquid crystal light valves 1210, 1220, and 1230 are disposed to face the incident surfaces of the cross dichroic prism 1206 for each color light. The color light incident on the liquid crystal light valves 1210, 1220, and 1230 is modulated based on video information (video signal) and emitted toward the cross dichroic prism 1206. In this prism, four right-angle prisms are bonded together, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on the inner surface thereof. The three color lights are synthesized by these dielectric multilayer films, and the light representing the color image is synthesized. The synthesized light is projected onto the screen 1300 by the projection lens 1207, which is a projection optical system, and the image is enlarged and displayed.

  The liquid crystal light valve 1210 is the one to which the liquid crystal device 100 (see FIG. 1) of the first embodiment is applied. A pair of polarizing elements arranged in crossed Nicols are arranged with a gap between the colored light incident side and the emitting side of the liquid crystal device 100. The same applies to the other liquid crystal light valves 1220 and 1230.

  According to such a projection display apparatus 1000, since the liquid crystal device 100 of the first embodiment is used as the liquid crystal light valves 1210, 1220, and 1230, generation of light leakage current in the TFT 30 is suppressed and stable. Drive state is obtained. That is, it is possible to provide the projection display apparatus 1000 that realizes a stable driving state. Note that the same effect can be obtained even when the liquid crystal device having the element substrate 10C of the second embodiment is employed as the liquid crystal light valves 1210, 1220, and 1230.

  The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit or idea of the invention that can be read from the claims and the entire specification. The manufacturing method of the electro-optical device and the electronic apparatus to which the electro-optical device is applied are also included in the technical scope of the present invention. Various modifications other than the above embodiment are conceivable. Hereinafter, a modification will be described.

  (Modification 1) The configuration of the element substrate 10 in the liquid crystal device 100 of the first embodiment is not limited to this. For example, in the first embodiment, the semiconductor layer 30a of the TFT 30 is arranged in the extending direction (Y direction) of the data line 6a, but may be arranged in the extending direction of the scanning line 3. Further, although the translucent storage capacitor 16 is arranged in the opening region of the pixel P, the holding capacitor 16 may be arranged in the non-opening region.

  (Modification 2) The electro-optical device in which the light shielding structure of the present invention is applied to an element substrate including a transistor that is a switching element of the pixel P is not limited to the light receiving type liquid crystal device 100. The present invention can also be applied to an active drive type electro-optical device in which the pixel P includes a light emitting element such as an organic electroluminescence (EL) element.

  (Modification 3) The electronic apparatus to which the liquid crystal device 100 of the first embodiment is applied is not limited to the projection display device 1000 of the third embodiment. For example, the counter substrate 20 of the liquid crystal device 100 may include color filters corresponding to at least red (R), green (G), and blue (B), and the projection display device may have a single plate configuration. Also, for example, a projection type HUD (head-up display), HMD (head-mounted display), electronic book, personal computer, digital still camera, liquid crystal television, viewfinder type or monitor direct view type video recorder, car navigation system, The liquid crystal device 100 can be suitably used as a display unit of an information terminal device such as an electronic notebook or POS.

  4, 5 ... Relay layer as wiring layer, 10 ... Element substrate, 10s ... Base material as substrate, 11c ... Second interlayer insulating film as interlayer insulating film, 11d ... Side wall, 11e, 11g ... Recess, 15 ... Pixel Electrode, 30 ... Thin film transistor (TFT), 30a ... Semiconductor layer, 41 ... Light shielding layer (TiN layer), 100 ... Liquid crystal device as electro-optical device, 1000 ... Projection type display device as electronic equipment.

Claims (12)

A substrate,
A transistor provided on the substrate;
A pixel electrode provided on the substrate and driven by the transistor;
An interlayer insulating film provided on the upper layer side of the transistor;
A recess provided in the interlayer insulating film, recessed toward the semiconductor layer of the transistor, and having a reverse-tapered sidewall disposed outside the region where the semiconductor layer is provided;
A light shielding layer provided on the interlayer insulating film so as to cover at least the side wall;
An electro-optical device comprising: a planar light-shielding wiring layer stacked on a region where the semiconductor layer is provided in a plane and the concave portion provided with the light-shielding layer.   The electro-optical device according to claim 1, wherein the recess includes a region where the semiconductor layer is provided in a planar manner.   The electro-optical device according to claim 1, wherein the concave portion is provided in a portion along an outer edge of a region where the wiring layer is provided.   The electro-optical device according to claim 1, wherein the wiring layer includes a layer made of a metal, and the light shielding layer is made of a nitride of the metal. The wiring layer includes a first layer made of a metal and a second layer made of the metal nitride,
The electro-optical device according to claim 1, wherein the light shielding layer is configured by the second layer. A method of manufacturing an electro-optical device having a transistor and a pixel electrode driven by the transistor on a substrate,
Forming the transistor on the substrate;
Forming an interlayer insulating film covering the transistor;
Forming a recess in the interlayer insulating film having a reverse-tapered sidewall disposed outside a region overlapping the semiconductor layer of the transistor in a plane;
Forming a light shielding layer covering at least the side wall;
And a step of forming a light-shielding wiring layer by laminating the semiconductor layer on the planar region and the concave portion on which the light-shielding layer is formed. Method.   The method of manufacturing the electro-optical device according to claim 6, wherein the step of forming the recess includes forming the recess in a region including a region where the semiconductor layer is formed in a planar manner.   The method of manufacturing an electro-optical device according to claim 6, wherein the step of forming the recess includes forming the recess in a portion along an outer edge of a region where the wiring layer is formed.   9. The method of manufacturing an electro-optical device according to claim 6, wherein in the step of forming the light shielding layer, the light shielding layer is formed using metal nitride.   The step of forming the wiring layer includes a step of forming the light shielding layer using a metal nitride, and a step of forming a metal layer by laminating the light shielding layer using the metal. The method of manufacturing an electro-optical device according to claim 6.   An electronic apparatus comprising the electro-optical device according to claim 1.   An electronic apparatus comprising the electro-optical device manufactured using the method for manufacturing an electro-optical device according to claim 6.

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