JP2014153384A - Electro-optic device, method for manufacturing electro-optic device, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress degradation in transistor characteristics due to diffusion of an impurity when an impurity that gives an adverse influence on the transistor characteristics is present on a substrate for forming a transistor.SOLUTION: An electro-optic device includes a substrate body 10a, a first dielectric layer 35 covering a liquid crystal layer 50 side of the substrate body 10a, a barrier layer 33 covering at least a part of the first dielectric layer 35, a second dielectric layer 36 sandwiching the barrier layer 33 with the first dielectric layer 35, and a semiconductor layer of a transistor 30 formed above the second dielectric layer 36. The region where the barrier layer 33 is disposed overlaps a channel region 1a' of the semiconductor layer in a view along the normal direction of the surface on the liquid crystal layer 50 side of the substrate body 10a, and is equal to or larger than the channel region 1a'.

Description

  The present invention relates to an electro-optical device, a method for manufacturing the electro-optical device, and an electronic apparatus equipped with the electro-optical device.

  As the electro-optical device, for example, an active drive type liquid crystal device used as light modulation means (light valve) of a liquid crystal projector can be cited. This liquid crystal device has a pixel region in which a pixel electrode and a driving element for driving the pixel electrode are arranged, and a peripheral region in which a scanning line driving circuit and a data line driving circuit for driving the driving element are arranged. ing. The driving element, the scanning line driving circuit, and the data line driving circuit described above are formed of thin film transistors, and the characteristics of the thin film transistors greatly affect the performance of the liquid crystal device.

  FIG. 14 is a schematic cross-sectional view showing the structure of a thin film transistor 500 in the prior art. As shown in FIG. 14, a conventional thin film transistor 500 includes, for example, a semiconductor layer 504, a gate insulating film 505, a gate electrode 506, and an interlayer insulating film 507 in this order via a base layer 503 on a quartz substrate 502. It has a formed structure. The source region 508 and the drain region 509 are formed by ion implantation of impurities into the semiconductor layer 504. The gate electrode 506, the source electrode 510, and the drain electrode 511 have a multilayer wiring structure with an interlayer insulating film 507 interposed therebetween.

The characteristics of the thin film transistor 500 vary depending on the state of the interface between the semiconductor layer 504 and the gate insulating film 505, the state of the interface between the semiconductor layer 504 and the base layer 503, and the like. For example, in order to control the threshold voltage in the thin film transistor 500, it is important to form these interfaces without mixing impurities. As a method for suppressing the entry of impurities into these interfaces, a manufacturing method described in Patent Document 1 has been proposed.
In Patent Document 1, the base layer 503, the semiconductor layer 504, and the gate insulating film 505 are formed in a vacuum without being exposed to the atmosphere, and the interface between the base film 503 and the semiconductor layer 504, and the semiconductor layer 504 and the gate insulating film are formed. By making the interface with 505 clean, the thin film transistor 500 having a stable threshold voltage and high driving capability can be manufactured.

JP 2000-260995 A

  In the manufacturing method of Patent Document 1, when a base material (quartz substrate) on which a thin film transistor is formed has a source of impurities that adversely affect transistor characteristics, there is a problem that the impurities may be affected by heat. was there. Specifically, when a thin film transistor is formed on a base material after forming a constituent element such as a prism or a microlens that improves the optical characteristics of the liquid crystal device on the base material, the transistor characteristics are included in the constituent element. If impurities that adversely affect the temperature are included, for example, in a process at a high temperature of 600 ° C. or higher, there is a problem that the impurities may be affected by the diffused impurities.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

  Application Example 1 An electro-optical device according to this application example includes a substrate, a first dielectric layer covering a first surface of the substrate, a barrier layer covering at least a part of the first dielectric layer, A second dielectric layer sandwiching the barrier layer with the first dielectric layer; and a transistor semiconductor layer formed above the second dielectric layer, wherein the barrier layer is disposed Is overlapped with the channel region of the semiconductor layer when viewed from the normal direction of the first surface, and is the same as or larger than the channel region.

  According to this application example, when there is an impurity that adversely affects the transistor characteristics on the first surface of the substrate on which the transistor is formed, the barrier layer disposed between the substrate and the semiconductor layer has the impurity on the substrate side. From diffusion to the semiconductor layer side. The region where the barrier layer is disposed overlaps with the channel region of the semiconductor layer when viewed from the normal direction of the first surface of the substrate and is the same as or larger than the channel region. Diffusion into the channel region is suppressed by the barrier layer. Therefore, even when an impurity that adversely affects the transistor characteristics exists on the substrate over which the transistor is formed, deterioration of the transistor characteristics due to the impurities is suppressed. Therefore, an electro-optical device having stable electro-optical characteristics can be provided.

  Application Example 2 In the electro-optical device according to the application example described above, the constituent material of the barrier layer preferably includes any of aluminum oxide, polycrystalline silicon, and tungsten silicide.

  According to this application example, aluminum oxide, polycrystalline silicon, and tungsten silicide have an effect of suppressing diffusion of impurities such as halogens and alkali metals that adversely affect transistor characteristics. By forming the barrier layer using a material containing either silicon or tungsten silicide, diffusion of the impurity from the substrate side to the semiconductor layer can be suppressed.

  Application Example 3 In the electro-optical device according to the application example, it is preferable that the first dielectric layer is silicon oxide formed by plasma CVD using tetraethoxysilane gas.

  Silicon oxide formed by plasma CVD using tetraethoxysilane gas has excellent step coverage and is deposited at a higher speed than silicon oxide formed by plasma CVD using monosilane gas, for example. When a component such as a prism or a microlens is formed on a substrate on which a transistor is formed, it is necessary to cover the substrate with a thick film of silicon oxide to mitigate (suppress) the influence of the surface unevenness of the component. is there. Silicon oxide formed by plasma CVD using tetraethoxysilane gas can cover the surface irregularities of the component in a shorter time without gaps than silicon oxide formed by plasma CVD using monosilane gas. it can.

  Application Example 4 In the electro-optical device according to the application example described above, a third dielectric that sandwiches the scan line between the scan line that covers a part of the second dielectric layer and the second dielectric layer. A layer, a data line formed above the third dielectric layer, a pixel electrode formed above the third dielectric layer, and the scan line, the data line, and the pixel electrode. A first transistor and a second transistor connected to the first transistor through either the scan line or the data line, the transistor including the first transistor and the first transistor. It is preferable that two transistors are included.

  Since both the first transistor for controlling the pixel electrode and the second transistor for controlling the first transistor have a barrier layer disposed between the substrate and the semiconductor layer, impurities that adversely affect the transistor characteristics. Diffusion from the substrate side to the semiconductor layer side is suppressed.

  Application Example 5 In the electro-optical device according to the application example described above, the region where the scanning line is arranged is the area of the semiconductor layer of the first transistor as viewed from the normal direction of the first surface of the substrate. It is preferable that the channel region overlaps and is larger than the channel region of the first transistor.

  Between the semiconductor layer of the first transistor and the third dielectric layer (first surface of the substrate), it overlaps with the channel region of the semiconductor layer of the first transistor when viewed from the normal direction of the first surface of the substrate. Since the scanning line larger than the channel region is disposed, light traveling from the substrate side to the semiconductor side is blocked by the scanning line. Therefore, characteristic deterioration of the first transistor due to light traveling from the substrate side to the semiconductor layer side is suppressed. Therefore, an electro-optical device having stable electro-optical characteristics can be provided.

  Application Example 6 In the electro-optical device according to the application example described above, the electro-optical device that modulates incident light incident on the transistor side from the substrate side and emits the display light as display light. It is preferable that a prism is provided on the surface to reflect the incident light and make it a part of the display light.

  Incident light that is incident obliquely with respect to the normal direction of the first surface of the substrate and cannot be used as display light can be reflected by the prism and used as part of the display light. Brighter display can be realized.

  Application Example 7 In the electro-optical device according to the application example described above, the electro-optical device that modulates incident light incident on the transistor side from the substrate side and emits the display light as display light. The surface is preferably provided with a microlens that collects the incident light.

  Since the incident light is collected by the microlens, the utilization efficiency of the incident light can be improved and a brighter display can be realized.

  Application Example 8 An electronic apparatus according to this application example includes the electro-optical device described in the application example.

  An electronic apparatus according to this application example includes the electro-optical device described in the application example. In the electro-optical device, deterioration of transistor characteristics that influence the performance of the electro-optical device is suppressed by the barrier layer, and the prism and the microlens. A bright display is realized. For example, a projection display device, a projection type HUD (head-up display), a direct-view type HMD (head-mounted display), an electronic book, a personal computer, a digital still camera, a liquid crystal television, a viewfinder type or a monitor direct-view type video recorder By applying the electro-optical device described in the application example to an information terminal device such as a car navigation system, a POS, and an electronic device such as an electronic notebook, stable and bright display can be realized.

  Application Example 9 A method for manufacturing an electro-optical device according to this application example includes a substrate, a first dielectric layer that covers the first surface of the substrate, a barrier layer that covers at least a part of the first dielectric layer, and the A method for manufacturing an electro-optical device, comprising: a second dielectric layer sandwiching the barrier layer with a first dielectric layer; and a semiconductor layer of a transistor formed above the second dielectric layer. Depositing silicon oxide by plasma CVD using ethoxysilane gas to form the first dielectric layer; depositing one of aluminum oxide, polycrystalline silicon, and tungsten silicide, and forming the first surface of the substrate; Forming the barrier layer by patterning so as to overlap the channel region of the semiconductor layer as viewed from the normal direction and to be the same as or larger than the channel region; Depositing silicon oxide by plasma CVD using a run gas to form the second dielectric layer; and forming the semiconductor layer above the second dielectric layer. And

  Between the substrate and the semiconductor layer, any one of aluminum oxide, polycrystalline silicon, and tungsten silicide overlaps with the channel region of the semiconductor layer when viewed from the normal direction of the first surface of the substrate, and is the same as the channel region or A barrier layer is formed by patterning to be larger than the channel region. When impurities that adversely affect the transistor characteristics are present on the first surface of the substrate, the barrier layer suppresses diffusion of the impurities into the semiconductor layer, so that deterioration of the transistor characteristics due to the impurities is suppressed. Therefore, an electro-optical device having stable electro-optical characteristics can be provided.

(A) is a schematic plan view which shows the structure of the liquid crystal device which concerns on Embodiment 1, (b) is a schematic sectional drawing cut | disconnected by the J-J 'line | wire of (a). FIG. 3 is an equivalent circuit diagram illustrating an electrical configuration of the liquid crystal device according to the first embodiment. The schematic plan view which shows arrangement | positioning of a pixel electrode. FIG. 4 is a schematic cross-sectional view of the liquid crystal device taken along line A-A ′ in FIG. 3. The schematic plan view of the element layer arrange | positioned at a display area. The schematic plan view of the element layer arrange | positioned at a display area. FIG. 7 is a schematic cross-sectional view of an element layer taken along line B-B ′ in FIGS. 5 and 6. The schematic sectional drawing of the CMOS type TFT which comprises a circuit part. Process flow from the process of forming the prism to the process of forming the semiconductor layer. Fluorine concentration contained in the first dielectric layer and the second dielectric layer. Electrical characteristics of n-type TFT. 1 is a schematic cross-sectional view of a liquid crystal device 200 according to an embodiment. Schematic which shows the structure of a projection type display apparatus. FIG. 6 is a schematic cross-sectional view showing a structure of a thin film transistor in the prior art.

  Embodiments of the present invention will be described below with reference to the drawings. Such an embodiment shows one aspect of the present invention and does not limit the present invention, and can be arbitrarily changed within the scope of the technical idea of the present invention. In each of the following drawings, the scale of each layer or each part is made different from the actual scale so that each layer or each part can be recognized on the drawing.

(Embodiment 1)
"Outline of LCD device"
The liquid crystal device 100 according to the first embodiment is an example of an electro-optical device, and is a transmissive liquid crystal device including a thin film transistor (hereinafter referred to as TFT) 30. The liquid crystal device 100 according to the present embodiment can be suitably used as, for example, a light modulation element of a projection display device (liquid crystal projector) described later.

  First, an overall configuration of a liquid crystal device 100 as an electro-optical device according to the present embodiment will be described with reference to FIGS. 1 and 2. 1A is a schematic plan view showing the configuration of the liquid crystal device, FIG. 1B is a schematic cross-sectional view taken along the line JJ ′ of FIG. 1A, and FIG. 2 is an electrical configuration of the liquid crystal device. FIG.

  As shown in FIG. 1A and FIG. 1B, a liquid crystal device 100 according to this embodiment includes an element substrate 10 and a counter substrate 20 that are arranged to face each other, and a liquid crystal layer 50 that is sandwiched between the pair of substrates. And have.

  The element substrate 10 is slightly larger than the counter substrate 20. The two substrates are bonded via a seal material 52 arranged in a frame shape, and liquid crystal having positive or negative dielectric anisotropy is sealed in the gap. A liquid crystal layer 50 is formed. For the sealing material 52, for example, an adhesive such as a thermosetting or ultraviolet curable epoxy resin is employed. Spacers (not shown) are mixed in the sealing material 52 to keep the distance between the pair of substrates constant.

  A light shielding film 53 is similarly provided in a frame shape inside the sealing material 52 arranged in a frame shape. The light shielding film 53 is made of, for example, a light shielding metal or metal oxide, and the inside of the light shielding film 53 is the display region E. In the display area E, a plurality of pixels P are arranged in a matrix.

A data line driving circuit 101 is provided between one side portion of the element substrate 10 where the plurality of external connection terminals 102 are disposed and the sealing material 52 along the one side portion. A scanning line driving circuit 104 is provided inside the sealing material 52 along the other two sides that are orthogonal to the one side and face each other. A plurality of wirings 105 that connect the two scanning line driving circuits 104 are provided inside the sealing material 52 on the other side facing the one side. Wirings connected to the data line driving circuit 101 and the scanning line driving circuit 104 are connected to a plurality of external connection terminals 102 arranged along the one side.
Hereinafter, the direction along the one side is the X direction, the direction along the other two sides orthogonal to the one side and facing each other is the Y direction, and the direction from the element substrate 10 toward the counter substrate 20 is Z. This will be described as a direction.
The Z direction is an example of the “normal direction” in the present invention.

As shown in FIG. 1B, the element substrate 10 includes a substrate body 10a and an intermediate layer 10b and an element layer 10c that are sequentially stacked on the surface of the substrate body 10a on the liquid crystal layer 50 side.
The substrate body 10a is an example of the “substrate” in the present invention. The surface of the substrate body 10a on the liquid crystal layer 50 side is an example of the “first surface” in the present invention.

  The substrate body 10a includes a base material 8, a prism 110, and the like. A quartz substrate is used for the base material 8. The base material 8 should just be a translucent insulated substrate, for example, can use a glass substrate other than a quartz substrate. The prism 110 is provided on the surface of the substrate body 10a on the liquid crystal layer 50 side.

  The intermediate layer 10b is provided between the substrate body 10a and the element layer 10c. The intermediate layer 10b includes a first dielectric layer 35 covering the substrate body 10a, a barrier layer 33 covering at least a part of the first dielectric layer 35, and a first dielectric layer 35 sandwiching the barrier layer 33 between the first dielectric layer 35. It is composed of two dielectric layers 36 and the like.

  The element layer 10c is disposed so as to sandwich the intermediate layer 10b with the substrate body 10a, and a component for driving the liquid crystal layer 50 is provided. Specifically, the element layer 10c includes a pixel electrode 9a, a TFT 30 that drives the pixel electrode 9a, an alignment film 16 that covers these, and the like. Further, the above-described circuit portion (data line driving circuit 101, scanning line driving circuit 104), external connection terminal 102, wiring 105, and the like are also constituent elements of the element layer 10c.

The circuit portion (data line driving circuit 101, scanning line driving circuit 104) includes an n-channel transistor (hereinafter referred to as an n-type TFT) 202n and a P-channel transistor (hereinafter referred to as a p-type TFT) 202p. This circuit is composed of a CMOS type TFT 202 (see FIG. 8) or the like, and is formed in the same process as the TFT 30. The TFT 30 is also an n-channel transistor.
The TFT 30 is an example of a “first transistor” in the present invention, and a CMOS TFT 202 described later is an example of a “second transistor”.
Details of the substrate body 10a, the intermediate layer 10b, and the element layer 10c will be described later.

  The counter substrate 20 includes a counter substrate body 20a, light shielding films 21 and 53, a dielectric film 22, a counter electrode 23, an alignment film 24, and the like, which are sequentially stacked on the surface of the counter substrate body 20a on the liquid crystal layer 50 side. .

  A quartz substrate is used for the counter substrate body 20a. The counter substrate main body 20a may be a translucent insulating substrate, and for example, a glass substrate can be used in addition to the quartz substrate.

  The light shielding films 21 and 53 are made of, for example, a light shielding metal or metal oxide. As shown in FIG. 1A, the light shielding film 53 is provided in a frame shape at a position overlapping the scanning line driving circuit 104 in a plan view. The light shielding film 21 is provided at a position overlapping the TFT 30 in plan view. Accordingly, the light incident on the element substrate 10 from the counter substrate 20 is shielded, and the malfunction of the scanning line driving circuit 104 and the TFT 30 due to the light is prevented. Further, unnecessary stray light is shielded so as not to enter the display area E, and a high contrast in the display of the display area E is ensured.

  The dielectric film 22 is a translucent inorganic insulating material, and for example, a silicon oxide film formed by using a normal pressure or low pressure CVD method can be used. The film thickness is such that surface irregularities caused by the formation of the light shielding films 21 and 53 on the counter substrate body 20a can be alleviated.

  The counter electrode 23 is made of a transparent conductive film such as ITO, and is formed over the display region E. As shown in FIG. 1A, the counter electrode 23 is electrically connected to the wiring on the element substrate 10 side by vertical conduction portions 106 provided at the four corners of the counter substrate 20.

  The alignment film 16 covering the pixel electrode 9a and the alignment film 24 covering the counter electrode 23 are set based on the optical design of the liquid crystal device 100, and in this embodiment, an obliquely deposited film (inorganic film) of an inorganic material such as silicon oxide is used. Alignment film) is used. The alignment films 16 and 24 may be organic alignment films such as polyimide.

  As shown in FIG. 2, the liquid crystal device 100 extends in parallel with the plurality of scanning lines 11 a and the plurality of data lines 6 a as signal lines that are insulated and orthogonal to each other at least in the display region E, and the data lines 6 a. Capacity wiring 400 to be used. Note that the arrangement of the capacitor wiring 400 is not limited to this, and the capacitor wiring 400 may be arranged to extend in parallel with the scanning line 11a.

  A pixel electrode 9a, a TFT 30, and a storage capacitor 70 are provided in a region divided by the scanning line 11a and the data line 6a, and these constitute a pixel circuit of the pixel P.

  The scanning line 11 a is electrically connected to the gate of the TFT 30, and the data line 6 a is electrically connected to the source of the TFT 30. The pixel electrode 9 a is electrically connected to the drain of the TFT 30. Thus, the scanning line 11a, the data line 6a, and the pixel electrode 9a are connected to the TFT 30.

The data line 6a is connected to the data line driving circuit 101 (see FIG. 1), and supplies the image signals S1, S2,..., Sn supplied from the data line driving circuit 101 to the pixel P (TFT 30). The scanning line 11a is connected to the scanning line driving circuit 104 (see FIG. 1), and supplies scanning signals G1, G2,..., Gm supplied from the scanning line driving circuit 104 to the pixel P (TFT 30). Thus, the CMOS type TFT 202 constituting the data line driving circuit 101 is connected to the TFT 30 via the sample holder circuit and the data line 6a. The CMOS type TFT 202 constituting the scanning line driving circuit 104 is connected to the TFT 30 through the scanning line 11a.
Note that the image signals S1 to Sn supplied from the data line driving circuit 101 to the data lines 6a may be supplied in this order in a line sequential manner, and supplied to each of a plurality of adjacent data lines 6a for each group. May be. The scanning line driving circuit 104 supplies the scanning signals G1 to Gm to the scanning line 11a in a pulse-sequential manner at a predetermined timing.

  In the liquid crystal device 100, the TFT 30 as a switching element is turned on for a certain period by the input of the scanning signals G1 to Gm, so that the image signals S1 to Sn supplied from the data line 6a are turned on at a predetermined timing. Thus, the pixel electrode 9a is written. The predetermined level of image signals S1 to Sn written to the liquid crystal layer 50 through the pixel electrode 9a is held for a certain period between the pixel electrode 9a and the counter electrode 23 arranged to face the liquid crystal layer 50. The

  In order to prevent the held image signals S1 to Sn from leaking, a storage capacitor 70 is connected in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode 23. The storage capacitor 70 is provided between the drain of the TFT 30 and the capacitor wiring 400. As will be described in detail later, one of the pair of electrodes constituting the storage capacitor 70 functions as the capacitor wiring 400.

  Such a liquid crystal device 100 is a transmission type, and the transmittance of the pixel P when the voltage is not applied is larger than the transmittance when the voltage is applied, and a normally white mode where a bright display is obtained, or when no voltage is applied. The normally black mode optical design is adopted in which the transmittance of the pixel P is smaller than the transmittance at the time of voltage application and dark display is achieved. Depending on the optical design, polarizing elements (not shown) are respectively used on the light incident side and the light emitting side.

"Outline of element substrate"
Next, an outline of the element substrate 10 will be described for each component (substrate body 10a, intermediate layer 10b, element layer 10c) of the element substrate 10.
FIG. 3 is a schematic plan view showing the arrangement of the pixel electrodes. 4 is a schematic cross-sectional view of the liquid crystal device taken along line AA ′ of FIG. 5 and 6 are schematic plan views of element layers arranged in the display region E. FIG. FIG. 7 is a schematic cross-sectional view of the element layer cut along the line BB ′ in FIGS. 5 and 6. FIG. 8 is a schematic cross-sectional view of a CMOS type TFT constituting a circuit portion (data line driving circuit 101, scanning line driving circuit 104) arranged around the display area E.
For convenience of explanation, the constituent elements of the intermediate layer 10b are shown by two-dot chain lines in FIGS.

As shown in FIG. 3, the pixel electrode 9a is provided for each pixel P, and is arranged in a matrix in the X direction and the Y direction. The shape of the pixel electrode 9a is a quadrangle (square). When viewed from the Z direction, the outer edge of the pixel electrode 9a is formed of light shielding films 21 and 53 provided on the counter substrate 20 and signal lines (data line 6a, scanning line 11a, and capacitor wiring 400 provided on an element layer 10c described later). ) Or the like, and is arranged so as to overlap with the light-shielding non-opening region D2. In addition, a region surrounded by the non-opening region D2 is a translucent opening region D1. In the present embodiment, the width of the non-opening region D2 in the X direction and the Y direction is set to be the same.
Although not shown in FIG. 3, the TFT 30, the storage capacitor 70, the prism 110, and the like provided for each pixel electrode 9a are arranged in the non-opening region D2.

"Board body"
In FIG. 4, arrows with reference signs L <b> 1 and L <b> 2 indicate incident light emitted from a light source (not shown) and incident on the element substrate 10. Light emitted from the light source is incident from the element substrate 10 side toward the counter substrate 20 side. The liquid crystal device 100 of the present embodiment is a light modulation element (light valve) that can be suitably used for a liquid crystal projector described later, and the Z direction is the optical axis of the liquid crystal projector. Incident light L1 indicated by a solid line in the drawing is light traveling along the optical axis direction, and incident light L2 indicated by a broken line is light traveling in an oblique direction with respect to the optical axis. The light emitted from the liquid crystal device 100 in the Z direction becomes display light of the liquid crystal projector.

  The insulating layer 40 of the element layer 10c in the figure includes a first interlayer insulating film 41, a dielectric layer 75, a second interlayer insulating film 42, a third interlayer insulating film 43, and a fourth interlayer insulating film 44, which will be described later. (See FIG. 7). Since these constituent elements of the insulating layer 40 are made of a light-transmitting material having substantially the same refractive index, the insulating layer 40 has a high transmittance with respect to the incident lights L1 and L2.

  As shown in FIG. 4, a prism 110 serving as a light reflecting portion is provided on the surface of the substrate body 10a on the liquid crystal layer 50 side. The prism 110 includes a groove portion 111 having a V-shaped cross section formed by etching the base material 8 so as to open toward the liquid crystal layer 50, a sealing portion 114 that seals an opening portion of the groove portion 111, and the groove portion 111. And a sealed air layer 113.

The inclined surface 112 formed by the groove 111 is an interface between the base material 8 and the air layer 113 having a refractive index lower than that of the base material 8 (quartz), and light incident on the inclined surface 112 is totally reflected. It is like that. In addition, the area | region enclosed by the groove part 111 and the sealing part 114 should just be filled with the low refractive index material rather than the base material 8 (quartz), for example, may be a vacuum (reduced pressure atmosphere).
Such a prism 110 is provided in the non-opening region D2 surrounding the opening region D1.

The light (incident light L1) incident on the opening region D1 along the optical axis direction passes through the opening region D1, is emitted in the Z direction, and becomes display light. Light that is oblique to the optical axis (incident light L2) is totally reflected in the Z direction by the inclined surface 112 of the prism 110 and becomes part of the display light. Light that is oblique to the optical axis (incident light L2) is light that enters the non-opening region D2, and is light that is blocked by the non-opening region D2 if the prism 110 is not formed. Light oblique to the optical axis (incident light L2) is reflected by the prism 110, passes through the aperture region D1, and exits in the Z direction to become display light.
As described above, the prism 110 can also use the incident light L2 oblique to the optical axis as display light in addition to the incident light L1 along the optical axis direction, so that the prism 110 is not formed. The utilization efficiency of incident light can be increased, and a brighter display is realized.

"Middle class"
As shown in FIG. 4, the intermediate layer 10b includes a first dielectric layer 35, a barrier layer 33, and a second dielectric layer 36 that are sequentially stacked on the surface of the substrate body 10a on the liquid crystal layer 50 side. Yes.
The first dielectric layer 35 is a silicon oxide film that covers the surface of the substrate body 10a on the liquid crystal layer 50 side, and has a film thickness of approximately 2000 nm to 4000 nm. The barrier layer 33 is an aluminum oxide film (Al ₂ O ₃ ) that covers at least a part of the first dielectric layer 35 and has a film thickness of approximately 50 nm to 100 nm. The second dielectric layer 36 is a silicon oxide film disposed so as to sandwich the barrier layer 33 with the first dielectric layer 35, and has a film thickness of approximately 800 nm to 1000 nm.

"Element layer"
First, the outline of the element layer 10c (pixel P) arranged in the display area E will be described.
As shown in FIG. 7, the element layer 10c in the display region E is, in order from the surface on the intermediate layer 10b side, a first layer including the scanning lines 11a and the like, a second layer including the TFTs 30 and the like, a first layer including the storage capacitors 70 and the like. It consists of three layers, a fourth layer including the data lines 6a and the like, a fifth layer including the capacitor wiring 400 and the like, and a sixth layer (uppermost layer) including the pixel electrodes 9a and the alignment film 16 and the like. In addition, the base insulating layer 12 is provided between the first layer and the second layer, the first interlayer insulating film 41 is provided between the second layer and the third layer, and the layer between the third layer and the fourth layer. Includes a second interlayer insulating film 42, a third interlayer insulating film 43 between the fourth layer and the fifth layer, a fourth interlayer insulating film 44 between the fifth layer and the sixth layer, Each is provided to prevent the above-described elements from being short-circuited. The various insulating films 12, 41, 42, 43, and 44 are also provided with, for example, a contact hole 81 that electrically connects the high concentration source region 1d in the semiconductor layer 1a of the TFT 30 and the data line 6a. It has been. Note that the first layer to the third layer are shown in FIG. 5 as the lower layer portion, and the fourth layer to the sixth layer are shown in FIG. 6 as the upper layer portion.
Hereinafter, each of these elements will be described in order from the bottom with reference to FIGS.

(Structure of the first layer-scanning line, etc.)
In the first layer, a scanning line 11a made of tungsten silicide (WSi) is provided. As a material constituting the scanning line 11a, in addition to tungsten silicide, for example, at least one of refractory metals such as Ti, Cr, W, Ta, and Mo, a simple metal, an alloy, a metal silicide, a poly Silicides and stacked layers thereof may be used. Thus, the scanning line 11a is made of a light-shielding material and forms part of the non-opening region D2. The scanning lines 11a are patterned in a stripe shape so as to be along the X direction in FIG. More specifically, the stripe-shaped scanning line 11a includes a main line portion extending along the X direction in FIG. 5 and a protruding portion extending in the Y direction in FIG. 5 where the data line 6a or the capacitor wiring 400 extends. ing.

  As viewed from the Z direction, the region where the scanning line 11a is disposed overlaps a channel region 1a 'of a semiconductor layer 1a described later and is larger than the channel region 1a'. Accordingly, the scanning line 11a blocks light that is about to enter the TFT 30 from below, and suppresses malfunction of the TFT 30 due to light.

(Structure of the second layer-TFT etc.)
Next, the TFT 30 including the gate electrode 3a is provided as the second layer. The TFT 30 includes a gate electrode 3a made of a conductive polycrystalline silicon film, a semiconductor layer 1a made of a polycrystalline silicon film, and a gate insulating film 2 made of a silicon oxide film that insulates the gate electrode 3a from the semiconductor layer 1a. ing. The TFT 30 includes a high concentration source region 1d, a channel region 1a ′, a high concentration drain region 1e, and a junction region (low concentration source region 1b) formed between the high concentration source region 1d and the channel region 1a ′. The semiconductor layer 1a has an LDD (Lightly Doped Drain) structure having a junction region (low concentration drain region 1c) formed between the channel region 1a 'and the high concentration drain region 1e (see FIG. 7). ).

  As viewed from the Z direction, the channel region 1 a ′ of the semiconductor layer 1 a overlaps with the barrier layer 33 provided in the intermediate layer 10 b and is smaller than the barrier layer 33. In other words, as viewed from the Z direction, the region where the barrier layer 33 is disposed overlaps the channel region 1a 'of the semiconductor layer 1a and is larger than the channel region 1a'. Note that, as viewed from the Z direction, the region where the barrier layer 33 is disposed may overlap the channel region 1a 'of the semiconductor layer 1a and be the same as the channel region 1a'.

  A relay electrode 719 is formed in the same layer as the gate electrode 3a. As shown in FIG. 5, the relay electrode 719 is formed in an island shape so as to be positioned approximately at the center of one side extending in the X direction of each pixel electrode 9 a as viewed in a plan view. The relay electrode 719 and the gate electrode 3a are formed as the same film.

(Configuration between the first layer and the second layer-base insulating layer-)
A base insulating layer 12 made of a silicon oxide film is provided on the scanning line 11 a described above and below the TFT 30. The base insulating layer 12 is an example of the “third dielectric layer” in the present invention.

  The base insulating layer 12 is provided with groove-shaped contact holes 12cv along the channel length direction of the semiconductor layer 1a extending along the data line 6a described later on both sides of the semiconductor layer 1a in plan view. Yes. Corresponding to the contact hole 12cv, the gate electrode 3a stacked thereabove includes a portion formed in a concave shape on the lower side. A gate electrode 3a is formed so as to fill the entire contact hole 12cv, and a side wall portion 3b formed integrally with the gate electrode 3a extends. The gate electrode 3a and the scanning line 11a are connected via the contact hole 12cv and are always at the same potential.

(3rd layer configuration-storage capacity, etc.)
In the third layer, a storage capacitor 70 is provided. The storage capacitor 70 includes a lower electrode 71 as a pixel potential side capacitor electrode connected to the high concentration drain region 1e of the TFT 30 and the pixel electrode 9a, and a capacitor electrode 300 as a fixed potential side capacitor electrode. Are formed so as to face each other (see FIG. 7). According to the storage capacitor 70, it is possible to remarkably improve the potential holding characteristic in the pixel electrode 9a. Further, as shown in FIG. 5, the storage capacitor 70 is formed so as not to reach the light transmission region substantially corresponding to the formation region of the pixel electrode 9a (in other words, fits in the non-opening region D2. Therefore, the pixel aperture ratio of the liquid crystal device 100 is kept relatively large, and a brighter display can be provided.

  More specifically, the lower electrode 71 is made of, for example, a conductive polycrystalline silicon film and functions as a pixel potential side capacitor electrode. The lower electrode 71 has a function of relaying and connecting the pixel electrode 9a and the high concentration drain region 1e of the TFT 30 in addition to a function as a pixel potential side capacitor electrode. Incidentally, the relay connection here is performed through the relay electrode 719.

  The capacitor electrode 300 functions as a fixed potential side capacitor electrode of the storage capacitor 70. The capacitor electrode 300 is electrically connected to a later-described capacitor wiring 400 and has the same potential (fixed potential) as that of the capacitor wiring 400. The capacitor electrode 300 includes at least one of refractory metals such as Ti, Cr, W, Ta, and Mo, a simple metal, an alloy, a metal silicide, a polysilicide, a laminate of these, or preferably tungsten silicide. Consists of. Alternatively, depending on the subsequent processes, a low resistance material having light shielding properties such as aluminum may be used. As described above, the capacitor electrode 300 is made of a light-shielding material and forms a part of the non-opening region D2. The capacitor electrode 300 has a function of blocking light that is about to enter the TFT 30 from above.

As shown in FIG. 7, the dielectric layer 75 is a silicon oxide film such as a relatively thin HTO (High Temperature Oxide) film, LTO (Low Temperature Oxide) film having a thickness of about 5 to 200 nm, a silicon nitride film, or the like. Consists of Alternatively, a high dielectric constant film such as aluminum oxide, tantalum oxide, or hafnium oxide may be used.
Specifically, the dielectric layer 75 has a two-layer structure in which the lower layer is a silicon oxide film 75a and the upper layer is a silicon nitride film 75b.

(Configuration between the second layer and the third layer-first interlayer insulating film-)
On the gate electrode 3a and the relay electrode 719 and below the storage capacitor 70, for example, NSG (non-silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphorus silicate glass). A first interlayer insulating film 41 made of silicate glass film, silicon nitride film, silicon oxide film, or the like, or preferably NSG is formed.

  A contact hole 81 that electrically connects the high-concentration source region 1d of the TFT 30 and a data line 6a described later is formed in the first interlayer insulating film 41 so as to penetrate the second interlayer insulating film 42 described later. Has been. The first interlayer insulating film 41 is provided with a contact hole 83 that electrically connects the high-concentration drain region 1 e of the TFT 30 and the lower electrode 71 constituting the storage capacitor 70. Further, the first interlayer insulating film 41 is provided with a contact hole 881 for electrically connecting the lower electrode 71 serving as a pixel potential side capacitor electrode constituting the storage capacitor 70 and the relay electrode 719. . Further, a contact hole 882 for electrically connecting the relay electrode 719 and a second relay electrode 6a2 described later is formed in the first interlayer insulating film 41 through the second interlayer insulating film 42 described later. Has been.

(Fourth layer configuration-data lines, etc.)
A data line 6a is provided in the fourth layer. As shown in FIG. 7, the data line 6a is formed as a film having a two-layer structure of an aluminum layer (reference numeral 41A in FIG. 7) and a titanium nitride layer (reference numeral 41TN in FIG. 7) in order from the lower layer. ing. The data line 6a is made of a light shielding material and forms a part of the non-opening region D2.

  In the fourth layer, the capacitor wiring relay layer 6a1 and the second relay electrode 6a2 are formed as the same film as the data line 6a. As shown in FIG. 6, when viewed in plan, for example, when attention is paid to the data line 6a located on the leftmost side of FIG. 6, the capacitor wiring relay layer 6a1 having a substantially quadrilateral shape on the right side thereof, Further, a second relay electrode 6a2 having a substantially quadrilateral shape having a slightly larger area than the capacitor wiring relay layer 6a1 is formed on the right side, and is formed so as to be divided.

  The capacitor wiring relay layer 6a1 and the second relay electrode 6a2 are formed as the same film as the data line 6a, and have a two-layer structure of an aluminum layer 41A and a titanium nitride layer 41TN in order from the lower layer.

(Configuration between the third layer and the fourth layer—second interlayer insulating film)
A plasma CVD method using a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like, or preferably TEOS gas, is provided above the storage capacitor 70 and the data line 6a. A second interlayer insulating film 42 formed by the above is formed. The second interlayer insulating film 42 is provided with the contact hole 81 for electrically connecting the high-concentration source region 1d of the TFT 30 and the data line 6a, and the relay layer 6a1 for capacitive wiring. A contact hole 801 is formed to electrically connect the capacitor electrode 300 as the upper electrode of the storage capacitor 70. Further, the contact hole 882 is formed in the second interlayer insulating film 42 for electrically connecting the second relay electrode 6a2 and the relay electrode 719.

(Fifth layer configuration-capacitive wiring, etc.)
In the fifth layer, the capacitor wiring 400 is formed. When viewed in plan, the capacitor wiring 400 is formed so as to extend in the Y direction and cover the data line 6a, as shown in FIG. The capacitor wiring 400 extends from the display area E in which the pixel electrode 9a is disposed to the periphery thereof, and is electrically connected to a constant potential source to have a fixed potential.

  In the fourth layer, a third relay electrode 402 is formed as the same film as the capacitor wiring 400. The third relay electrode 402 has a function of relaying an electrical connection between the second relay electrode 6a2 and the pixel electrode 9a through contact holes 804 and 89 described later. The capacity wiring 400 and the third relay electrode 402 are not continuously formed in a planar shape, but are formed so as to be separated from each other by patterning.

  The capacitor wiring 400 and the third relay electrode 402 described above have a two-layer structure in which a lower layer is made of aluminum and an upper layer is made of titanium nitride. As described above, the capacitor wiring 400 and the third relay electrode 402 are made of a light-shielding material and form a part of the non-opening region D2.

(Configuration between the fourth layer and the fifth layer-third interlayer insulating film-)
A third interlayer insulating film 43 made of a silicon nitride film, a silicon oxide film, or the like is formed on the data line 6a described above and below the capacitor wiring 400. The third interlayer insulating film 43 includes a contact hole 803 for electrically connecting the capacitor wiring 400 and the capacitor wiring relay layer 6a1, and the third relay electrode 402 and the second relay electrode 6a2. Contact holes 804 for electrical connection are respectively opened.

(Structure between the sixth layer and the fifth layer and the sixth layer-pixel electrode, etc.)
As described above, the pixel electrode 9a is formed in an island shape (matrix shape) for each pixel P on the sixth layer, and the alignment film 16 is formed on the pixel electrode 9a. Under the pixel electrode 9a, a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like, or a fourth interlayer insulating film 44 preferably made of NSG is formed. In the fourth interlayer insulating film 44, a contact hole 89 for electrically connecting the pixel electrode 9a and the third relay electrode 402 is formed. Between the pixel electrode 9a and the TFT 30, the contact hole 89, the third relay electrode 402, the contact hole 804, the second relay electrode 6a2, the contact hole 882, the relay electrode 719, the contact hole 881, the lower electrode 71, and the contact described above. It is electrically connected through the hole 83.

(Circuit part-CMOS type TFT etc.)
Next, an outline of the element layer 10c (circuit unit (scanning line driving circuit 104, data line driving circuit 101)) arranged around the display area E will be described. As described above, the circuit portion (the scanning line driving circuit 104 and the data line driving circuit 101) includes the CMOS type TFT 202 including the n type TFT 202n and the p type TFT 202p.

  FIG. 8 is a schematic cross-sectional view of a CMOS type TFT constituting the circuit portion. Hereinafter, an outline of the CMOS type TFT 202 will be described with reference to FIG.

  As shown in FIG. 8, the CMOS TFT 202 includes a p-type TFT 202p and an n-type TFT 202n, which are respectively formed in the semiconductor layer 202a, the gate insulating film 2, the gate electrode film 202b, the drain region and the source region of the semiconductor layer 202a. It consists of various electrodes 210a, 210b, 210c, 210d and wiring 220 to be connected. As can be seen from the reference numerals 12, 41, 42, 43, and 44 shown in FIG. 8, the CMOS TFT 202 and the structure on the upper side thereof are provided in the display area E shown in FIG. It is formed in the same process as the element layer 10c (pixel P). For example, the semiconductor layer 202a is formed in the same process as the semiconductor layer 1a of the TFT 30, and the gate electrode film 202b is formed in the same process as the gate electrode 3a. For the lower electrode 71 and the capacitor electrode 300 constituting the storage capacitor 70 shown in FIG. 7, the wiring films 711 and 712 formed in the same process as those shown in FIG. , 210c, 210d. Further, the two-layered film (the layer 41A made of aluminum and the layer 41TN made of titanium nitride) constituting the data line 6a in FIG. 7 is also formed in the wiring film 222 formed in the same process in FIG. , 223 constitute the wiring 220. Note that a thin film may be formed in the same process as the capacitor wiring 400 in FIG. 7 and used as part of the configuration of the CMOS TFT 202 (for example, wiring).

  The portion of the semiconductor layer 202a that is disposed to face the gate electrode 202b with the gate insulating film 2 interposed therebetween becomes a channel region 202a 'of the semiconductor layer 202a. As viewed from the Z direction, the channel region 202 a ′ of the semiconductor layer 202 a overlaps with the barrier layer 33 provided in the intermediate layer 10 b and is smaller than the barrier layer 33. In other words, when viewed from the Z direction, the region where the barrier layer 33 is disposed overlaps with the channel region 202a 'of the semiconductor layer 202a and is larger than the channel region 202a'. As viewed from the Z direction, the region where the barrier layer 33 is disposed may overlap with the channel region 202a 'of the semiconductor layer 202a and have the same size as the channel region 202a'.

  The liquid crystal device 100 is incorporated in an electronic device such as a liquid crystal projector described later in a state where the liquid crystal device 100 is mounted by a shield case (not shown). Light incident on the circuit portion (the scanning line driving circuit 104 and the data line driving circuit 101) is shielded by the shield case. Since the vicinity of the display area E is not covered with the shield case, it is necessary to shield the light incident on the circuit portion with the light shielding film. Incident light L1, L2 (FIG. 4) traveling from the element substrate 10 side near the display region E toward the counter substrate 20 side is blocked by a light shielding film (not shown) formed in the same process as the scanning line 11a. Is done. Light (for example, reflected light of incident light L1 and L2) traveling from the counter substrate 20 side in the vicinity of the display region E toward the element substrate 10 side is shielded by a wiring layer having a light shielding property disposed on the upper layer. The That is, in the region where the CMOS TFT 202 is disposed, a region where a light shielding film formed in the same process as the scanning line 11a is provided (not shown), and a region where no light shielding film is provided (FIG. 8). Exists.

  Thus, by forming the configuration in the display region E (TFT 30, storage capacitor 70, wiring, etc.) and the configuration in the peripheral region of the display region E (CMOS TFT 202, wiring, etc.) in the same process, The manufacturing process can be simplified or omitted as compared with the case of forming separately.

"Method for manufacturing element substrates"
FIG. 9 is a process flow from the process of forming the prism to the process of forming the semiconductor layer, which is a characteristic part of the present invention. Hereinafter, an outline of a method for manufacturing a characteristic portion of the element substrate will be described with reference to FIG. In addition, after the process of forming the semiconductor layers 1a and 202a, a known technique is used, and the description of the manufacturing method of the element substrate 10 is omitted.

  As shown in FIGS. 7 and 8, at least one of the first dielectric layer 35 and the first dielectric layer 35 covering the surface on which the prism 110 is formed on the surface of the substrate body 10a on the liquid crystal layer 50 side. The second dielectric layer 36 sandwiching the barrier layer 33 between the barrier layer 33 covering the portion, the first dielectric layer 35, the scanning line 11a covering a part of the second dielectric layer, the second dielectric layer 36, A base insulating layer 12 sandwiching the scanning line 11a therebetween, and semiconductor layers 1a and 202a films covering a part of the base insulating layer 12 are formed in this order.

  As shown in FIG. 9, in step S1, the base material 8 is etched by a known technique, for example, dry etching to form a groove 111 having a V-shaped cross section. A silicon oxide film is deposited on the surface of the substrate 8 on which the groove 111 is formed by a known technique such as a sputtering method or a CVD method so as to close the opening of the groove 111 to form a sealing portion 114. At this time, the inside of the groove 111 is sealed in an atmosphere (depressurized atmosphere) when depositing the silicon oxide film. As a result, a prism having the groove 111, a sealing portion 114 that seals the opening of the groove 111, and an air layer 113 (depressurized atmosphere) sealed in the groove 111 is formed (see FIG. 4).

If it is difficult to block the opening of the groove 111 simply by depositing the silicon oxide film described above, polysilicon or the like, which is a sacrificial film, is embedded in the groove 111 in advance, and is buried by a damascene method. Turn into. A first silicon oxide film is formed thereon. Furthermore, a small hole for etching is formed in the first silicon oxide film, and the sacrificial film is selectively removed by etching, whereby the groove 111 is made hollow. Thereafter, a prism 110 in which the air layer 113 is sealed inside the groove 111 can be formed by depositing a second silicon oxide film and closing the etching hole.
Alternatively, a low refractive index silicon oxide film containing an impurity such as fluorine may be deposited inside the groove 111.

In step S3, aluminum oxide having a thickness of 50 nm to 100 nm is formed by a known technique such as ALD (atomic layer deposition) using TMA (trimethylaluminum Al (CH ₃ ) ₃ ) or MOCVD (Metal Organic Chemical Vapor Deposition). accumulate. Next, using a known technique (for example, dry etching), the channel region 1a ′ of the semiconductor layer 1a and the channel region 202a ′ of the semiconductor layer 202a overlap with the channel region 1a ′ of the semiconductor layer 1a, as viewed from the Z direction. The barrier layer 33 is formed by patterning aluminum oxide so as to be larger than the channel region 202a ′ of the semiconductor layer 202a.

  Note that when viewed from the Z direction, the channel region 1a ′ of the semiconductor layer 1a and the channel region 202a ′ of the semiconductor layer 202a overlap with each other, and the channel region 1a ′ of the semiconductor layer 1a and the channel region 202a ′ of the semiconductor layer 202a have the same size. Thus, the barrier layer 33 may be formed by patterning aluminum oxide.

  Aluminum oxide is a translucent dielectric, and patterning by a known technique may be omitted, and the barrier layer 33 may be formed covering the entire surface of the first dielectric layer 35. In this case, the barrier layer 33 is also disposed in the opening region D1, and the interface between the first dielectric layer 35 (silicon oxide film) and the barrier layer 33 (aluminum oxide), and the barrier layer (aluminum oxide) and the second dielectric material. At the interface with the layer 36 (silicon oxide film), a light reflecting surface based on the difference in refractive index between the silicon oxide film and the aluminum oxide is formed. As a result, light is reflected at these interfaces, and the luminance of display light emitted from the liquid crystal device 100 may be lowered. Therefore, the barrier layer 33 may be patterned so as to be disposed in the non-opening region D2. More preferable.

In step S4, a silicon oxide film having a thickness of 800 nm to 1000 nm is deposited by a plasma CVD method using monosilane (SiH ₄ ) gas, and a planarization process is performed by a CMP process to form a second dielectric layer 36.

  In step S5, tungsten silicide is deposited using sputtering or MOCVD. Thereafter, using a known technique (dry etching), the pattern is formed so as to overlap with the channel region 1a 'of the semiconductor layer 1a and be larger than the channel region 1a' when viewed from the Z direction, thereby forming the scanning line 11a.

  In step S6, a silicon oxide film having a thickness of about 400 nm is deposited by plasma CVD using monosilane gas, and a silicon oxide film having a thickness of about 50 nm is deposited in this order by thermal CVD using monosilane gas. 12 is formed.

  In step S7, an amorphous silicon film is deposited by a thermal CVD method using monosilane gas, and heat treatment is performed at a temperature of 600 ° C. to 700 ° C. to crystallize the amorphous to form a polycrystalline silicon film. Next, the semiconductor layers 1a and 202a are formed by patterning using a known technique (dry etching). The semiconductor layer 1a overlaps the scanning line 11a when viewed from the Z direction, and is smaller than the scanning line 11aa. Further, the channel region 1 a ′ of the semiconductor layer 1 a and the channel region 202 a ′ of the semiconductor layer 202 a overlap with the barrier layer 33 when viewed from the Z direction and are smaller than the barrier layer 33.

  In the process after step S6, that is, the process from the process of forming the first interlayer insulating film 41 to the process of forming the pixel electrode 9a, it is performed at 300 ° C. in a hydrogen gas atmosphere or a mixed gas atmosphere of hydrogen gas and nitrogen gas. A heat treatment at ˜400 ° C. is performed, and dangling bond termination treatment (hydrogen treatment) of the semiconductor layers 1a and 202a is performed to stabilize the transistor characteristics.

Further, in order to form the low concentration source region 1b, the low concentration drain region 1c, the high concentration source region 1d, and the high concentration drain region 1e of the semiconductor layer 1a of the TFT 30, an n-type impurity such as phosphorus ion is introduced into the semiconductor layer 1a. doing. Further, in order to form a source electrode (source region) and a drain electrode (drain region), n-type impurities such as phosphorus ions are introduced into the semiconductor layer 202a of the n-type TFT 202n, and boron ions or the like are introduced into the semiconductor layer 202a of the p-type TFT 202p. P-type impurities are introduced. In order to diffuse these impurities in the semiconductor layers 1a and 202a, heat treatment (activation annealing) at 900 ° C. to 1100 ° C. is performed.
As described above, in the manufacturing process of the element substrate 10, heat treatment is performed by a film forming process for depositing the components of the element substrate 10, a hydrogen process, an activation annealing process, and the like.

"Changes in fluorine concentration due to heat treatment"
FIG. 10 shows the concentration of fluorine contained in the first dielectric layer and the second dielectric layer. In the figure, the upper part shows the fluorine concentration in the state immediately after film formation (as-deposited state), and the lower part shows the fluorine concentration after heat treatment at 900 ° C. for 200 seconds. A test substrate having the same structure as the actual substrate was prepared separately from the actual substrate, and the fluorine concentration in the region where the barrier layer 33 was not provided was measured using secondary ion mass spectrometry. The heat treatment conditions of the test substrate are 900 ° C. and 200 seconds, but more severe heat treatment is performed in the actual manufacturing process.

As shown in FIG. 10, the fluorine concentration of the first dielectric layer 35 was 8E19 to 4E20 atoms / cm ³ in the as-deposited state, and the fluorine ion concentration decreased to 4E19 to 5E19 atoms / cm ³ after the heat treatment. The fluorine concentration of the second dielectric layer 36 was 6E18 atoms / cm ³ in the as-deposited state, and the fluorine ion concentration increased to 4E19 to 6E19 atoms / cm ³ after the heat treatment. “E” indicates an exponent part, for example, “8E19” indicates 8 × 10 ¹⁹ .
Although not shown, the fluorine concentration of the base insulating layer 12 in the as-deposited state is equal to or less than the fluorine concentration of the second dielectric layer 36 and is in the range of 1E17 atoms / cm ^{3 to} E18 atoms / cm ^3. .

The first dielectric layer 35 of the test substrate is formed under the same conditions and the same apparatus as the first dielectric layer 35 in step S2 described above. The second dielectric layer 36 of the test substrate is formed under the same conditions and the same apparatus as the second dielectric layer 36 in step S4 described above. In step S2 and step S4, a fluorine-based gas such as CF ₄ , NF ₃ , or C ₂ F _{6 is} used to remove the silicon oxide film and by-products deposited on the inner wall surface of the film forming chamber of the film forming apparatus. A cleaning process (dry etching process) is periodically performed using the same. The first dielectric layer 35 and the second dielectric layer 36 are formed by different film forming apparatuses, and the first dielectric layer 35 is processed by an apparatus having excellent coverage characteristics and capable of high speed film formation. . However, on the other hand, due to the performance of the apparatus, there is also a drawback that a large amount of residual fluorine component at the time of cleaning is taken into the film.

  Fluorine mixed in the silicon oxide film diffuses (moves) from the high concentration region (first dielectric layer 35) toward the low concentration region (second dielectric layer 36) by heat treatment. For this reason, it is considered that the fluorine concentration of the first dielectric layer 35 decreased and the fluorine concentration of the second dielectric layer 36 increased due to the heat treatment.

From the above results, it is considered that the following phenomenon occurs in the manufacturing process of the element substrate 10 due to various heat treatments in the manufacturing process of the element substrate 10.
(1) Since the first dielectric layer 35, the second dielectric layer 36, and the base insulating layer 12 are made of the same material (silicon oxide film), fluorine mixed into the film when heat treatment is performed. Diffuses from the high concentration region side to the low concentration region side.
(2) The residual fluorine concentration mixed in the silicon oxide film of the first dielectric layer 35 is larger than that of the second dielectric layer 36 and the underlying insulating layer 12 due to the characteristics of the device.
(3) From (1) and (2), fluorine mixed in the silicon oxide film diffuses from the high concentration region (first dielectric layer 35) side toward the low concentration region side (underlying insulating layer 12). Then, the fluorine concentration of the base insulating layer 12 which is the base film of the semiconductor layers 1a and 202a increases.

"Electrical characteristics of transistors"
FIG. 11 shows the electrical characteristics (relationship between the gate voltage and the drain current) of the n-type TFT 202n when 0 V is applied to the source electrode, 10 V is applied to the drain electrode, and −5 to 20 V is applied to the gate electrode. The solid line in the figure is the electrical characteristic of the n-type TFT 202n (FIG. 8) having the barrier layer 33, and the broken line is the electrical characteristic of the n-type TFT 202n without the barrier layer 33 (hereinafter referred to as a comparative example TFT). .

  As shown in FIG. 11, the n-type TFT 202n provided with the barrier layer 33 has a small drain current (off current) of 1E-13 to 1E-12A when the gate voltage is -5V to 0V. Furthermore, the on / off ratio (ratio between on-current and off-current) is as large as 8 to 9 digits, and has good electrical characteristics.

The TFT of the comparative example in which the barrier layer 33 is not provided has a large off-current of 1E10-7 to 1E10-6A, an on / off ratio (ratio of on-current to off-current) as small as two digits, and undesirable electrical characteristics. have.
Although not shown, the TFT 30 provided with the barrier layer 33 has good electrical characteristics equivalent to those of the n-type TFT 202n provided with the barrier layer 33.

The difference in the electrical characteristics is considered to be due to the fluorine diffusion observed in FIG.
In the TFT of the comparative example in which the barrier layer 33 is not provided, as described above, the fluorine mixed into the first dielectric layer 35 due to various heat treatments in the manufacturing process of the element substrate 10 is caused to occur from the first dielectric layer 35 side. Diffusion toward the insulating layer 12 side increases the fluorine concentration of the base insulating layer 12 that is the base film of the semiconductor layers 1a and 202a. Furthermore, the fluorine diffused into the base insulating layer 12 is also diffused into the semiconductor layers 1a and 202a, and it is considered that the film quality of the semiconductor layers 1a and 202a is deteriorated. For example, when fluorine penetrates into the semiconductor layers 1a and 202a, a new defect is generated in the semiconductor layers 1a and 202a, and a problem that the leakage current of the semiconductor layers 1a and 202a increases is assumed. That is, by various heat treatments in the manufacturing process of the element substrate 10, the fluorine of the first dielectric layer 35 diffuses to the channel regions of the semiconductor layers 1a and 202a that control the switching operation, and the film quality of the channel regions of the semiconductor layers 1a and 202a. It is considered that the electrical characteristics of the comparative example TFT deteriorated because of the deterioration.

  In the n-type TFT 202n and the TFT 30 provided with the barrier layer 33, diffusion of fluorine mixed into the first dielectric layer 35 into the base insulating layer 12 is suppressed by the barrier layer. That is, since an increase in the fluorine concentration of the base insulating layer 12 in the region where the barrier layer 33 is provided is suppressed, deterioration in the film quality of the channel regions of the semiconductor layers 1a and 202a that control the switching operation is suppressed. Therefore, since the deterioration of the electrical characteristics of the n-type TFT 202n and TFT 30 is suppressed, the n-type TFT 202n and TFT 30 provided with the barrier layer 33 have good electrical characteristics.

  Thus, the first dielectric layer 35 is a source of impurities (fluorine) that degrade the electrical characteristics of the transistor, and the barrier layer 33 suppresses diffusion of the impurities into the channel regions of the semiconductor layers 1a and 202a. It has a function. Further, even if impurities such as halogen such as fluorine or an alkali metal that deteriorate the electrical characteristics of the transistor exist in the prism 110 formed in step S1, the barrier layer 33 causes the semiconductor layer 1a and 202a to reach the channel region. Since diffusion of the impurity is suppressed, deterioration of the electrical characteristics of the transistor can be suppressed.

  When the region where the barrier layer 33 is formed is smaller than the channel region of the semiconductor layers 1a and 202a when viewed from the Z direction, the diffusion of impurities that degrade the electrical characteristics of the transistor into the channel regions of the semiconductor layers 1a and 202a is performed. Since it becomes difficult to suppress, the region where the barrier layer 33 is formed is preferably larger than the channel regions of the semiconductor layers 1a and 202a. Further, as described above, when the barrier layer 33 is disposed in the opening region D1, the luminance of the display light may be reduced. Therefore, the region where the barrier layer 33 is formed is smaller than the non-opening region D2. Is preferred. That is, as viewed from the Z direction, the region where the barrier layer 33 is formed is preferably larger than the channel regions of the semiconductor layers 1a and 202a and is disposed in the non-opening region D2. Further, when viewed from the Z direction, the region where the barrier layer 33 is formed and the channel region of the semiconductor layers 1a and 202a may be the same.

  As a constituent material of the barrier layer 33, tungsten silicide or polycrystalline silicon can be used in addition to the above-described aluminum oxide. That is, the barrier layer 33 formed of tungsten silicide or polycrystalline silicon also suppresses the diffusion of impurities that degrade the electrical characteristics of the transistor, and suppresses the degradation of the electrical characteristics of the transistor in the same manner as the barrier layer 33 composed of aluminum oxide. can do.

(Embodiment 2)
The liquid crystal device 200 according to the second embodiment is different from the first embodiment in that a microlens 26 is formed on the element substrate 10. Specifically, the microlens 26 is formed on the surface of the substrate body 10a on the liquid crystal layer 50 side, and the prism 110 is formed in the first embodiment. Other configurations are the same as those in the first embodiment. It is.

  FIG. 12 is a schematic cross-sectional view of the liquid crystal device 200 according to the present embodiment, and corresponds to FIG. Hereinafter, with reference to FIG. 12, the liquid crystal device 200 according to the present embodiment will be described focusing on differences from the first embodiment. Moreover, about the same component as Embodiment 1, the same code | symbol is attached | subjected and the overlapping description is abbreviate | omitted.

  Arrows denoted by reference signs L3 and L4 in the drawing indicate incident light emitted from a light source (not shown) and incident on the liquid crystal device 200 from the element substrate 10 side toward the counter substrate 20 side. Incident lights L3 and L4 are collected by the microlens 26 and emitted from the liquid crystal device 200 in the Z (+) direction as display light traveling along the optical axis direction. The Z (+) direction is the optical axis.

As shown in FIG. 12, a microlens 26 as a condensing element is provided on the surface of the substrate body 10a on the liquid crystal layer 50 side. The microlens 26 is formed on the substrate body 10 a so that the convex lens surface 26 a faces away from the liquid crystal layer 50.
As a method for forming such a microlens 26, for example, the concave portion corresponding to the lens surface 26a is formed by selectively etching the surface of the substrate 8. The concave portion is filled with a lens material such as silicon oxynitride (SiON) having a higher refractive index than that of the substrate 8. Next, a microlens 26 having a convex lens surface 26a is formed for each pixel P by performing a flattening process by a method such as CMP.

  The incident light L3 is light that travels along the optical axis. The incident light L3 travels straight through the microlens 26, passes through the liquid crystal layer 50, and is emitted toward the counter substrate 20 to become display light. The incident light L4 is light that travels in an oblique direction with respect to the optical axis. The incident light L4 is refracted when it enters the microlens 26 and is emitted in a direction substantially along the optical axis. Therefore, the incident light L4 is emitted toward the counter substrate 20 substantially in parallel with the incident light L1, and a part of the display light Become. As described above, the incident light L4 traveling in an oblique direction with respect to the optical axis can be made part of the display light by the microlens 26, so that the utilization efficiency of the incident light is improved and a brighter display is provided. be able to.

  A barrier layer 33 is also provided in the CMOS TFT or TFT 30 of the second embodiment, and the diffusion of impurities (fluorine) into the channel regions of the semiconductor layers 1a and 202a is suppressed by the barrier layer 33, so that the electrical characteristics of the transistor are deteriorated. The effect equivalent to Embodiment 1 that can be suppressed can be acquired.

(Embodiment 3)
"Electronics"
FIG. 13 is a schematic diagram illustrating a configuration of a projection display device (liquid crystal projector) as an electronic apparatus. As shown in FIG. 13, a projection display apparatus 1000 as an electronic apparatus according to the present embodiment includes a polarization illumination apparatus 1100 arranged along the system optical axis L, and two dichroic mirrors 1104 and 1105 as light separation elements. Three reflection mirrors 1106, 1107, 1108, five relay lenses 1201, 1202, 1203, 1204, 1205, three transmissive liquid crystal light valves 1210, 1220, 1230 as light modulation means, and a light combining element As a cross dichroic prism 1206 and a projection lens 1207.

  The polarized light illumination device 1100 is generally configured by a lamp unit 1101 as a light source composed of a white light source such as an ultra-high pressure mercury lamp or a halogen lamp, an integrator lens 1102, and a polarization conversion element 1103.

  The dichroic mirror 1104 reflects red light (R) and transmits green light (G) and blue light (B) among the polarized light beams emitted from the polarization illumination device 1100. Another dichroic mirror 1105 reflects the green light (G) transmitted through the dichroic mirror 1104 and transmits the blue light (B).

The red light (R) reflected by the dichroic mirror 1104 is reflected by the reflection mirror 1106 and then enters the liquid crystal light valve 1210 via the relay lens 1205.
Green light (G) reflected by the dichroic mirror 1105 enters the liquid crystal light valve 1220 via the relay lens 1204.
The blue light (B) transmitted through the dichroic mirror 1105 is incident on the liquid crystal light valve 1230 via a light guide system including three relay lenses 1201, 1202, 1203 and two reflection mirrors 1107, 1108.

  The liquid crystal light valves 1210, 1220, and 1230 are disposed to face the incident surfaces of the cross dichroic prism 1206 for each color light. The color light incident on the liquid crystal light valves 1210, 1220, and 1230 is modulated based on video information (video signal) and emitted toward the cross dichroic prism 1206. In this prism, four right-angle prisms are bonded together, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on the inner surface thereof. The three color lights are synthesized by these dielectric multilayer films, and the light representing the color image is synthesized. The synthesized light is projected on the screen 1300 by the projection lens 1207 which is a projection optical system, and the image is enlarged and displayed.

  By applying the liquid crystal device 100 of the first embodiment or the liquid crystal device 200 of the second embodiment to the liquid crystal light valves 1210, 1220, and 1230, a brighter display can be stably provided.

The present invention is not limited to the above-described embodiment, and can be appropriately changed without departing from the spirit or concept of the invention that can be read from the claims and the entire specification. Electronic equipment to which the liquid crystal device 100 is applied is also included in the technical scope of the present invention.
Various modifications other than the above embodiment are conceivable. Hereinafter, a modification will be described.

  (Modification 1) The structure of the transistor having the barrier layer 33 is not limited to being applied to the liquid crystal device 100, and can be applied to, for example, a light emitting device having an organic electroluminescence element. According to this, it is possible to obtain an effect equivalent to that of the first and second embodiments in which the barrier layer 33 suppresses the diffusion of impurities that degrade the characteristics of the transistor. In addition, the prism 110 and the microlens 26 can provide an effect that a brighter display can be provided.

(Modification 2)
In the first embodiment, the prism 110 includes the groove portion 111, the sealing portion 114 that seals the opening portion of the groove portion 111, and the air layer 113 that is sealed in the groove portion 111.
In this modification, after forming a groove portion 111 having a V-shaped cross section by a known technique (dry etching), a silicon oxide film is deposited by plasma CVD using TEOS gas, and planarized by CMP, and has a thickness of 2000 nm. A first dielectric layer 35 of ˜4000 nm is formed. At this time, the opening portion of the groove 111 is sealed by the first dielectric layer 35, and the prism 110 in which the air layer 113 is sealed can be formed. Specifically, the inside of the groove 111 is sealed in a state where the pressure is reduced when the silicon oxide film is deposited. Also according to this modification, the prism 110 having the same performance as that of the first embodiment can be formed.
According to this modification, the step of forming the sealing portion 114 is omitted, and thus the prism 110 can be formed at a lower cost.

(Modification 3)
In the first embodiment, the light emitted from the light source is emitted from the element substrate 10 toward the counter substrate 20. In this modification, the light emitted from the light source is emitted from the counter substrate 20 toward the element substrate 10.
Incident light along the optical axis direction that enters from the counter substrate 20 side passes through the opening region D1, is emitted in the Z (−) direction, and becomes display light. Incident light in an oblique direction with respect to the optical axis incident from the counter substrate 20 side is totally reflected in the Z (−) direction by the inclined surface 112 of the prism 110 and becomes a part of display light. As described above, the incident light in the oblique direction with respect to the optical axis can be used as the display light in addition to the incident light along the optical axis direction by the prism 110. Therefore, the incident light is compared with the case where the prism 110 is not formed. Can be used more efficiently, and a brighter display can be realized.

(Modification 4)
In the periphery of the display area E, in addition to the data line driving circuit 101 and the scanning line driving circuit 104, a sampling circuit that samples an image signal on the image signal line and supplies it to the data line 6a, and a predetermined voltage across the plurality of data lines 6a A precharge circuit that supplies a precharge signal of a level in advance of an image signal, an inspection circuit for inspecting quality, defects, and the like of the electro-optical device during manufacture or at the time of shipment may be formed. These sampling circuit, precharge circuit, and inspection circuit are also composed of a transistor such as a CMOS TFT 202 provided with a barrier layer 33, and impurities (for example, an impurity that degrades the electrical characteristics of the transistor on the surface on the liquid crystal layer 50 side of the substrate body 10a). , Diffusion of fluorine mixed in the first dielectric layer 35 is suppressed, so that deterioration of the electrical characteristics of the transistors in the sampling circuit, the precharge circuit, and the inspection circuit is suppressed.

  (Modification 5) The electronic apparatus to which the liquid crystal device 100 is applied is not limited to the projection display device 1000 of the third embodiment. In addition to the projection display device 1000, a projection type HUD (head-up display), a direct-view type HMD (head-mounted display), an electronic book, a personal computer, a digital still camera, a liquid crystal television, a viewfinder type, or a monitor direct-view type The liquid crystal device 100 according to the first embodiment and the liquid crystal device 200 according to the second embodiment can be applied to information terminal devices such as video recorders, car navigation systems, POS, and electronic devices such as electronic notebooks.

  DESCRIPTION OF SYMBOLS 1a ... Semiconductor layer, 1a '... Channel region, 1b ... Low concentration source region, 1c ... Low concentration source region, 1d ... High concentration source region, 1e ... High concentration drain region, 2 ... Gate insulating film, 3a ... Gate electrode, 3b ... sidewall portion, 6a ... data line, 6a1 ... relay layer for capacitive wiring, 6a2 ... second relay electrode, 8 ... base material, 9a ... pixel electrode, 10 ... element substrate, 10a ... substrate body, 10b ... intermediate layer, DESCRIPTION OF SYMBOLS 10c ... Element layer, 11a ... Scanning line, 12 ... Base insulating layer, 12cv ... Contact hole, 16, 24 ... Orientation film, 19 ... Base material, 20 ... Counter substrate, 20a ... Counter substrate main body, 21, 53 ... Light shielding film 22 ... Dielectric film, 23 ... Counter electrode, 26 ... Microlens, 30 ... TFT, 33 ... Barrier film, 35 ... First dielectric layer, 36 ... Third dielectric layer, 40 ... Insulating layer, 41A ... Aluminum, 41TN ... Nitro Titanium, 41 ... first interlayer insulating film, 42 ... second interlayer insulating film, 43 ... third interlayer insulating film, 44 ... fourth interlayer insulating film, 50 ... liquid crystal layer, 52 ... sealing material, 53 ... light shielding film, 70 Storage capacitor 71 Lower electrode 75 Dielectric layer 75a Silicon oxide 75b Silicon nitride 81, 83, 89, 801, 803, 804, 881, 882 Contact hole 100, 200 Liquid crystal device 101 ... Data line driving circuit, 102 ... External connection terminal, 104 ... Scanning line driving circuit, 105 ... Wiring, 106 ... Vertical conduction part, 110 ... Prism, 111 ... Groove part, 112 ... Inclined surface, 113 ... Air layer, 114... Sealing portion, 202... CMOS type TFT, 202 a... Semiconductor layer, 202 b... Gate electrode film, 202 n... N-type TFT, 202 p. 0 ... wire, 221, 223 ... wiring layer, 300 ... capacitor electrode, 400 ... capacitor wiring, 402 ... third relay electrode, 711 ... wiring layer, 712 ... wiring layer, 719 ... relay electrode.

Claims (9)

A substrate,
A first dielectric layer covering the first surface of the substrate;
A barrier layer covering at least a portion of the first dielectric layer;
A second dielectric layer sandwiching the barrier layer with the first dielectric layer;
A transistor semiconductor layer formed above the second dielectric layer;
With
The region where the barrier layer is disposed overlaps with the channel region of the semiconductor layer when viewed from the normal direction of the first surface, and is the same as or larger than the channel region. apparatus.   The electro-optical device according to claim 1, wherein the constituent material of the barrier layer includes any one of aluminum oxide, polycrystalline silicon, and tungsten silicide.   3. The electro-optical device according to claim 1, wherein the first dielectric layer is silicon oxide formed by plasma CVD using tetraethoxysilane gas. 4. A scan line covering a portion of the second dielectric layer;
A third dielectric layer sandwiching the scan line with the second dielectric layer;
A data line formed above the third dielectric layer;
A pixel electrode formed above the third dielectric layer;
A first transistor connected to the scan line, the data line, and the pixel electrode;
A second transistor connected to the first transistor via either the scan line or the data line;
With
4. The electro-optical device according to claim 1, wherein the transistor includes the first transistor and the second transistor. 5.   The region where the scanning line is arranged overlaps with the channel region of the semiconductor layer of the first transistor when viewed from the normal direction of the first surface of the substrate, and is more than the channel region of the first transistor. The electro-optical device according to claim 4, wherein the electro-optical device is large. An electro-optical device that modulates incident light incident on the transistor side from the substrate side and emits it as display light,
6. The prism according to claim 1, wherein a prism that reflects the modulated incident light and serves as a part of the display light is provided on the first surface of the substrate. 7. Electro-optic device. An electro-optical device that modulates incident light incident on the transistor side from the substrate side and emits it as display light,
The electro-optical device according to claim 1, wherein a microlens that collects the incident light is provided on the first surface of the substrate.   An electronic apparatus comprising the electro-optical device according to claim 1. A first dielectric layer covering a first surface of the substrate, a barrier layer covering at least a part of the first dielectric layer, and a first dielectric layer sandwiching the barrier layer between the first dielectric layer; A method for manufacturing an electro-optical device, comprising: a two-dielectric layer; and a semiconductor layer of a transistor formed above the second dielectric layer,
Depositing silicon oxide by plasma CVD using tetraethoxysilane gas to form the first dielectric layer;
One of aluminum oxide, polycrystalline silicon, and tungsten silicide is deposited, and viewed from the normal direction of the first surface of the substrate, overlaps with the channel region of the semiconductor layer, and is the same as the channel region or the channel region Patterning to be larger than that, and forming the barrier layer;
Depositing silicon oxide by plasma CVD using monosilane gas to form the second dielectric layer;
Forming the semiconductor layer above the second dielectric layer;
A method for manufacturing an electro-optical device.

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