JP6417847B2 - Electro-optical device, method of manufacturing electro-optical device, and electronic apparatus - Google Patents

Description

  The present invention relates to an electro-optical device, a method for manufacturing the electro-optical device, and an electronic apparatus.

  As an electro-optical device, an active drive type liquid crystal device including a transistor that controls switching of a pixel electrode can be given. Since the liquid crystal device is a light receiving type, an illumination device is used to make the display easier to see. On the other hand, it is known that when light emitted from a lighting device is incident on a semiconductor layer (particularly a channel region) constituting a transistor, the semiconductor layer is excited by incident light and a light leakage current flows. Since the electrical characteristics of the transistor change due to the occurrence of light leakage current and a desired switching state cannot be obtained, various light shielding structures for shielding unnecessary light incident on the transistor have been proposed.

  For example, Patent Literature 1 includes a first insulating layer formed on a semiconductor layer of a transistor, and a light-shielding conductive layer that is provided on the first insulating layer and covers at least part of the semiconductor layer, A semiconductor device is disclosed in which the first insulating layer includes a first interlayer insulating layer and a second interlayer insulating layer having different refractive indexes. According to this semiconductor device, light diffracted at the end of the light-shielding conductive layer can be prevented from entering the semiconductor layer. Specifically, at least a part of the diffracted light is reflected at the interface between the first interlayer insulating film and the second interlayer insulating film having different refractive indexes.

  Further, for example, Patent Document 2 includes a light shielding film that is disposed above a transistor and covers at least a semiconductor layer of the transistor, the light shielding film is formed of a highly reflective material, and the side wall of the light shielding film has a set inclination angle. An electro-optical device having an inclined surface is disclosed. According to this electro-optical device, the light incident on the semiconductor layer is reflected by the light shielding film, and the light reflected by the inclined surface is guided to the pixel aperture region, so that the substantial pixel aperture ratio is improved and bright. The display can be realized.

JP 2004-179450 A JP 2008-89683 A

In Patent Document 1, even if a light-blocking conductive layer is provided to block light incident on the semiconductor layer of the transistor, light diffracted at the end of the conductive layer (hereinafter referred to as diffracted light) is the semiconductor layer. It is shown that there is a possibility of being incident on. There is a problem that incident light (illumination light) cannot be efficiently used only by reflecting the diffracted light at the interface between the laminated first interlayer insulating layer and the second interlayer insulating layer.
Further, as in Patent Document 2, in the method of reflecting a part of incident light on the inclined surface of the light shielding film, the light shielding film is formed so as to efficiently guide the reflected light from the inclined surface to the pixel opening region. There is a problem that this is technically difficult.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

  [Application Example] An electro-optical device according to this application example is an electro-optical device having a pixel electrode and a transistor that controls switching of the pixel electrode on a substrate, and is disposed between the substrate and the transistor. The first light-shielding layer, the second light-shielding layer disposed between the transistor and the pixel electrode, the third light-shielding layer disposed between the second light-shielding layer and the pixel electrode, A first interlayer insulating film disposed between the first light shielding layer and the transistor; a second interlayer insulating film disposed between the transistor and the second light shielding layer; the second light shielding layer; A third interlayer insulating film disposed between the third light shielding layer and a fourth interlayer insulating film covering the third light shielding layer and the third interlayer insulating film, wherein the third interlayer insulating film comprises: In one direction in which the pixel electrodes are arranged It has a sidewall sandwiching the second light shielding layer, and satisfies the relationship of n3 <n4, where n3 is the refractive index of the third interlayer insulating film and n4 is the refractive index of the fourth interlayer insulating film. To do.

  According to this application example, since the transistor is disposed between the first light shielding layer and the second light shielding layer on the substrate, at least light incident on the first light shielding layer and the second light shielding layer is shielded, and the transistor It does not enter. On the other hand, since the refractive index n3 of the third interlayer insulating film is smaller than the refractive index n4 of the fourth interlayer insulating film, light incident on the side wall of the third interlayer insulating film from the fourth interlayer insulating film side The light is reflected and guided to the opening area of the pixel where the pixel electrode is disposed. The diffracted light that enters from the fourth interlayer insulating film side and is generated at the end of the third light shielding layer also enters the side wall, and is similarly guided to the opening region side of the pixel. Therefore, it is possible to provide an electro-optical device that can efficiently use incident light while suppressing generation of light leakage current in the transistor.

In the electro-optical device according to the application example, the side wall is provided from the third interlayer insulating film to the first interlayer insulating film, a refractive index of the first interlayer insulating film is n1, and the second When the refractive index of the interlayer insulating film is n2, it is preferable that the relationship of n1 ≦ n2 <n3 <n4 is satisfied.
According to this configuration, since the side wall is provided from the third interlayer insulating film to the vicinity of the substrate, the utilization efficiency of incident light can be further increased.

In the electro-optical device according to the application example, the second interlayer insulating film covers at least the semiconductor layer of the transistor in a plane and has a first side wall sandwiching the semiconductor layer in the one direction. The first side wall is provided from the second interlayer insulating film to the first interlayer insulating film, and the third interlayer insulating film is connected to the second light shielding layer and the first interlayer in the one direction. The second interlayer insulating film is sandwiched between the first and second interlayer insulating films, and the refractive index of the first interlayer insulating film is n1, and the refractive index of the second interlayer insulating film is n2, so that the relationship of n1 ≦ n2 <n3 <n4 is satisfied. It is preferable.
According to this configuration, even if a part of the light incident on the second side wall is refracted to the semiconductor layer side of the transistor, it is incident on the first side wall. Since the refractive index n2 of the second interlayer insulating film provided with the first sidewall is smaller than the refractive index n3 of the third interlayer insulating film provided with the second sidewall, the light incident on the first sidewall is Are reflected and guided to the aperture region of the pixel. That is, it is possible to provide an electro-optical device that can further increase the utilization efficiency of incident light.

In the electro-optical device according to the application example, when the width of the first light shielding layer in the one direction is d1, the width of the second light shielding layer is d2, and the width of the third light shielding layer is d3. , D1 <d2 <d3 is preferably satisfied.
According to this configuration, of the light incident on the substrate from the fourth interlayer insulating film side, the diffracted light generated at the end of the third light shielding layer having the largest width is incident on the side wall and reflected, and the pixel To the open area of Therefore, it is possible to provide an electro-optical device that can use incident light more efficiently while suppressing generation of light leakage current in the transistor.

[Application Example] A method of manufacturing an electro-optical device according to this application example is a method of manufacturing an electro-optical device having a transistor that controls switching of a pixel electrode on a substrate, and a first light shielding layer is formed on the substrate. A step of forming a first interlayer insulating film that covers the first light shielding layer, and a semiconductor layer of the transistor on the first interlayer insulating film and overlapping the first light shielding layer in plan view Forming a second interlayer insulating film covering the semiconductor layer, and forming a second light shielding layer on the second interlayer insulating film and overlapping the first light shielding layer in plan view Forming a third interlayer insulating film covering the second light shielding layer; and
Forming a third light-shielding layer on the third interlayer insulating film and in a portion overlapping the second light-shielding layer in a plane, and at least the third light-shielding layer in a plane of at least the third interlayer insulating film Etching the portion that does not overlap with the substrate, and forming a recess, and filling the recess and forming a fourth interlayer insulating film covering the third light shielding layer, and refraction of the third interlayer insulating film. When the refractive index is n3 and the refractive index of the fourth interlayer insulating film is n4, the third interlayer insulating film and the fourth interlayer insulating film are formed so as to satisfy the relationship of n3 <n4. .

  According to this application example, since the semiconductor layer of the transistor is formed between the first light shielding layer and the second light shielding layer on the substrate, at least the first light shielding layer, the second light shielding layer, and the third light shielding layer are formed. The incident light is blocked and does not enter the semiconductor layer of the transistor. On the other hand, since the third interlayer insulating film and the fourth interlayer insulating film are formed so that the refractive index n3 of the third interlayer insulating film is smaller than the refractive index n4 of the fourth interlayer insulating film, the fourth interlayer insulating film is formed. Light incident on the side wall of the concave portion of the third interlayer insulating film from the film side is reflected by the side wall of the concave portion and guided to the pixel opening region where the pixel electrode is disposed. The diffracted light that enters from the fourth interlayer insulating film side and is generated at the end portion of the third light shielding layer also enters the side wall of the recess, and is similarly guided to the opening region of the pixel. Therefore, it is possible to manufacture an electro-optical device that can efficiently use incident light while suppressing generation of light leakage current in the transistor.

In the method of manufacturing the electro-optical device according to the application example, in the step of forming the recess, the recess is formed by etching the third interlayer insulating film and the second interlayer insulating film, and the first interlayer insulation is performed. The first interlayer insulating film and the second interlayer insulating film are formed so that n1 ≦ n2 <n3 <n4, where n1 is a refractive index of the film and n2 is a refractive index of the second interlayer insulating film. Is preferred.
According to this method, the second interlayer insulating film is formed so that the refractive index n2 of the second interlayer insulating film is smaller than the refractive index n3 of the third interlayer insulating film, and the refractive index n1 of the first interlayer insulating film is the first refractive index n1. The first interlayer insulating film is formed so as to be equal to or smaller than the refractive index n2 of the two interlayer insulating film. Accordingly, by forming a recess from the third interlayer insulating film to the second interlayer insulating film, the area of the sidewall of the recess is increased, and an electro-optical device that can use incident light more efficiently is manufactured. Can do.

In the method of manufacturing the electro-optical device according to the application example, in the step of forming the recess, the recess is formed by etching the third interlayer insulating film, the second interlayer insulating film, and the first interlayer insulating film. When the refractive index of the first interlayer insulating film is n1 and the refractive index of the second interlayer insulating film is n2, the first interlayer insulating film and the second interlayer are such that n1 ≦ n2 <n3 <n4. It is preferable to form an insulating film.
According to this method, a recess having a deeper depth is formed and the area of the side wall of the recess is further increased, and thus an electro-optical device that can use incident light more efficiently can be manufactured.

  [Application Example] A method of manufacturing an electro-optical device according to this application example is a method of manufacturing an electro-optical device having a transistor that controls switching of a pixel electrode on a substrate, and a first light shielding layer is formed on the substrate. A step of forming a first interlayer insulating film that covers the first light shielding layer, and a semiconductor layer of the transistor on the first interlayer insulating film and overlapping the first light shielding layer in plan view Forming a second interlayer insulating film covering the semiconductor layer, and forming a second light shielding layer on the second interlayer insulating film and overlapping the first light shielding layer in plan view Forming a first concave portion extending from the second interlayer insulating film to the first interlayer insulating film by etching a portion of the second interlayer insulating film that does not overlap the second light shielding layer in plan view. And the first recess And a step of forming a third interlayer insulating film covering the second light shielding layer, and a third light shielding layer on the third interlayer insulating film and overlapping the second light shielding layer in plan view. Forming a second concave portion inside the first concave portion by etching a portion of the third interlayer insulating film that does not overlap the third light shielding layer in a plan view, and forming the second concave portion inside the first concave portion; And a step of forming a fourth interlayer insulating film that covers the third light shielding layer and fills the concave portion of the second light shielding layer, wherein the refractive index of the first interlayer insulating film is n1, and the refractive index of the second interlayer insulating film Is n2, the refractive index of the third interlayer insulating film is n3, and the refractive index of the fourth interlayer insulating film is n4, the first interlayer insulating film satisfies the relationship n1 ≦ n2 <n3 <n4. Each of the fourth interlayer insulating films is formed from a film. To.

  According to this application example, even if part of the light incident on the side wall of the second recess is refracted toward the semiconductor layer side of the transistor, the light is incident on the side wall of the first recess. Since the refractive index n2 of the second interlayer insulating film provided with the first concave portion is smaller than the refractive index n3 of the third interlayer insulating film provided with the second concave portion, the light enters the side wall of the first concave portion. The light is reflected and guided to the aperture area of the pixel. That is, it is possible to manufacture an electro-optical device that can further increase the utilization efficiency of incident light.

In the electro-optical device manufacturing method according to the application example described above, in one direction in which the pixel electrodes are arranged, the width of the first light shielding layer is d1, the width of the second light shielding layer is d2, and the third If the width of the light shielding layer is d3, each of the first light shielding layer, the second light shielding layer, and the third light shielding layer is preferably formed so as to satisfy the relationship of d1 <d2 <d3.
According to this method, of the light incident on the substrate from the fourth interlayer insulating film side, the diffracted light generated at the end of the third light shielding layer having the largest width enters the side wall of the second recess. And is led to the aperture region of the pixel. Therefore, it is possible to manufacture an electro-optical device that can use incident light more efficiently while suppressing generation of light leakage current in the transistor.

  [Application Example] An electronic apparatus according to this application example includes the electro-optical device according to the application example described above.

  [Application Example] An electronic apparatus according to this application example includes an electro-optical device manufactured by using the electro-optical device manufacturing method described in the application example.

  According to these application examples, the generation of light leakage current in a transistor is suppressed, a stable driving state is obtained, and an electronic device capable of bright display by efficiently using light incident on a pixel is provided. be able to.

(A) is a schematic plan view which shows the structure of a liquid crystal device, (b) is a schematic sectional drawing in alignment with the H-H 'line | wire of the liquid crystal device shown to (a). FIG. 3 is an equivalent circuit diagram illustrating an electrical configuration of the liquid crystal device. The schematic plan view which shows arrangement | positioning of a pixel. FIG. 2 is a schematic plan view showing the arrangement of thin film transistors, electrodes related to the thin film transistors, and scanning lines in the pixel. FIG. 3 is a schematic plan view showing an arrangement of data lines, storage capacitors and the like in a pixel. FIG. 6 is a schematic cross-sectional view showing the structure of an element substrate taken along line A-A ′ in FIG. 5. FIG. 6 is a schematic cross-sectional view showing a structure of an element substrate taken along line B-B ′ in FIG. 5. (A)-(d) is a schematic sectional drawing which shows the manufacturing method of an element substrate. (E)-(g) is a schematic sectional drawing which shows the manufacturing method of an element substrate. The schematic sectional drawing which shows the structure of the element substrate in the liquid crystal device of 2nd Embodiment. Schematic which shows the structure of a projection type display apparatus. (A) And (b) is a schematic sectional drawing which shows the structure of the element substrate of a modification.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described with reference to the drawings. Note that the drawings to be used are appropriately enlarged or reduced so that the part to be described can be recognized.

  In the present embodiment, an active drive type liquid crystal device including a thin film transistor (hereinafter referred to as TFT) for each pixel will be described as an example of an electro-optical device. This liquid crystal device can be suitably used, for example, as a light modulation element (liquid crystal light valve) of a projection display device (liquid crystal projector) described later.

(First embodiment)
<Electro-optical device>
First, the configuration of a liquid crystal device as an electro-optical device of the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1A is a schematic plan view showing the configuration of the liquid crystal device, and FIG. 1B is a schematic cross-sectional view along the line HH ′ of the liquid crystal device shown in FIG. FIG. 2 is an equivalent circuit diagram showing an electrical configuration of the liquid crystal device.

  As shown in FIGS. 1A and 1B, a liquid crystal device 100 according to the present embodiment includes an element substrate 10 and a counter substrate 20 that are arranged to face each other, and a liquid crystal layer 50 that is sandwiched between the pair of substrates. Have. As the base material 10s of the element substrate 10 and the base material 20s of the counter substrate 20, for example, a quartz substrate or a glass substrate having translucency is used. Note that translucency in this specification refers to a property of transmitting light having a wavelength in the visible light region by at least 85%.

  The element substrate 10 is slightly larger than the counter substrate 20. The element substrate 10 and the counter substrate 20 are bonded together via a sealing material 40 arranged in a frame shape along the outer edge portion of the counter substrate 20, and liquid crystal having positive or negative dielectric anisotropy is enclosed in the gap. Thus, the liquid crystal layer 50 is configured. As the sealing material 40, for example, an adhesive such as a thermosetting or ultraviolet curable epoxy resin is employed. A spacer (not shown) is mixed in the sealing material 40 to keep the distance between the pair of substrates constant.

  Inside the sealing material 40, a display region E in which a plurality of pixels P are arranged in a matrix is provided. The counter substrate 20 is provided with a parting portion 21 that surrounds the display area E between the sealing material 40 and the display area E. The parting portion 21 is made of, for example, a light shielding metal or metal oxide. Note that the display area E may include dummy pixels arranged so as to surround the plurality of pixels P in addition to the plurality of pixels P contributing to display.

  The element substrate 10 is provided with a terminal portion in which a plurality of external connection terminals 104 are arranged. A data line driving circuit 101 is provided between the first side portion along the terminal portion of the element substrate 10 and the sealing material 40. In addition, an inspection circuit 103 is provided between the sealing material 40 and the display area E along the second side facing the first side. Further, a scanning line driving circuit 102 is provided between the seal material 40 and the display region E along the third side and the fourth side that are orthogonal to the first side and face each other. A plurality of wirings 105 that connect the two scanning line driving circuits 102 are provided between the sealing material 40 on the second side and the inspection circuit 103.

  Wirings connected to the data line driving circuit 101 and the scanning line driving circuit 102 are connected to a plurality of external connection terminals 104 arranged along the first side portion. Hereinafter, the direction along the first side is referred to as the X direction, and the direction along the third and fourth sides is referred to as the Y direction. Further, in this specification, viewing from the normal direction of the counter substrate 20 orthogonal to the X direction and the Y direction is referred to as “planar view” or “planar”.

  As shown in FIG. 1B, the element substrate 10 includes a base material 10s, a TFT 30 formed on the surface of the base material 10s on the liquid crystal layer 50 side, the pixel electrode 15, and an alignment film 18 that covers the pixel electrode 15 and the like. have. The TFT 30 and the pixel electrode 15 are components of the pixel P. Details of the pixel P will be described later.

  The counter substrate 20 includes a base material 20s, a parting portion 21, a planarization layer 22, a counter electrode 23, an alignment film 24, and the like, which are sequentially stacked on the surface of the base material 20s on the liquid crystal layer 50 side.

  The parting part 21 surrounds the display area E as shown in FIG. 1A, and is provided at a position overlapping the scanning line driving circuit 102 and the inspection circuit 103 in plan view. Thus, the light incident on the peripheral circuit including these drive circuits from the counter substrate 20 side is blocked, and the peripheral circuit has a role of preventing malfunction due to the light. Further, unnecessary stray light is shielded so as not to enter the display area E, and a high contrast in the display of the display area E is ensured.

  The planarization layer 22 is made of an inorganic material such as silicon oxide, for example, and is provided so as to cover the parting portion 21 with translucency. Such a planarization layer 22 is a silicon oxide film formed by using, for example, a plasma CVD method, and has a thickness that can relax the surface unevenness of the counter electrode 23 formed on the planarization layer 22. Have.

  The counter electrode 23 is made of a transparent conductive film such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), for example, covers the planarization layer 22 and is formed at the four corners of the counter substrate 20 as shown in FIG. The vertical conduction portion 106 provided is electrically connected to the wiring on the element substrate 10 side.

  The alignment film 18 that covers the pixel electrode 15 and the alignment film 24 that covers the counter electrode 23 are set based on the optical design of the liquid crystal device 100, and an oblique deposition film (inorganic alignment film) of an inorganic material such as silicon oxide is used. It has been adopted. The alignment films 18 and 24 may employ an organic alignment film such as polyimide in addition to the inorganic alignment film.

  Such a liquid crystal device 100 is a transmission type, and adopts an optical design of a normally white mode in which the pixel P is brightly displayed when not driven and a normally black mode in which the pixel P is darkly displayed when not driven. Polarizing elements are arranged and used according to the optical design on the light incident side and the light exit side, respectively.

  Next, the electrical configuration of the liquid crystal device 100 will be described with reference to FIG. The liquid crystal device 100 includes a plurality of scanning lines 3 and a plurality of data lines 6 a as signal lines that are insulated and orthogonal to each other at least in the display region E, and a capacitor line 7. In FIG. 2, the capacitor line 7 is shown so as to be parallel to the data line 6a. However, in this embodiment, one capacitor electrode of a pair of capacitor electrodes of the storage capacitor 16 described later is the capacitor line 7. It is comprised so that the function of may be fulfilled.

  A pixel electrode 15, a TFT 30, and a storage capacitor 16 are provided in a region divided by the scanning line 3 and the data line 6a, and these constitute a pixel circuit of the pixel P.

  The scanning line 3 is electrically connected to the gate of the TFT 30, the data line 6 a is electrically connected to the first source / drain region of the TFT 30, and the pixel electrode 15 is electrically connected to the second source / drain region of the TFT 30. Has been.

  The data line 6a is connected to the data line driving circuit 101 (see FIG. 1). Image signals D1, D2,..., Dn are supplied from the data line driving circuit 101 to each pixel P via the data line 6a. The scanning line 3 is connected to the scanning line driving circuit 102 (see FIG. 1). The scanning signals SC1, SC2,..., SCm are supplied to each pixel P from the scanning line driving circuit 102 via the scanning line 3.

  The image signals D1 to Dn supplied from the data line driving circuit 101 may be supplied to the data lines 6a in the order of lines in this order, or may be supplied for each of a plurality of adjacent data lines 6a for each group. Good. The scanning line driving circuit 102 supplies the scanning signals SC <b> 1 to SCm to the scanning line 3 in a pulse-sequential manner at a predetermined timing.

  In the liquid crystal device 100, the TFT 30 that is a switching element is turned on for a certain period by the input of the scanning signals SC1 to SCm, so that the image signals D1 to Dn supplied from the data line 6a are supplied to the pixel electrode 15 at a predetermined timing. It is the structure written in. The predetermined level of image signals D1 to Dn written to the liquid crystal layer 50 via the pixel electrode 15 is held between the pixel electrode 15 and the counter electrode 23 for a certain period.

  In order to prevent the held image signals D1 to Dn from leaking, the holding capacitor 16 is connected in parallel with the liquid crystal capacitor formed between the pixel electrode 15 and the counter electrode 23. The storage capacitor 16 is provided between the second source / drain region of the TFT 30 and the capacitor line 7.

  Note that a data line 6a is connected to the inspection circuit 103 shown in FIG. 1A, and an operation defect or the like of the liquid crystal device 100 is confirmed by detecting the image signal in the manufacturing process of the liquid crystal device 100. Although it can be configured, it is omitted in the equivalent circuit of FIG.

  The inspection circuit 103 includes a sampling circuit that samples the image signal and supplies it to the data line 6a, and a precharge circuit that supplies a precharge signal of a predetermined voltage level to the data line 6a prior to the image signal. Also good.

Next, the configuration of the pixel P in the liquid crystal device 100 will be described with reference to FIG. FIG. 3 is a schematic plan view showing the arrangement of pixels.
As shown in FIG. 3, the pixel P in the liquid crystal device 100 has, for example, a substantially square (substantially square) opening region in a plan view. The opening area is surrounded by a light-shielding non-opening area extending in the X direction and the Y direction and provided in a lattice shape.

  A scanning line 3 shown in FIG. 2 is provided in the non-opening region extending in the X direction. The scanning line 3 uses a light-shielding conductive member, and the scanning line 3 constitutes a part of the non-opening region.

  Similarly, a data line 6a shown in FIG. 2 is provided in the non-opening region extending in the Y direction. The data line 6a also uses a light-shielding conductive member, and these constitute a part of the non-opening region.

  The non-opening region is constituted not only by the signal lines provided on the element substrate 10 side, but also by a light shielding film provided in the same layer as the parting portion 21 and patterned in a lattice pattern on the counter substrate 20 side. Has been.

  The TFT 30 shown in FIG. 2 is provided near the intersection of the non-opening regions. By providing the TFT 30 in the vicinity of the intersection of the non-opening region having a light shielding property, generation of light leakage current of the TFT 30 is suppressed, and the opening ratio in the opening region is secured. Although the detailed structure of the pixel P will be described later, the width of the non-opening region in the vicinity of the intersecting portion is wider than that in other portions due to the provision of the TFT 30 near the intersecting portion.

  A pixel electrode 15 is provided for each pixel P. The pixel electrode 15 is substantially square in plan view, and is provided in the opening region so that the outer edge of the pixel electrode 15 overlaps the non-opening region. Although not shown in FIG. 3, a translucent storage capacitor 16 is disposed in the opening region.

  The liquid crystal device 100 of the present embodiment is a transmissive type, and on the premise that light is incident from the counter substrate 20 side, the light incident on the pixel P is not incident on the TFT 30 on the element substrate 10. A light blocking structure that can reduce the loss of light incident on P and efficiently emit light from the element substrate 10 is adopted. Hereinafter, the light shielding structure of the element substrate 10 will be described.

<Light shielding structure of element substrate>
The light shielding structure in the element substrate 10 will be described with reference to FIGS. FIG. 4 is a schematic plan view showing the arrangement of thin film transistors in the pixel, electrodes and scanning lines related to the thin film transistor, and FIG. 5 is a schematic plan view showing the arrangement of data lines, storage capacitors, etc. in the pixel. 6 is a schematic cross-sectional view showing the structure of the element substrate taken along the line AA ′ of FIG. 5, and FIG. 7 is a schematic cross-sectional view showing the structure of the element substrate taken along the line BB ′ of FIG.

  As shown in FIG. 4, the scanning line 3 is provided for each pixel P, extending in the X direction across the plurality of pixels P, and protrudes from the first part 3 a in the Y direction. It has the 2nd part 3b and the 3rd part 3c. Further, the scanning line 3 has a fourth portion 3d whose width is expanded in the X direction and the Y direction as compared with the first portion 3a and the second portion 3b (third portion 3c). The second part 3b and the third part 3c protruding in the Y direction are arranged so as to overlap with a data line 6a described later in a plane.

  On the scanning line 3, the semiconductor layer 30a of the TFT 30 is disposed in a region extending between the second portion 3b and the third portion 3c with the fourth portion 3d interposed therebetween. The semiconductor layer 30a is made of, for example, high-temperature polysilicon, and has a channel region 30c, a first source / drain region 30s, and a second source / drain region 30d. The first source / drain region 30s is disposed at a position overlapping the third portion 3c of the scanning line 3, and the second source / drain region 30d is disposed at a position overlapping the second portion 3b of the scanning line 3. Yes. A channel region 30c sandwiched between the first source / drain region 30s and the second source / drain region 30d is mainly disposed at a position overlapping the fourth portion 3d of the scanning line 3.

  A contact hole CNT1 for electrical connection with the data line 6a is provided at the end of the first source / drain region 30s. Specifically, the relay layer 5 for providing electrical connection with the data line 6a is provided at a position overlapping the first source / drain region 30s in plan view, and the contact hole CNT1 is connected to the relay layer 5. A contact hole CNT3 is provided between the relay layer 5 and the data line 6a. At the end of the second source / drain region 30d, a contact hole CNT2 for electrical connection with the storage capacitor 16 and the pixel electrode 15 is provided. That is, in the present embodiment, the contact hole CNT1 functions as the source electrode 31 of the TFT 30, and the contact hole CNT2 functions as the drain electrode 32 of the TFT 30.

  A gate electrode 30g is arranged at a position overlapping the channel region 30c of the semiconductor layer 30a. The gate electrode 30g has a portion that overlaps the channel region 30c at a position that overlaps the fourth portion 3d of the scanning line 3, and a portion that faces the channel region 30c in the X direction and extends in the Y direction. ing. In the portion extending in the Y direction, a contact hole 33 and a contact hole 34 reaching the lower scanning line 3 are provided. That is, the gate electrode 30g is electrically connected to the scanning line 3 via the two contact holes 33 and 34 provided with the channel region 30c interposed therebetween.

  The TFT 30 includes the semiconductor layer 30a and the gate electrode 30g described above. A relay layer 4 for electrical connection between the drain electrode 32 of the TFT 30 and the storage capacitor 16 or the pixel electrode 15 is provided at the intersection of the scanning line 3 where the TFT 30 is disposed and the data line 6a. . The relay layer 4 includes a first portion 4a and a fourth portion 4c that protrude in the X direction from the intersecting portion, and a second portion 4b and a third portion 4d that protrude in the Y direction from the intersecting portion. doing.

  The second portion 4b protruding in the Y direction of the relay layer 4 is disposed and electrically connected so as to overlap the contact hole CNT2 functioning as the drain electrode 32. The other third portion 4d protruding in the Y direction of the relay layer 4 is arranged so as not to overlap the relay layer 5 in plan view. As will be described in detail later, the relay layer 4 and the relay layer 5 are provided in the same wiring layer on the base material 10s.

  A contact hole CNT4 for electrical connection with a relay layer 6b (see FIG. 5) described later is provided at a position near the end of the first portion 4a protruding in the X direction of the relay layer 4. . In FIG. 4, the shape of the contact holes CNT1, CNT2, CNT3, and CNT4 is square in plan view, but is not limited to this, and may be circular or elliptical.

  Each of the scanning line 3, the relay layer 4, and the relay layer 5 illustrated in FIG. 4 is one of the elements constituting the non-opening region illustrated in FIG.

  As shown in FIG. 5, the data line 6a is provided so as to extend in the Y direction at a position overlapping the contact hole CNT1 (source electrode 31), CNT2 (drain electrode 32) and the contact hole CNT3 of the TFT 30. An independent relay layer 6b is provided for each pixel P between adjacent data lines 6a in the X direction. The relay layer 6b is substantially rectangular in plan view, and a contact hole CNT4 is provided in the middle of the longitudinal direction extending in the X direction. As described above, the relay layer 6b is electrically connected to the lower relay layer 4 through the contact hole CNT4.

  As will be described in detail later, the data line 6a and the relay layer 6b are provided in the same wiring layer on the base material 10s. On the base material 10s, the lower electrode 16a of the pair of capacitor electrodes of the storage capacitor 16 is provided on the upper layer of the wiring layer provided with the data line 6a and the relay layer 6b so as to straddle the plurality of pixels P. ing. The lower electrode 16a functions as the capacitor line 7 common to the plurality of pixels P. The upper electrode 16b of the pair of capacitor electrodes of the storage capacitor 16 is provided independently for each pixel P between the adjacent data lines 6a. The upper electrode 16b is substantially square in plan view, and the outer edges of the two sides facing each other in the X direction overlap the data line 6a in plan view. In addition, one of the two sides facing the Y direction of the upper electrode 16b overlaps the relay layer 6b in plan view. The lower electrode 16a and the upper electrode 16b are formed using a transparent conductive film such as ITO or IZO, for example.

  In the relay layer 6b, contact holes CNT5 and CNT6 are arranged on both sides in the X direction with the contact hole CNT4 interposed therebetween. The contact hole CNT5 and the contact hole CNT6 are provided through the lower electrode 16a so as not to contact the lower electrode 16a. The contact hole CNT5 is provided at a position where the relay layer 6b and the upper electrode 16b overlap in plan view, and electrically connects the relay layer 6b and the upper electrode 16b. The upper electrode 16b is cut away so as not to contact the contact hole CNT6. The contact hole CNT6 is provided for electrical connection between the relay layer 6b and the pixel electrode 15 (see FIG. 6). The shape of the contact holes CNT5 and CNT6 in plan view is a substantially rectangular shape whose longitudinal direction is along the X direction. The term “substantially rectangular” includes those whose corners are arcuate.

  Each of the data line 6a and the relay layer 6b shown in FIG. 5 is one of the elements constituting the non-opening region shown in FIG.

  Next, a cross-sectional structure in electrical connection between the pixel electrode 15 and the TFT 30 will be described with reference to FIG. As shown in FIG. 6, on the base material 10 s of the element substrate 10, a first layer including the scanning line 3, a second layer including the TFT 30, a third layer including the relay layers 4 and 5, and a data line are sequentially arranged. A fourth layer including 6a and the like, a fifth layer including storage capacitor 16 and the like, and a sixth layer (uppermost layer) including pixel electrode 15 and the like are formed. A first interlayer insulating film 11a is formed between the first layer and the second layer, and a second interlayer insulating film 11c is formed between the second layer and the third layer. A third interlayer insulating film 12 is formed between the third layer and the fourth layer, a fourth interlayer insulating film 13 is formed between the fourth layer and the fifth layer, and the fifth layer and the sixth layer are formed. A fifth interlayer insulating film 14 is formed between the layers. This prevents a short circuit between the aforementioned elements. Further, in these interlayer insulating films, contact holes for electrical connection between the aforementioned elements are formed. Hereinafter, each of these elements will be described in order. FIG. 4 shows a planar arrangement of each element from the first layer to the third layer, and FIG. 5 shows a planar arrangement of each element from the fourth layer to the fifth layer.

  First, in the first layer, for example, a metal simple substance, an alloy, a metal silicide, a polysilicide, or a laminate of these containing at least one of refractory metals such as Ti, Cr, Mo, Ta, W, etc. Alternatively, the scanning line 3 made of conductive polysilicon or the like is formed. In particular, the scanning line 3 is preferably formed using metal silicide from the viewpoint of shielding the return light incident from the base material 10s side and not reflecting the incident light incident from the counter substrate 20 side. In the embodiment, the scanning line 3 is formed using WSi (tungsten silicide). The film thickness of the scanning line 3 is about 200 nm, for example.

Next, a first interlayer insulating film 11a that covers the scanning lines 3 is formed. The first interlayer insulating film 11a is formed using, for example, silicon oxide. The film thickness of the first interlayer insulating film 11a is, for example, about 400 nm.
Subsequently, a semiconductor layer 30a is formed on the first interlayer insulating film 11a as a second layer. The semiconductor layer 30a is made of, for example, polysilicon, and impurity ions are selectively implanted, and the LDD including the first source / drain region 30s, the junction region 30e, the channel region 30c, the junction region 30f, and the second source / drain region 30d. (Lightly Doped Drain) structure is built. The film thickness of the semiconductor layer 30a is approximately 40 nm, for example.

  Next, a gate insulating film 11b covering the semiconductor layer 30a is formed. The gate insulating film 11b is formed using, for example, silicon oxide. The film thickness of the gate insulating film 11b is about 50 nm, for example.

  Next, a groove-shaped through hole is formed in the first interlayer insulating film 11a and the gate insulating film 11b. A gate electrode 30g and a pair of contact holes 33 and 34 are formed by forming and patterning a conductive film so as to fill the through hole. In FIG. 6, the contact hole 34 of the pair of contact holes 33 and 34 is illustrated, and the contact hole 33 is not illustrated. Thereby, a part of the semiconductor layer 30a of the TFT 30 is covered with the contact holes 33 and 34 from the side in a plan view as shown in FIG. 4, and at least from the pair of contact holes 33 and 34 side. Incident light is blocked. The contact holes 33 and 34 are formed so that the lower ends thereof are in contact with the scanning lines 3. Accordingly, the gate electrode 30g and the scanning line 3 existing in a certain row (X direction) are always at the same potential as long as the row is focused.

An example of the conductive film used for the gate electrode 30g is a conductive polysilicon film. The film thickness of the gate electrode 30g is about 100 nm, for example.
Then, a second interlayer insulating film 11c that covers the gate electrode 30g and the gate insulating film 11b is formed. The second interlayer insulating film 11c is formed using, for example, silicon oxide and has a thickness of about 300 nm, for example.

  A through hole is formed in the gate insulating film 11b and the second interlayer insulating film 11c at a position overlapping the first source / drain region 30s and the second source / drain region 30d of the semiconductor layer 30a, and fills the inside of the through hole. As described above, the relay layer 5, the contact hole CNT1, the relay layer 4, and the contact hole CNT2 are formed by forming and patterning a conductive film on the second interlayer insulating film 11c. The relay layer 4 as the third layer is formed so as to overlap the gate electrode 30g in plan view (see FIG. 4). Examples of the conductive film used for the relay layer 4 and the relay layer 5 as the third layer include metals such as Al (aluminum) and Ti (titanium), which are low resistance wiring materials, and metal compounds thereof. In the present embodiment, the relay layers 4 and 5 have a three-layer structure of TiN (titanium nitride) / Al (aluminum) / TiN (titanium nitride).

  Next, a third interlayer insulating film 12 covering the relay layers 4 and 5 is formed. The third interlayer insulating film 12 is formed using, for example, silicon oxynitride and has a film thickness of about 400 nm, for example. A through hole penetrating the third interlayer insulating film 12 is formed at a position overlapping the relay layer 5 of the third interlayer insulating film 12. In addition, a through-hole penetrating the third interlayer insulating film 12 is formed at a position overlapping the first portion 4 a in the relay layer 4 of the third interlayer insulating film 12. A conductive film is formed on the third interlayer insulating film 12 and patterned so as to fill the inside of these through holes, whereby the data line 6a and the relay layer 6b as the fourth layer, the contact hole CNT3 and the contact are formed. Hole CNT4 is formed. As the conductive film used for the fourth layer, the same metal or metal compound as that for the third layer can be used. In the present embodiment, the fourth layer has a two-layer structure of Al (aluminum) / TiN (titanium nitride).

  Next, a fourth interlayer insulating film 13 is formed to cover the data line 6a and the relay layer 6b as the fourth layer. The fourth interlayer insulating film 13 is formed using, for example, silicon oxynitride. The film thickness of the fourth interlayer insulating film 13 is about 400 nm, for example. Since the fourth interlayer insulating film 13 has irregularities on the surface after film formation due to the lower wiring structure, for example, a planarization process such as a CMP (Chemical Mechanical Polishing) process is performed.

  Next, the storage capacitor 16 that is the fifth layer is formed on the fourth interlayer insulating film 13 that has been subjected to the planarization process. Specifically, first, the lower electrode 16a of the storage capacitor 16 is formed by forming a transparent conductive film such as ITO or IZO on the fourth interlayer insulating film 13 and patterning it. The film thickness of the lower electrode 16a is about 140 nm, for example. As shown in FIG. 5, the lower electrode 16 a is formed over at least the display region E as a common capacitance line 7 in the plurality of pixels P. The lower electrode 16a is a contact hole CNT5 for electrical connection between the upper electrode 16b of the storage capacitor 16 and the relay layer 6b, and a contact hole CNT6 for electrical connection between the pixel electrode 15 and the relay layer 6b. In order to avoid contact with the contact holes CNT, patterning is performed so as to have openings in portions overlapping the contact holes CNT5 and CNT6.

Next, a dielectric layer 16c that covers the lower electrode 16a is formed. The dielectric layer 16c is composed of a plurality of layers formed using dielectric materials having different dielectric constants. The film thickness of the dielectric layer 16c is approximately 30 nm, for example. Examples of the dielectric material include hafnium oxide, aluminum oxide, a silicon oxide film, a silicon nitride film, and tantalum oxide (Ta ₂ O ₅ ). By combining these layers having different dielectric constants, a larger electric capacity can be realized while ensuring translucency.

  Next, a through-hole penetrating the fourth interlayer insulating film 13 and the dielectric layer 16c is formed at a position overlapping the relay layer 6b in plan view. The upper electrode 16b of the storage capacitor 16 and the contact hole CNT5 are formed by patterning a transparent conductive film such as ITO or IZO that covers the dielectric layer 16c so as to cover the inside of the through hole. It is formed. The film thickness of the upper electrode 16b is approximately 140 nm, for example.

  Next, a fifth interlayer insulating film 14 covering the upper electrode 16b and the contact hole CNT5 is formed. The fifth interlayer insulating film 14 includes a first insulating film 14a and a second insulating film 14b stacked on the first insulating film 14a. More specifically, first, an NSG (Non doped Silicate Glass) film that covers the upper electrode 16b and the contact hole CNT5 is formed by, for example, a plasma CVD method. Then, for the purpose of alleviating the unevenness of the surface of the NSG film generated by covering the contact holes CNT5 and the like, a planarization process such as a CMP process is performed. The thickness of the NSG film after the planarization process, that is, the first insulating film 14a is, for example, about 400 nm. And the 2nd insulating film 14b which covers the 1st insulating film 14a is formed. The second insulating film 14b is formed using a material different from that of the first insulating film 14a so as to be thinner than the first insulating film 14a. The second insulating film 14b is, for example, a BSG (Boron doped Silicate Glass) film, and is formed by using, for example, a plasma CVD method. The film thickness of the second insulating film 14b is approximately 75 nm, for example. Therefore, the film thickness of the fifth interlayer insulating film 14 including the first insulating film 14a and the second insulating film 14b is approximately 475 nm.

  Next, a through-hole penetrating the fourth interlayer insulating film 13, the dielectric layer 16c, and the fifth interlayer insulating film 14 is formed at a position overlapping the relay layer 6b in plan view. The pixel electrode 15 and the contact hole CNT6 are formed by forming and patterning a transparent conductive film such as ITO covering the fifth interlayer insulating film 14 so as to cover the inside of the through hole. As shown in FIG. 3, the pixel electrode 15 is formed so as to overlap with the storage capacitor 16 in the opening region of the pixel P, and to overlap the outer edge portion of the pixel electrode 15 with the non-opening region. In the present embodiment, light incident from the counter substrate 20 side is transmitted through the counter substrate 20 and the liquid crystal layer 50, and is transmitted through the pixel electrode 15 and the storage capacitor 16 disposed in the opening region of the pixel P. It is injected from the side. In the present embodiment, the film thickness of each of the pixel electrode 15, the lower electrode 16a, and the upper electrode 16b made of a transparent conductive film is about 140 nm. Accordingly, the optical attenuation of the incident light by passing through the pixel electrode 15 and the storage capacitor 16 is suppressed. Further, by setting the film thickness of the pixel electrode 15 to approximately 140 nm, the coverage of the contact hole CNT6 deeper than the contact hole CNT5 is improved, and the electrical connection between the pixel electrode 15 and the relay layer 6b is stabilized. Yes.

  In the present embodiment, the base material 10 s corresponds to the “substrate” of the present invention, and the scanning line 3 having a light shielding property corresponds to the “first light shielding layer” of the present invention. Further, the relay layers 4 and 5 having the same light shielding property correspond to the “second light shielding layer” of the present invention, and the data line 6a and the relay layer 6b correspond to the “third light shielding layer” of the present invention. . Therefore, by using the reference numerals of the main configuration of the wiring layer, hereinafter, they will be referred to as the first light shielding layer 3, the second light shielding layer 4, and the third light shielding layer 6a for the sake of explanation.

  As shown in FIG. 7, the first light shielding layer 3, the semiconductor layer 30a, the second light shielding layer 4, the third light shielding layer 6a, the storage capacitor 16, and the pixel electrode 15 are arranged in this order on the base material 10s. . In the present embodiment, when the width of the first light shielding layer 3 in the X direction is d1, the width of the second light shielding layer 4 is d2, and the width of the third light shielding layer 6a is d3, in the present embodiment, the relationship of d1 <d2 <d3 is satisfied. Each of the first light shielding layer 3, the second light shielding layer 4, and the third light shielding layer 6a is formed so as to satisfy the above. The X direction in the present embodiment corresponds to “one direction in which pixel electrodes are arranged” in the present invention. The width of the semiconductor layer 30a in the X direction is smaller than the width d1 of the first light shielding layer 3.

  On the base material 10s, a side wall 12a is formed from the third interlayer insulating film 12 positioned below the third light shielding layer 6a to the first interlayer insulating film 11a. The side wall 12a is formed so as to sandwich the first light shielding layer 3, the semiconductor layer 30a, and the second light shielding layer 4 in the X direction. In other words, a recess (trench) including the side wall 12a is formed in the opening region of the pixel P where the pixel electrode 15 is disposed. The fourth interlayer insulating film 13 covering the third light shielding layer 6a is formed so as to fill the recess (trench). The concave portion (trench) is formed by dry etching the third interlayer insulating film 12, the second interlayer insulating film 11c, and the first interlayer insulating film 11a. Depending on the etching method, the sidewall 12a and the third light shielding layer 6a are formed. There is a slight overhang between them. Therefore, on the base material 10s, the side wall 12a is provided so as to sandwich the first light shielding layer 3 and the second light shielding layer 4, and the cross section of the side wall 12a has a trapezoidal shape having a forward tapered slope.

  In the present embodiment, the refractive index of the first interlayer insulating film 11a is n1, the refractive index of the second interlayer insulating film 11c is n2, the refractive index of the third interlayer insulating film 12 is n3, and the fourth interlayer insulating film 13 is used. Assuming that the refractive index of n4 is n4, each of the first interlayer insulating film 11a to the fourth interlayer insulating film 13 is formed so as to satisfy the relationship of n1 ≦ n2 <n3 <n4.

  From the relationship between the refractive indexes of the respective interlayer insulating films, as shown in FIG. 7, the light L1 incident on the pixel electrode 15 from the normal direction is the fifth interlayer insulating film 14, the storage capacitor 16, the fourth The light passes through the interlayer insulating film 13 and is emitted from the base material 10s. Light L2 that is incident obliquely on the pixel electrode 15 and is incident between the third light shielding layers 6a adjacent in the X direction has the fourth interlayer insulating film 13, the third interlayer insulating film 12, and the second The light enters the side wall 12a that is a boundary between the second interlayer insulating film 11c and the first interlayer insulating film 11a. The light L2 incident on the side wall 12a inclined in the forward taper is reflected, guided to the opening region of the pixel P, and emitted from the base material 10s.

  Further, the diffracted light generated at the end of the third light shielding layer 6a having the largest width d3 in the X direction also enters the side wall 12a. Therefore, the diffracted light is also reflected by the side wall 12a and guided to the opening region of the pixel P, so that the diffracted light does not enter the second light shielding layer 4 or the semiconductor layer 30a. Of course, the light L4 incident on the third light shielding layer 6a having the largest width d3 is shielded by the third light shielding layer 6a and does not enter the second light shielding layer 4 or the semiconductor layer 30a.

  In the liquid crystal device 100, a part of the light incident from the counter substrate 20 side is shielded by the non-opening region as shown in FIG. As described above, the non-opening region in the element substrate 10 includes the first light shielding layer 3, the second light shielding layer 4, and the third light shielding layer 6a. Most of the light incident on the opening region surrounded by the non-opening region in the element substrate 10 is emitted from the base material 10s. On the other hand, when there is no side wall 12a formed from the third interlayer insulating film 12 to the first interlayer insulating film 11a, the diffracted light generated at the end of the third light shielding layer 6a located on the light incident side is the third light shielding. Light is lost because the light is shielded by the light shielding layer located below the layer 6a or absorbed by the interlayer insulating film. In the present embodiment, such a light loss can be reduced or substantially eliminated by providing the side wall 12a extending from directly under the third light shielding layer 6a to the base material 10s.

  The light incident on the opening region of the element substrate 10 includes not only the light L1 incident substantially parallel to the optical axis but also the light L2 incident at an angle with respect to the optical axis. Therefore, diffracted light can also be generated at the end of the second light shielding layer 4 below the third light shielding layer 6a having the largest width d3. The diffracted light generated at the end of the second light shielding layer 4 may enter the semiconductor layer 30a and may cause a light leakage current in the TFT 30. According to the present embodiment, the generation of diffracted light that causes such a light leakage current can also be suppressed by the side wall 12a.

  A detailed method for forming each light shielding layer, each interlayer insulating film, and the recess (side wall 12a) will be described in the method for manufacturing the element substrate 10.

<Method of manufacturing electro-optical device>
Next, as a method for manufacturing the electro-optical device according to this embodiment, a method for manufacturing the element substrate 10 of the liquid crystal device 100 will be described with reference to FIGS. 7, 8, and 9. FIGS. 8A to 8D and FIGS. 9E to 9G are schematic sectional views showing a method for manufacturing an element substrate. Specifically, it is a schematic cross-sectional view corresponding to FIG.

  The manufacturing method of the element substrate 10 in this embodiment includes a first light shielding layer forming step (step S1), a first interlayer insulating film forming step (step S2), a semiconductor layer forming step (step S3), and a second interlayer insulating film forming. Step (Step S4), Second light shielding layer forming step (Step S5), Third interlayer insulating film forming step (Step S6), Third light shielding layer forming step (Step S7), Recessed portion forming step (Step S8), Fourth This includes an interlayer insulating film forming step (step S9), a storage capacitor forming step (step S10), a fifth interlayer insulating film forming step (step S11), and a pixel electrode forming step (step S12).

  In step S1, as shown in FIG. 7, the first light shielding layer 3 is formed on the base material 10s. As described above, the first light shielding layer 3 functions as a scanning line, and shields the return light incident from the base material 10s side and does not reflect the incident light incident from the counter substrate 20 side. It is preferable to use metal silicide having both light shielding properties and low reflectivity. In this embodiment, it is formed using WSi (tungsten silicide), and is patterned using a photolithography method so as to have a scanning line function. The film thickness of the first light shielding layer 3 is, for example, approximately 200 nm.

In step S2, as shown in FIG. 7, the first interlayer insulating film 11a covering the first light shielding layer 3 is formed. Examples of the method for forming the first interlayer insulating film 11a include a method of forming a silicon oxide film by a plasma CVD method using water (H ₂ O) and TEOS (Tetra_ethoxy_silane). The film thickness of the first interlayer insulating film 11a is, for example, about 450 nm. Thus, the refractive index n1 of the first interlayer insulating film 11a containing silicon oxide as a main component has a value of 1.46 to 1.48. The first interlayer insulating film 11a is preferably formed so as to have substantially the same refractive index as that of the base material 10s so that light is not easily reflected at the interface with the base material 10s.

  In step S3, as shown in FIG. 7, the semiconductor layer 30a is formed on the first interlayer insulating film 11a overlapping the first light shielding layer 3 in plan. As described above, the semiconductor layer 30a is made of, for example, high-temperature polysilicon, and an LDD structure is formed by controlling the implantation of impurity ions. Thereafter, a gate insulating film 11b made of silicon oxide is formed so as to cover the semiconductor layer 30a. The gate insulating film 11b is thinner than the first interlayer insulating film 11a, and the gate insulating film 11b only needs to cover at least the semiconductor layer 30a, and is not necessarily formed over the entire surface of the base material 10s. Description is omitted.

In step S4, as shown in FIG. 7, a second interlayer insulating film 11c is formed to cover the first interlayer insulating film 11a on which the semiconductor layer 30a is formed. As a method of forming the second interlayer insulating film 11c, a method of forming a silicon oxide film by a plasma CVD method using, for example, water (H ₂ O) and TEOS similarly to the first interlayer insulating film 11a. The film thickness of the second interlayer insulating film 11c is about 300 nm, for example. As described above, the refractive index n2 of the second interlayer insulating film 11c containing silicon oxide as a main component is 1.46 to 1.48, which is the same as the refractive index n1 of the first interlayer insulating film 11a.

  In step S5, as shown in FIG. 7, the second light shielding layer 4 is formed on the second interlayer insulating film 11c overlapping the first light shielding layer 3 and the semiconductor layer 30a in plan view. As described above, the second light shielding layer 4 functions as a relay layer and has a three-layer structure of TiN (titanium nitride) / Al (aluminum) / TiN (titanium nitride), for example. Such a three-layer structure is formed by, for example, laminating each layer by sputtering, followed by patterning using photolithography. The thickness of the second light shielding layer 4 is, for example, about 50 nm for the lower TiN layer, about 350 nm for the middle Al layer, and about 150 nm for the upper TiN layer. That is, the film thickness of the second light shielding layer 4 is approximately 550 nm.

In step S6, as shown in FIG. 7, the third interlayer insulating film 12 is formed to cover the second interlayer insulating film 11c on which the second light shielding layer 4 is formed. As a method for forming the third interlayer insulating film 12, for example, a silicon oxynitride film (SiO _x N _y ) is formed by a plasma CVD method using monosilane gas (SiH ₄ ) and dinitrogen monoxide gas (N ₂ O). The method of doing is mentioned. By adjusting the flow rate of such a source gas, the refractive index n3 of the formed silicon oxynitride film (SiO _x N _y ), that is, the third interlayer insulating film 12 can be set to 1.50 to 1.54. it can.

  In step S7, as shown in FIG. 7, the third light shielding layer 6a is formed on the third interlayer insulating film 12 overlapping the second light shielding layer 4 in plan view. As described above, the third light shielding layer 6a functions as the data line 6a and has a two-layer structure of, for example, Al (aluminum) / TiN (titanium nitride). Such a two-layer structure is formed, for example, by layering each layer by sputtering and then patterning using photolithography. The film thickness of the third light shielding layer 6a is, for example, about 350 nm for the lower Al layer and about 150 nm for the upper TiN layer. That is, the film thickness of the third light shielding layer 6a is approximately 500 nm.

  In step S8, a portion of the third interlayer insulating film 12 that does not overlap the third light shielding layer 6a in plan is etched to form a recess. Specifically, a photosensitive resist layer covering the third interlayer insulating film 12 on which the third light shielding layer 6a is formed is formed, and this is exposed and developed, so that at least the first resist layer as shown in FIG. 3 A resist pattern 70 patterned so as to overlap with the light shielding layer 6a is formed. The planar shape of the resist pattern 70 is the shape of a non-opening region surrounding the opening region for each pixel P shown in FIG. Then, the third interlayer insulating film 12 not covered with the resist pattern 70 is subjected to dry etching using, for example, a fluorine-based processing gas. Dry etching is performed up to the first interlayer insulating film 11a on the substrate 10s. As a result, as shown in FIG. 8B, the third interlayer insulating film 12 to the first interlayer insulating film 11a are etched between the adjacent third light shielding layers 6a to form a recess (trench) including the side wall 12a. ) 12t is formed. A recess (trench) 12t is formed for each pixel P.

In step S9, a fourth interlayer insulating film 13 that fills the recess (trench) 12t and covers the third light shielding layer 6a and the third interlayer insulating film 12 is formed. Specifically, first, for example, monosilane gas (SiH ₄ ), dinitrogen monoxide gas (N ₂ O), and ammonia gas (NH ₃ ) are used for the base material 10 s in which the recess (trench) 12 t is formed. A method of depositing silicon oxynitride (SiO _x N _y ) by the conventional plasma CVD method can be given. By adjusting the flow rate of such a source gas, the refractive index of the silicon oxynitride film (SiO _x N _y ) 13a formed by increasing the nitrogen atom content over the third interlayer insulating film 12 is set to 1. 55 to 1.60. The film thickness of the silicon oxynitride film 13a is, for example, 3 μm. As shown in FIG. 8C, the surface of the silicon oxynitride film 13a is uneven by filling a recess 12t and covering the third light shielding layer 6a. In order to alleviate the unevenness, the silicon oxynitride film 13a is subjected to a planarization process such as CMP process. As a result, as shown in FIG. 8D, a fourth interlayer insulating film 13 having a flat surface is completed. The film thickness of the thickest portion of the fourth interlayer insulating film 13 is approximately 2 μm. The refractive index n4 of the fourth interlayer insulating film 13 is 1.55 to 1.60 as described above.

  In step S10, the storage capacitor 16 is formed on the fourth interlayer insulating film 13 as shown in FIG. As described above, the lower electrode 16a is formed by forming a transparent conductive film such as ITO over at least the display region E so as to function as the capacitor line 7 extending over the plurality of pixels P. A dielectric layer 16c is formed so as to cover the lower electrode 16a. Furthermore, an independent upper electrode 16b is formed for each pixel P by forming and patterning a transparent conductive film such as ITO, covering the dielectric layer 16c. Thereby, a storage capacitor 16 is formed for each pixel P. The film thickness of the lower electrode 16a and the upper electrode 16b is, for example, approximately 140 nm, and the film thickness of the dielectric layer 16c is, for example, 30 nm.

  In step S11, as shown in FIG. 9F, a fifth interlayer insulating film 14 that covers the storage capacitor 16 is formed. As described above, the fifth interlayer insulating film 14 includes the first insulating film 14a made of the NSG film formed by the plasma CVD method and the second insulating film 14b made of the BSG film also formed by the plasma CVD method. Consists of.

  In step S12, as shown in FIG. 9G, the pixel electrode 15 is formed on the fifth interlayer insulating film. Specifically, a transparent conductive film such as ITO is formed so as to cover the fifth interlayer insulating film 14, and this is patterned to form an independent pixel electrode 15 for each pixel P. The film thickness of the pixel electrode 15 is 140 nm, for example. Thereby, the element substrate 10 is completed. The completed element substrate 10 is subjected to an alignment process based on the optical design of the liquid crystal device 100.

  In the method of manufacturing the element substrate 10, the first interlayer insulating film 11a, the second interlayer insulating film 11c, and the third interlayer insulating film are formed so that the refractive index of each interlayer insulating film satisfies the relationship of n1 ≦ n2 <n3 <n4. A film 12 and a fourth interlayer insulating film 13 are formed. In addition, the first light shielding layer 3, the second light shielding layer 4, and the third light shielding layer 6a are arranged so that the width of each light shielding layer in at least the X direction in which the pixel electrodes 15 are arranged satisfies the relationship d1 <d2 <d3. Each is formed.

  In order to efficiently guide the light incident on the side wall 12a to the opening region of the pixel P, it is preferable that the inclination angle of the side wall 12a with respect to the surface of the base material 10s is as close to 90 degrees as possible. In the recess forming step (step S8) described above, the dry etching conditions (for example, the flow rate of the processing gas and the etching time) were set so that the inclination angle of the side wall 12a was 87 degrees to 89 degrees.

  Note that the angle of light incident on the side wall 12a is the angle distribution of light incident on the counter substrate 20 (for example, in the projection display device 1000 described later, light emitted from the polarization illumination device 1100 is collected with respect to the liquid crystal light valve. Depends on the F number of the optical system to be illuminated. Therefore, the inclination angle of the side wall 12a is not necessarily an angle close to 90 degrees, and may be an angle of 70 degrees to less than 90 degrees that can be formed by dry etching.

According to the first embodiment, the following effects can be obtained.
(1) On the base material 10 s of the element substrate 10 in the liquid crystal device 100, the semiconductor layer 30 a of the TFT 30 is a first interlayer between the first light shielding layer (scanning line) 3 and the second light shielding layer (relay layer) 4. Arranged on the insulating film 11a. Further, by performing dry etching on the third interlayer insulating film 12 that is not covered with the third light shielding layer (data line) 6a that overlaps the second light shielding layer (relay layer) 4 in plan view, the third interlayer insulating film 12 is obtained. A recess (trench) 12t having a side wall 12a is formed on the first interlayer insulating film 11a. The refractive index n3 (1.50 to 1.54) of the third interlayer insulating film 12 with respect to the refractive index n4 (1.55 to 1.60) of the fourth interlayer insulating film 13 filling the recess 12t. The refractive index n2 (1.46 to 1.48) of the second interlayer insulating film 11c and the refractive index n1 (1.46 to 1.48) of the first interlayer insulating film 11a are in a relationship of n1 ≦ n2 <n3 <n4. Therefore, the light incident on the side wall 12a serving as the interface with the fourth interlayer insulating film 13 is reflected by the side wall 12a and guided to the opening region of the pixel P. In addition, the diffracted light generated at the end of the third light-shielding layer 6a is also incident on the side wall 12a, reflected, and guided to the opening region of the pixel P. Further, since the diffracted light generated at the end of the third light shielding layer 6a is difficult to go to the second light shielding layer 4 as the lower layer, the light diffracted at the end of the second light shielding layer 4 and incident on the semiconductor layer 30a The generation of light leakage current of the TFT 30 is further suppressed. That is, according to the element substrate 10 and the manufacturing method thereof of the present embodiment, the occurrence of light leakage current of the TFT 30 is further suppressed, so that a stable switching operation of the pixel P is realized and the incident light is incident from the counter substrate 20 side. It is possible to provide or manufacture the liquid crystal device 100 that can improve the light use efficiency by reducing the loss of light and obtain a bright display quality.
(2) In the arrangement direction of the pixel electrodes 15, the width d1 of the first light shielding layer 3, the width d2 of the second light shielding layer 4, and the width d3 of the third light shielding layer 6a satisfy the relationship d1 <d2 <d3. The 1st light shielding layer 3, the 2nd light shielding layer 4, and the 3rd light shielding layer 6a are formed. Therefore, the light incident from the fourth interlayer insulating film 13 side is difficult to reach by the second light shielding layer 4 and the first light shielding layer 3 located below the third light shielding layer 6a, and thus is generated at the end of the light shielding layer. Generation of light leakage current of the TFT 30 due to diffracted light can be further suppressed.

(Second Embodiment)
Next, an element substrate in the liquid crystal device of the second embodiment will be described with reference to FIG. FIG. 10 is a schematic cross-sectional view showing the structure of the element substrate in the liquid crystal device of the second embodiment. FIG. 10 corresponds to FIG. 7 which is a schematic cross-sectional view showing the structure of the element substrate 10 in the liquid crystal device 100 of the first embodiment.
In the liquid crystal device of the second embodiment, the structure of the element substrate 10 in the liquid crystal device 100 of the first embodiment is different. Therefore, the same components as those of the liquid crystal device 100 are denoted by the same reference numerals and detailed description thereof is omitted.

  As shown in FIG. 10, the element substrate 10B of the present embodiment includes a first light shielding layer 3, a first interlayer insulating film 11a, a semiconductor layer 30a, and a second interlayer insulating film 11c, which are arranged in order on the base material 10s. , The second light shielding layer 4, the third interlayer insulating film 12, the third light shielding layer 6a, the fourth interlayer insulating film 13, the storage capacitor 16, the fifth interlayer insulating film 14, and the pixel electrode 15.

  The first interlayer insulating film 11a and the second interlayer insulating film 11c, which are lower layers of the second light shielding layer 4, have a first interlayer that sandwiches the first light shielding layer 3 and the semiconductor layer 30a in at least the X direction in which the pixel electrodes 15 are arranged. A side wall 11d is provided. That is, the 1st recessed part (trench) which has the 1st side wall 11d between the adjacent 2nd light shielding layers 4 is formed.

  The third interlayer insulating film 12, which is the lower layer of the third light shielding layer 6 a, is provided with a second side wall 12 b that sandwiches the first side wall 11 d and the second light shielding layer 4. That is, a second recess (trench) having the second side wall 12b is formed inside the first recess (trench) between the adjacent third light shielding layers 6a. The fourth interlayer insulating film 13 is formed to fill the second concave portion (trench) and cover the third light shielding layer 6a.

  As described in the first embodiment, the first interlayer insulating film 11a, the second interlayer insulating film 11c, the third interlayer insulating film 11c, the third interlayer insulating film 11c, the third interlayer insulating film 11c, the third interlayer insulating film 11c, and the third interlayer insulating film 11c. An interlayer insulating film 12 and a fourth interlayer insulating film 13 are formed. In addition, the first light shielding layer 3, the second light shielding layer 4, and the third light shielding layer 6a are arranged so that the width of each light shielding layer in at least the X direction in which the pixel electrodes 15 are arranged satisfies the relationship d1 <d2 <d3. Each is formed.

  For example, the first recess (trench) may be formed by performing dry etching on the first interlayer insulating film 11a and the second interlayer insulating film 11c formed by stacking from the second interlayer insulating film 11c side. The method of giving is mentioned. The second recess (trench) may be formed by dry etching the third interlayer insulating film 12 formed by filling the first recess (trench).

  The inclination angle of the first side wall 11d with respect to the surface of the substrate 10s is preferably larger than the inclination angle of the second side wall 12b and closer to 90 degrees. Since the depth of the first recess is shallower than the depth of the second recess, the inclination angle of the first side wall 11d can easily approach 90 degrees by dry etching.

  According to the second embodiment, the light L3 incident and refracted by the second side wall 12b at an incident angle that cannot be reflected by the second side wall 12b is reflected by the first side wall 11d, and the opening region of the pixel P is reflected. Can lead to. Therefore, generation of light leakage current in the TFT 30 is suppressed, and light incident from the counter substrate 20 side (fourth interlayer insulating film 13 side) can be used more efficiently than in the first embodiment. That is, it is possible to provide or manufacture a liquid crystal device capable of obtaining a stable driving state and capable of displaying brighter.

(Third embodiment)
<Electronic equipment>
Next, a projection display device as an electronic apparatus to which the liquid crystal device 100 as an electro-optical device according to this embodiment is applied will be described with reference to FIG. FIG. 11 is a schematic diagram showing the configuration of the projection display device.

  As shown in FIG. 11, a projection display apparatus 1000 as an electronic apparatus according to the present embodiment includes a polarization illumination apparatus 1100 arranged along the system optical axis L, and two dichroic mirrors 1104 and 1105 as light separation elements. And. In addition, three reflection mirrors 1106, 1107, 1108 and five relay lenses 1201, 1202, 1203, 1204, 1205 are provided. Further, it includes transmissive liquid crystal light valves 1210, 1220, and 1230 as three light modulation means, a cross dichroic prism 1206 as a light combining element, and a projection lens 1207.

  The polarized light illumination device 1100 is generally configured by a lamp unit 1101 as a light source composed of a white light source such as an ultra-high pressure mercury lamp or a halogen lamp, an integrator lens 1102, and a polarization conversion element 1103.

  The dichroic mirror 1104 reflects red light (R) and transmits green light (G) and blue light (B) among the polarized light beams emitted from the polarization illumination device 1100. Another dichroic mirror 1105 reflects the green light (G) transmitted through the dichroic mirror 1104 and transmits the blue light (B).

The red light (R) reflected by the dichroic mirror 1104 is reflected by the reflection mirror 1106 and then enters the liquid crystal light valve 1210 via the relay lens 1205.
Green light (G) reflected by the dichroic mirror 1105 enters the liquid crystal light valve 1220 via the relay lens 1204.
The blue light (B) transmitted through the dichroic mirror 1105 enters the liquid crystal light valve 1230 via a light guide system including three relay lenses 1201, 1202, 1203 and two reflection mirrors 1107, 1108.

  The liquid crystal light valves 1210, 1220, and 1230 are disposed to face the incident surfaces of the cross dichroic prism 1206 for each color light. The color light incident on the liquid crystal light valves 1210, 1220, and 1230 is modulated based on video information (video signal) and emitted toward the cross dichroic prism 1206. In this prism, four right-angle prisms are bonded together, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on the inner surface thereof. The three color lights are synthesized by these dielectric multilayer films, and the light representing the color image is synthesized. The synthesized light is projected onto the screen 1300 by the projection lens 1207, which is a projection optical system, and the image is enlarged and displayed.

  The liquid crystal light valve 1210 is the one to which the liquid crystal device 100 (see FIG. 1) of the first embodiment is applied. A pair of polarizing elements arranged in crossed Nicols are arranged with a gap between the colored light incident side and the emitting side of the liquid crystal device 100. The same applies to the other liquid crystal light valves 1220 and 1230.

  According to such a projection display apparatus 1000, since the liquid crystal device 100 of the first embodiment is used as the liquid crystal light valves 1210, 1220, and 1230, generation of light leakage current in the TFT 30 is suppressed and stable. Drive state is obtained. In addition, light incident on the pixel P is efficiently used, and a bright display is possible. That is, it is possible to provide a projection display apparatus 1000 that realizes a stable driving state and has excellent display quality. The same effect can be obtained even when the liquid crystal device having the element substrate 10B of the second embodiment is adopted as the liquid crystal light valves 1210, 1220, and 1230.

  The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit or idea of the invention that can be read from the claims and the entire specification. The manufacturing method of the electro-optical device and the electronic apparatus to which the electro-optical device is applied are also included in the technical scope of the present invention. Various modifications other than the above embodiment are conceivable. Hereinafter, a modification will be described.

(Modification 1) In the element substrate 10 of the first embodiment, the side wall 12a between the adjacent third light shielding layers 6a is formed so as to extend from the third interlayer insulating film 12 to the surface of the base material 10s. It is not limited to. 12 (a) and 12 (b) are schematic cross-sectional views showing the structure of a modified element substrate. In addition, the same code | symbol is attached | subjected to the same structure as the said 1st Embodiment, and detailed description is abbreviate | omitted.
For example, as shown in FIG. 12A, the element substrate 10C according to the modification is formed between the adjacent third light shielding layers 6a so as to extend from the third interlayer insulating film 12 to the first interlayer insulating film 11a. It has a side wall 12c. A part 11e of the first interlayer insulating film 11a remains on the surface of the base material 10s. As described in the first embodiment, in the recess forming step (step S8), the third interlayer insulating film 12 is dry etched to form a recess. However, the dry etching is not performed until the surface reaches the surface of the substrate 10s. Also good. The film thickness of each interlayer insulating film may vary. Accordingly, all the pixels P or partial pixels P in the display area E after dry etching may have a light shielding structure as shown in FIG.
Further, as shown in FIG. 12B, the element substrate 10D according to the modification is formed between the adjacent third light shielding layers 6a so as to extend from the third interlayer insulating film 12 to the second interlayer insulating film 11c. It has a side wall 12d. A portion 11f of the first interlayer insulating film 11a and the second interlayer insulating film 11c remains on the surface of the base material 10s. According to this, since the amount of the interlayer insulating film to be removed by dry etching is reduced, after the recess forming step (step S8), the inclination angle is closer to 90 degrees, and an overhang is formed between the third light shielding layer 6a. The side wall 12d that is difficult to occur can be formed. In other words, if the side wall that reflects incident light is formed at least in the third interlayer insulating film 12 below the third light shielding layer 6a, the utilization efficiency of incident light can be improved. In this case, n3 <n4 The third interlayer insulating film 12 and the fourth interlayer insulating film 13 may be formed so as to satisfy the relationship.

  (Modification 2) The configuration of the element substrate 10 in the liquid crystal device 100 of the first embodiment is not limited to this. For example, in the first embodiment, the semiconductor layer 30a of the TFT 30 is arranged in the extending direction (Y direction) of the data line 6a, but may be arranged in the extending direction of the scanning line 3. Further, although the translucent storage capacitor 16 is arranged in the opening region of the pixel P, the holding capacitor 16 may be arranged in the non-opening region.

  (Modification 3) The electronic apparatus to which the liquid crystal device 100 of the first embodiment is applied is not limited to the projection display device 1000 of the third embodiment. For example, the counter substrate 20 of the liquid crystal device 100 may include color filters corresponding to at least red (R), green (G), and blue (B), and the projection display device may have a single plate configuration. Also, for example, a projection type HUD (head-up display), HMD (head-mounted display), electronic book, personal computer, digital still camera, liquid crystal television, viewfinder type or monitor direct view type video recorder, car navigation system, The liquid crystal device 100 can be suitably used as a display unit of an information terminal device such as an electronic notebook or POS.

  DESCRIPTION OF SYMBOLS 3 ... Scan line (1st light shielding layer), 4 ... Relay layer (2nd light shielding layer), 6a ... Data line (3rd light shielding layer), 10 ... Element substrate, 10s ... Base material as a board | substrate, 11a ... 1st Interlayer insulating film, 11c ... second interlayer insulating film, 11d ... first sidewall, 12 ... third interlayer insulating film, 12a ... sidewall, 12b ... second sidewall, 12t ... concave (trench), 13 ... fourth interlayer Insulating film, 15... Pixel electrode, 100... Liquid crystal device as electro-optical device, 1000... Projection display device as electronic device.

Claims (11)

An electro-optical device having a pixel electrode and a transistor that controls switching of the pixel electrode on a substrate,
A first light-shielding layer disposed between the substrate and the transistor;
A second light-shielding layer disposed between the transistor and the pixel electrode;
A third light-shielding layer disposed between the second light-shielding layer and the pixel electrode;
A first interlayer insulating film disposed between the first light shielding layer and the transistor;
A second interlayer insulating film disposed between the transistor and the second light shielding layer;
A third interlayer insulating film disposed between the second light shielding layer and the third light shielding layer;
A fourth interlayer insulating film covering the third light shielding layer and the third interlayer insulating film,
The third interlayer insulating film has a clamping-free side walls said second light-shielding layer in one direction in which the pixel electrode is arranged,
When the refractive index of the third interlayer insulating film is n3 and the refractive index of the fourth interlayer insulating film is n4,
An electro-optical device satisfying a relationship of n3 <n4. The side wall is provided from the third interlayer insulating film to the first interlayer insulating film,
When the refractive index of the first interlayer insulating film is n1, and the refractive index of the second interlayer insulating film is n2,
The electro-optical device according to claim 1, wherein a relationship of n1 ≦ n2 <n3 <n4 is satisfied. The second interlayer insulating film planarly covers at least the semiconductor layer of the transistor and has a first side wall sandwiching the semiconductor layer in the one direction,
The first side wall is provided from the second interlayer insulating film to the first interlayer insulating film,
The third interlayer insulating film has a second side wall sandwiching the second light shielding layer and the first side wall in the one direction,
When the refractive index of the first interlayer insulating film is n1, and the refractive index of the second interlayer insulating film is n2,
The electro-optical device according to claim 1, wherein a relationship of n1 ≦ n2 <n3 <n4 is satisfied. In the one direction, when the width of the first light shielding layer is d1, the width of the second light shielding layer is d2, and the width of the third light shielding layer is d3,
The electro-optical device according to claim 1, wherein a relationship of d1 <d2 <d3 is satisfied. A method of manufacturing an electro-optical device having a transistor that controls switching of a pixel electrode on a substrate,
Forming a first light shielding layer on the substrate;
Forming a first interlayer insulating film covering the first light shielding layer;
Forming a semiconductor layer of the transistor on the first interlayer insulating film and in a portion overlapping the first light shielding layer in a plane;
Forming a second interlayer insulating film covering the semiconductor layer;
Forming a second light-shielding layer on the second interlayer insulating film in a portion overlapping the first light-shielding layer in a plane;
Forming a third interlayer insulating film covering the second light shielding layer;
Forming a third light-shielding layer on the third interlayer insulating film and in a portion overlapping the second light-shielding layer in a plane;
Etching at least a portion of the third interlayer insulating film that does not overlap the third light shielding layer in a plane to form a recess;
Forming a fourth interlayer insulating film that fills the recess and covers the third light shielding layer,
When the refractive index of the third interlayer insulating film is n3 and the refractive index of the fourth interlayer insulating film is n4, the third interlayer insulating film and the fourth interlayer insulating film satisfy the relationship of n3 <n4. Forming an electro-optical device. In the step of forming the recess, the third interlayer insulating film and the second interlayer insulating film are etched to form the recess, and the refractive index of the first interlayer insulating film is set to n1, and the second interlayer insulating film If the refractive index of n is n2,
6. The method of manufacturing an electro-optical device according to claim 5, wherein the first interlayer insulating film and the second interlayer insulating film are formed so that n1 ≦ n2 <n3 <n4. In the step of forming the recess, the recess is formed by etching the third interlayer insulating film, the second interlayer insulating film, and the first interlayer insulating film, and the refractive index of the first interlayer insulating film is n1; When the refractive index of the second interlayer insulating film is n2,
6. The method of manufacturing an electro-optical device according to claim 5, wherein the first interlayer insulating film and the second interlayer insulating film are formed so that n1 ≦ n2 <n3 <n4. A method of manufacturing an electro-optical device having a transistor that controls switching of a pixel electrode on a substrate,
Forming a first light shielding layer on the substrate;
Forming a first interlayer insulating film covering the first light shielding layer;
Forming a semiconductor layer of the transistor on the first interlayer insulating film and in a portion overlapping the first light shielding layer in a plane;
Forming a second interlayer insulating film covering the semiconductor layer;
Forming a second light-shielding layer on the second interlayer insulating film in a portion overlapping the first light-shielding layer in a plane;
Etching a portion of the second interlayer insulating film that does not overlap the second light-shielding layer in plan to form a first recess extending from the second interlayer insulating film to the first interlayer insulating film;
Forming a third interlayer insulating film filling the first recess and covering the second light shielding layer;
Forming a third light-shielding layer on the third interlayer insulating film and in a portion overlapping the second light-shielding layer in a plane;
Etching a portion of the third interlayer insulating film that does not overlap the third light shielding layer in a plan view to form a second recess inside the first recess;
Forming a fourth interlayer insulating film filling the second recess and covering the third light shielding layer,
The refractive index of the first interlayer insulating film is n1, the refractive index of the second interlayer insulating film is n2, the refractive index of the third interlayer insulating film is n3, and the refractive index of the fourth interlayer insulating film is n4. Then,
Each of the fourth interlayer insulating films is formed from the first interlayer insulating film so as to satisfy the relationship of n1 ≦ n2 <n3 <n4. In one direction in which the pixel electrodes are arranged, if the width of the first light shielding layer is d1, the width of the second light shielding layer is d2, and the width of the third light shielding layer is d3,
The first light-shielding layer, the second light-shielding layer, and the third light-shielding layer are formed so as to satisfy a relationship of d1 <d2 <d3, according to any one of claims 5 to 8. A method of manufacturing the electro-optical device according to claim.   An electronic apparatus comprising the electro-optical device according to claim 1.   An electronic apparatus comprising the electro-optical device manufactured using the method for manufacturing an electro-optical device according to claim 5.

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