JP2016081317A - Structure analysis method, structure analysis device and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce irregularity on a mount surface of a substrate including a plurality of wiring layers.SOLUTION: A computer 1 divides each of wiring layers 4a-4c into regions (finite elements) 5 of the first size, and on the basis of design data 6a of a multilayer wiring board 4, allocates material information showing material included in each of a plurality of finite elements 5 to each of the plurality of finite elements 5. The computer 1 divides the multilayer wiring board 4 into a plurality of regions A-C by surfaces 4e and 4f perpendicular to a mount surface 4d and calculates, among the plurality of finite elements 5, on the basis of the material information allocated to elements (e.g. finite elements 5a-5i in the region B) included in each of the regions A-C, a percentage content of conductive material in each of the regions A-C. The computer 1 then replaces the conductive material in the regions A-C with non-conductive material so that the percentage content falls within the first range by, for example, replacing the material information allocated to the finite elements 5a-5i.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a structure analysis method, a structure analysis apparatus, and a program.

  When an electronic component is mounted on a substrate including a plurality of wiring layers (hereinafter referred to as a multilayer wiring substrate), the multilayer wiring substrate may be warped due to a thermal load in a soldering process. The warpage generated in the multilayer wiring board causes non-attachment or short-circuiting at a bump joint portion or the like of an electronic component mounted on the multilayer wiring board, thereby reducing the product yield.

  In view of this, a method is known in which CAD (Computer Aided Design) and a finite element method are combined to preliminarily analyze warpage generated in a multilayer wiring board during a soldering process by computer simulation. By this prior prediction, the design can be changed to a multilayer wiring board with less warpage occurring in the mounting process.

JP 2004-13437 A JP 2006-209629 A JP 2000-277927 A

  By the way, if the content of conductive material such as wiring located below the mounting surface of the multilayer wiring board varies depending on the location, irregularities may occur on the mounting surface of the multilayer wiring board during the soldering process. Even with unevenness that has less influence on the shape of the board compared to the warp that occurs in the multilayer wiring board, since the density of electronic components mounted on the multilayer wiring board has been increasing in recent years, mounting defects (for example, Electrical connection failure or short circuit of electronic components, etc.).

  Therefore, it is a problem to reduce the unevenness of the mounting surface of the multilayer wiring board.

  According to one aspect of the invention, there is provided a structural analysis method for analyzing a structure of a substrate including a plurality of wiring layers by computer simulation, wherein the computer converts each of the plurality of wiring layers to a plurality of first sizes. Dividing into first regions, and assigning material information indicating materials contained in each of the plurality of first regions to each of the plurality of first regions based on the design data of the substrate, , And is divided into a plurality of second regions on a surface perpendicular to the mounting surface of the substrate, and is assigned to a third region included in each of the plurality of second regions among the plurality of first regions. The first content rate of the conductive material in each of the plurality of second regions is obtained based on the material information, and the first content rate is in the first range in each of the plurality of second regions. Fits in To, by rewriting the material information assigned to the third area, performing replacement of the conductive material and the non-conductive material of said plurality of second regions, structural analysis method is provided.

  According to another aspect of the invention, there is provided a structural analysis apparatus that analyzes a structure of a substrate including a plurality of wiring layers by computer simulation, the processor including a processor, wherein the processor includes each of the plurality of wiring layers, Material information indicating materials contained in each of the plurality of first regions is divided into a plurality of first regions having a first size and based on the design data of the substrate. And the board is divided into a plurality of second areas on a plane perpendicular to the mounting surface of the board, and included in each of the plurality of second areas among the plurality of first areas. The first content rate of the conductive material in each of the plurality of second regions is obtained based on the material information assigned to the third region, and the first content rate is determined in each of the plurality of second regions. Including A structure that replaces the conductive material and the non-conductive material in the plurality of second regions by rewriting the material information assigned to the third region so that the rate falls within the first range. An analysis device is provided.

  According to another aspect of the invention, there is provided a program for causing a computer to execute a process of analyzing a structure of a substrate including a plurality of wiring layers by computer simulation, wherein the plurality of wiring layers are included in the substrate including the plurality of wiring layers. Are divided into a plurality of first regions of a first size, and based on the design data of the substrate, material information indicating materials included in each of the plurality of first regions is Assigning to each of the first regions, dividing the substrate into a plurality of second regions on a plane perpendicular to the mounting surface of the substrate, and among the plurality of first regions, the plurality of second regions The first content rate of the conductive material in each of the plurality of second regions is obtained based on the material information assigned to the third region included in each of the plurality of second regions, and each of the plurality of second regions is obtained. In this case, the material information assigned to the third region is rewritten so that the first content rate falls within the first range, whereby the conductive material and the non-conductive material in the plurality of second regions are rewritten. There is provided a program for causing the computer to execute a process for performing replacement.

  According to the disclosed structure analysis method, structure analysis apparatus, and program, unevenness on the mounting surface of a substrate including a plurality of wiring layers can be reduced.

It is a figure which shows an example of the structure-analysis method of the multilayer wiring board of 1st Embodiment. It is a figure which shows an example of the hardware of the computer used for this Embodiment. It is a perspective view which shows an example of the multilayer wiring board used as structural analysis object. It is a flowchart explaining the flow of an example of the structural analysis method of the multilayer wiring board of 2nd Embodiment. It is a perspective view which shows an example of the division | segmentation into a finite element in a wiring layer. It is a perspective view which shows an example of the setting of the mesh in a wiring layer. It is a perspective view which shows an example which divides | segments a multilayer wiring board into a several area | region. It is a perspective view which shows an example of the finite element made into the rewriting object of material information. It is a figure which shows an example of the multilayer wiring board before rewriting of material information. It is a figure which shows an example of the multilayer wiring board after rewriting of material information. It is a perspective view which shows the mode of an example at the time of manufacture of the multilayer wiring board designed based on the analysis result of the structure analysis method of 2nd Embodiment. It is sectional drawing which shows the example of formation of the multilayer wiring board designed based on the analysis result of the structure analysis method of 2nd Embodiment. It is a perspective view which shows the mode of an example at the time of manufacture of the multilayer wiring board at the time of not replacing with the material of a copper material, and the material of a non-copper material. It is sectional drawing which shows the example of formation of a multilayer wiring board at the time of not replacing with the material of a copper material, and the material of a non-copper material. It is a top view of the semiconductor device which shows the other example of area division. It is sectional drawing of the semiconductor device which shows the other example of area | region division. It is sectional drawing of the semiconductor device after rewriting of material information.

Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings.
(First embodiment)
The structure analysis method of the present embodiment analyzes the structure of a substrate (hereinafter referred to as a multilayer wiring substrate) including a plurality of wiring layers by computer simulation.

FIG. 1 is a diagram illustrating an example of a structure analysis method for a multilayer wiring board according to the first embodiment.
The structure analysis method for the multilayer wiring board is executed by the structure analysis apparatus 1.
The structural analysis apparatus 1 is a computer, for example, and includes a processor 2 and a storage unit 3. The processor 2 executes the following structure analysis method based on data and programs stored in the storage unit 3.

The storage unit 3 stores programs executed by the processor 2 and various data. For example, the storage unit 3 stores design data 6a and material property information 6b of the multilayer wiring board.
The design data 6a is CAD (Computer Aided Design) data indicating the wiring pattern of the multilayer wiring board and the shape of the multilayer wiring board.

The material physical property information 6b is data including physical property values of materials included in the multilayer wiring board. The physical property value of the material is, for example, the elastic modulus, thermal expansion coefficient, density, etc. of the material.
First, the processor 2 reads the design data 6a from the storage unit 3, and divides each of the plurality of wiring layers into a certain size area (hereinafter referred to as a finite element) in the multilayer wiring board (step S1). The finite element is, for example, a small cube having a size that allows the material of each finite element to be specified.

In the example of FIG. 1, an example is shown in which the wiring layers 4 a, 4 b, 4 c of the three-layer multilayer wiring board 4 are divided into finite elements 5.
Next, the processor 2 assigns material information indicating materials included in each of the plurality of finite elements to each finite element based on the design data 6a (step S2). The material information is information including material names such as copper and prepreg. As will be described later, the processor 2 specifies the material from the position of each finite element in the multilayer wiring board by using the coordinates corresponding to the position of each finite element from the design data of the multilayer wiring board, for example, and converts it into the finite element. Material information can be assigned. For example, if the position of the finite element on the multilayer wiring board is on the wiring, the material included in the finite element can be specified as a conductive material (for example, a copper material).

  When one finite element includes a conductive material and a non-conductive material, for example, the processor 2 may specify the material to be allocated according to the ratio of each material included in the finite element. .

Thereafter, the processor 2 divides the multilayer wiring board into a plurality of regions on a plane perpendicular to the mounting surface of the multilayer wiring board (step S3).
FIG. 1 shows an example in which the multilayer wiring board 4 is divided into three regions A, B, and C by planes 4e and 4f perpendicular to the mounting surface 4d. The area may be divided into two or four or more instead of three.

  After the process of step S3, the processor 2 calculates the content ratio of the conductive material in each region based on the material information assigned to the finite element included in each divided region among the plurality of finite elements ( Step S4).

  In the example of FIG. 1, each of the areas A to C has 9 × N finite elements, and the content of the conductive material in each of the areas A to C is determined from the material information assigned to these finite elements. Calculated.

  After that, the processor 2 rewrites the material information assigned to the finite element in each region so that the content of the conductive material is within a predetermined range in each region, so that the non-conductive material in the plurality of regions Replacement with a conductive material is performed (step S5).

  In the example of FIG. 1, the content ratios of the conductive materials in the regions A to C are A0, A1, and A2, respectively, and A0 and A2 are within a predetermined range (T1 <A0 <T2, T1 <A2 <T2). , A1 is assumed to be outside a predetermined range (A1 <T1). The predetermined range is set, for example, as a range of 40% to 50% or the like according to the allowable range of unevenness in the surface direction.

  When the content rate of the conductive material in the region B is out of the predetermined range as described above, the processor 2 rewrites the material information assigned to the finite element in the region B, so that the conductive material in the plurality of regions is rewritten. And non-conductive materials are replaced. In order to simplify the description, attention is paid to nine finite elements in the first column of the region B in FIG. For example, the region B has finite elements 5a, 5b, 5c, 5d, 5e, 5f, 5g, 5h, and 5i. Of these, the material information assigned to the finite elements 5b, 5d, and 5h that are shaded indicates that these finite elements 5b, 5d, and 5h are conductive materials. The material information assigned to the other finite elements 5a, 5c, 5e-5g, 5i indicates that these finite elements 5a, 5c, 5e-5g, 5i are non-conductive materials.

  In the above example, the content ratio of the conductive material in the region B is A1 <T1, which is lower than the predetermined range. Therefore, the processor 2 assigns the finite element 5f included in the region B as illustrated in FIG. The material information is rewritten to indicate the conductive material. That is, the processor 2 replaces the material corresponding to the finite element 5f from the nonconductive material to the conductive material. This increases the content of the conductive material in the region B. When the content rate (A3) of the region B after replacement is within the above range (T1 <A3 <2), the process of step S5 ends.

  Thereafter, the processor 2 reads the material property information 6b from the storage unit 3 and executes the structural analysis of the multilayer wiring board (step S6). For example, the processor 2 calculates the density, elastic modulus, thermal expansion coefficient, and the like of the conductive material and the non-conductive material in each region from the physical property values of the material indicated by the material information assigned to the finite element in each region. The unevenness generated in the surface direction of the multilayer wiring board is analyzed.

  The processor 2 assigns the material physical property information 6b to each finite element during the process of step S2, and the finite element in which the conductive material and the non-conductive material are replaced in the process of step S5 is the material. The physical property information 6b may be reassigned.

  A multilayer wiring board is designed based on the above structural analysis result. When the conductive material and the non-conductive material are replaced in a certain finite element by the processing in step S5, for example, the arrangement position of the wiring is changed based on the position of the finite element. In addition, for example, a dummy pattern may be provided in a portion corresponding to the finite element in which the non-conductive material is replaced with the conductive material so that the ratio of the conductive material is increased.

  As described above, in the structural analysis method and the structural analysis apparatus of the present embodiment, during the structural analysis of the multilayer wiring board, the multilayer wiring board is divided into a plurality of regions on a surface perpendicular to the mounting surface, and the conductive material in each region is contained. The conductive material and the non-conductive material are replaced so that the rate falls within a predetermined range. Thereby, the variation in the content rate of the conductive material between the regions is reduced, and the unevenness in the surface direction of the multilayer wiring board is reduced. Since the unevenness of the mounting surface is reduced, the occurrence of mounting defects (for example, electrical connection defects such as electronic components or short circuits) is suppressed.

(Second Embodiment)
Hereinafter, an example of a structural analysis method for realizing a multilayer wiring board with higher quality will be described in consideration of not only the reduction of unevenness in the surface direction of the multilayer wiring board but also suppression of warpage.

The structure analysis method for a multilayer wiring board according to the second embodiment is executed by a computer as shown below, for example.
FIG. 2 is a diagram illustrating an example of computer hardware used in this embodiment.

  The entire computer 20 is controlled by a processor 21. The processor 21 is connected to a RAM (Random Access Memory) 22 and a plurality of peripheral devices via a bus 29. The processor 21 may be a multiprocessor. The processor 21 is, for example, a central processing unit (CPU), a micro processing unit (MPU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), or a programmable logic device (PLD). The processor 21 may be a combination of two or more elements among CPU, MPU, DSP, ASIC, and PLD.

  The RAM 22 is used as a main storage device of the computer 20. The RAM 22 temporarily stores at least part of an OS (Operating System) program and application programs to be executed by the processor 21. The RAM 22 stores various data necessary for processing by the processor 21.

  Peripheral devices connected to the bus 29 include an HDD (Hard Disk Drive) 23, a graphic processing device 24, an input interface 25, an optical drive device 26, a device connection interface 27, and a network interface 28.

  The HDD 23 magnetically writes and reads data to and from the built-in disk. The HDD 23 is used as an auxiliary storage device of the computer 20. The HDD 23 stores an OS program, application programs, and various data. As the auxiliary storage device, a semiconductor storage device such as a flash memory can be used.

  A monitor 24 a is connected to the graphic processing device 24. The graphic processing device 24 displays an image on the screen of the monitor 24a in accordance with an instruction from the processor 21. Examples of the monitor 24a include a display device using a CRT (Cathode Ray Tube) and a liquid crystal display device.

  A keyboard 25 a and a mouse 25 b are connected to the input interface 25. The input interface 25 transmits a signal sent from the keyboard 25a and the mouse 25b to the processor 21. The mouse 25b is an example of a pointing device, and other pointing devices can also be used. Examples of other pointing devices include a touch panel, a tablet, a touch pad, and a trackball.

  The optical drive device 26 reads data recorded on the optical disc 26a using a laser beam or the like. The optical disk 26a is a portable recording medium on which data is recorded so that it can be read by reflection of light. The optical disk 26a includes a DVD (Digital Versatile Disc), a DVD-RAM, a CD-ROM (Compact Disc Read Only Memory), a CD-R (Recordable) / RW (Rewritable), and the like.

  The device connection interface 27 is a communication interface for connecting peripheral devices to the computer 20. For example, the device connection interface 27 can be connected to a memory device 27a and a memory reader / writer 27b. The memory device 27 a is a recording medium equipped with a communication function with the device connection interface 27. The memory reader / writer 27b is a device that writes data to the memory card 27c or reads data from the memory card 27c. The memory card 27c is a card-type recording medium.

  The network interface 28 is connected to the network 28a. The network interface 28 transmits / receives data to / from other computers or communication devices via the network 28a.

  With the hardware configuration described above, the processing functions of the second embodiment can be realized. The structural analysis apparatus 1 shown in the first embodiment can also be realized by the same hardware as the computer 20 shown in FIG.

  The computer 20 implements the processing functions of the second embodiment by executing a program recorded on a computer-readable recording medium, for example. A program describing the processing contents to be executed by the computer 20 can be recorded in various recording media. For example, a program to be executed by the computer 20 can be stored in the HDD 23. The processor 21 loads at least a part of the program in the HDD 23 into the RAM 22 and executes the program. A program to be executed by the computer 20 can also be recorded on a portable recording medium such as the optical disk 26a, the memory device 27a, and the memory card 27c. The program stored in the portable recording medium becomes executable after being installed in the HDD 23 under the control of the processor 21, for example. The processor 21 can also read and execute the program directly from the portable recording medium.

Next, a multilayer wiring board to be subjected to structural analysis of the second embodiment will be described.
(Example of multilayer wiring board)
FIG. 3 is a perspective view showing an example of a multilayer wiring board to be subjected to structural analysis. In FIG. 3, the wiring and the like are not shown.

  A multilayer wiring board 10 to be subjected to structural analysis has wiring layers 11, 12, and 13. The wiring layers 11 to 13 are formed of a wiring or an insulating layer. In the example of FIG. 3, the upper surface of the wiring layer 11 is the mounting surface 10a. The wiring layers are not limited to three, and may be two or four or more.

(Example of structural analysis method)
FIG. 4 is a flowchart for explaining the flow of an example of the structure analysis method for a multilayer wiring board according to the second embodiment.

The following processing is performed under the control of the processor 21 based on the design data 6c and the material property information 6d in the computer 20 shown in FIG.
The design data 6c is CAD data indicating the wiring pattern of the multilayer wiring board 10 and the shape of the multilayer wiring board 10 shown in FIG.

  The material physical property information 6 d is data including physical property values of materials included in the multilayer wiring board 10. The physical property value of the material is, for example, the elastic modulus, thermal expansion coefficient, density, etc. of the material. The design data 6c and the material property information 6d are stored in advance in the HDD 23, for example.

  First, the processor 21 performs the processes of steps S10 and S11. These processes are the same as the processes in steps S1 and S2 shown in FIG. For example, the processor 21 reads the design data 6 c from the HDD 23 and divides each of the plurality of wiring layers 11 to 13 into a plurality of finite elements in the multilayer wiring board 10.

FIG. 5 is a perspective view showing an example of division into finite elements in the wiring layer.
In the example shown in FIG. 5, the wiring layers 11 to 13 are each divided into 7 × 9 finite elements. Further, as the finite element, for example, a cube can be used like the finite element 14 shown in FIG. Further, when the processor 21 divides into finite elements, it corresponds to the position of the finite element from the design data 6c of the multilayer wiring board 10 as information indicating the position of the finite element for the processing in step S11 described later. You may make it acquire the coordinate to do.

In the process of step S11, the processor 21 assigns material information indicating the material included in each of the plurality of finite elements to each finite element based on the design data 6c.
Through the processing in step S11 described above, the material information is assigned to the finite element, whereby it is specified whether the material included in the finite element is a conductive material or a non-conductive material. In the following description, the conductive material is assumed to be a copper material.

  Next, the processor 2 sets a plurality of regions (hereinafter referred to as meshes) larger than the size of the finite element in each of the wiring layers of the multilayer wiring board 10 (step S12). The processor 2 sets the mesh by combining a plurality of finite elements into one unit. Further, the number and size of the meshes are set in consideration of, for example, calculation time, calculation load, and the like at the time of structural analysis by processing in step S20 described later.

FIG. 6 is a perspective view showing an example of setting of the mesh in the wiring layer.
In the example illustrated in FIG. 6, four meshes are set for each of the wiring layers 11 to 13. For example, the mesh 15 is set by combining 3 × 4 finite elements 14a into one unit.

  After the processing in step S12, the processor 21 uses the material information assigned to the finite element included in each mesh to determine the content ratio of the conductive material in each mesh (hereinafter, using copper material as an example, and determining the copper content ratio). (Referred to as the remaining copper ratio) (step S13).

The remaining copper ratio is obtained, for example, by calculating a ratio of finite elements whose assigned material information indicates a copper material among the finite elements included in each mesh.
Next, the processor 21 determines whether or not the remaining copper ratio in each mesh is within a predetermined range (step S14). This range is set in advance based on the allowable range of variation in the remaining copper ratio allowed between the meshes in order to suppress warping of the multilayer wiring board 10. When the allowable range of variation in the remaining copper ratio is wide, the set range is also set wide. When the allowable range is narrow, the set range is also set narrow.

Note that different ranges may be set for each of the wiring layers 11 to 13. This is because the wiring density may be greatly different for each of the wiring layers 11 to 13.
When there is a mesh whose remaining copper ratio does not fall within the above range, the processor 21 executes the process of step S15, and the remaining copper ratio is included in the above range for all the meshes of each wiring layer. Performs the process of step S16.

  In the process of step S15, the processor 21 rewrites the material information assigned to the finite element included in the mesh whose remaining copper ratio is not within the above range, and the copper material and the non-conductive material (non-conductive material) Replacement with a copper material (for example, prepreg) is performed. Thereafter, the processor 21 repeats the processing from step S13.

  For example, when the remaining copper ratio in a certain mesh is lower than a predetermined range, the processor 21 rewrites the material information assigned to some finite elements included in the mesh, and the non-copper material From what shows, it shall show the material of a copper material. Thereby, the remaining copper rate in the mesh calculated by the process of step S13 increases.

  On the other hand, for example, when the remaining copper ratio in a mesh exceeds a predetermined range, the processor 21 rewrites the material information assigned to some finite elements included in the mesh, From materials showing, non-copper materials are shown. Thereby, the remaining copper rate in the mesh calculated by the process of step S13 falls.

  By performing the processes of steps S13 to S15, the remaining copper ratio in each mesh is included in a predetermined range, and the variation in the remaining copper ratio in the plane direction of the multilayer wiring board 10 is reduced.

  The process of step S16 is the same process as the process of step S3 shown in FIG. That is, the processor 21 divides the multilayer wiring board 10 into a plurality of regions on a plane perpendicular to the mounting surface (step S16).

FIG. 7 is a perspective view showing an example of dividing a multilayer wiring board into a plurality of regions.
In FIG. 7, the multilayer wiring board 10 is divided into three regions a, b, and c by planes 10b and 10c perpendicular to the mounting surface 10a.

  When the multilayer wiring board 10 is divided as shown in FIG. 7, the processor 21 calculates the remaining copper ratio in each region ac based on the material information assigned to the finite elements included in each region ac. Calculate (step S17). The process of step S17 is performed similarly to the process of step S4 shown in FIG.

  Next, the processor 21 determines whether or not the remaining copper ratio in each region is within a predetermined range (step S18). The predetermined range is set, for example, as a range of 40% to 50% or the like according to the allowable range of unevenness in the surface direction.

  When there is a region where the remaining copper ratio is not within the above range, the processor 21 executes the process of step S19, and when the remaining copper ratio is included in the above range in all the regions a to c. The process of step S20 is performed.

  In the process of step S19, the processor 21 rewrites the material information assigned to the finite element included in the region where the remaining copper ratio is not within the above range, and the copper material and the non-conductive material (non-conductive material) Replacement with a copper material (for example, prepreg) is performed. Thereafter, the processor 21 repeats the processing from step S12.

  For example, when the remaining copper ratio in a certain region is lower than a predetermined range, the processor 21 rewrites material information assigned to some finite elements included in the region, and the non-copper material From what shows, it shall show the material of a copper material. As a result, the remaining copper ratio in the region calculated in the process of step S17 increases.

  On the other hand, for example, when the remaining copper ratio in a certain area exceeds a predetermined range, the processor 21 rewrites material information assigned to some finite elements included in the area, From materials showing, non-copper materials are shown. Thereby, the remaining copper rate in the area | region calculated by the process of step S17 falls.

By performing the processing of steps S16 to S19, the remaining copper ratio in each of the areas a to c is included in a predetermined range, and the variation in the remaining copper ratio between the areas a to c is reduced.
Hereinafter, an example of the processing in steps S17 to S19 when the material information is rewritten will be described with reference to FIGS. 8, 9, and 10. FIG.

FIG. 8 is a perspective view showing an example of a finite element to be rewritten as material information.
FIG. 8 shows the multilayer wiring board 10 divided into regions a to c by the process of step S6.

For the sake of simplicity, 3 × 9 × 1 finite elements in the first column as viewed from the Y direction in FIG. 8 among 3 × 9 × N finite elements included in the multilayer wiring board 10 will be described below. Explain to the subject.
FIG. 9 is a diagram illustrating an example of a multilayer wiring board before rewriting material information. FIG. 9 is a side view of the multilayer wiring board 10 as seen from the direction of the arrow Y in FIG.

  Regions a to c each include nine finite elements. For example, the region a includes finite elements 30, 31, 32, 33, 34, 35, 36, 37, and 38, and the region b includes finite elements 39, 40, 41, 42, 43, 44, 45, 46, 47. The region c includes finite elements 48, 49, 50, 51, 52, 53, 54, 55, and 56. Moreover, the material information allocated to the finite elements 30, 32, 36, 38, 40, 42, 46, 48, 50, 54, 56 among the finite elements 30 to 53 indicates the material of the copper material. The material information assigned other than that indicates a non-copper material.

  In the case of the example in FIG. 9, the remaining copper ratio in the portion of the finite elements 30 to 38 is 44% in the region a and the remaining copper ratio in the portion of the finite elements 39 to 47 is in the region b. In 33% and the area | region c, the remaining copper rate in the part in the finite elements 48-56 is calculated | required as 44%.

  When the predetermined range in the process of step S18 is 40% to 50%, the remaining copper ratio in the region b is lower than the range. Therefore, the processor 21 performs the process of step S19, for example, rewrites the material information assigned to the finite element 44 in the region b, and replaces the non-copper material with the copper material. Thereby, the remaining copper rate in the region b is increased.

FIG. 10 is a diagram illustrating an example of a multilayer wiring board after rewriting of material information.
10 shows the multilayer wiring board 10A as viewed from the direction of the arrow Y in FIG. 8. In FIG. 10, the same elements as those shown in FIG.

By the processing in step S19, the material information assigned to the finite element 44 in the region b is replaced with information indicating a copper material from information indicating a non-copper material.
Therefore, in the process of step S17 performed again after the process of step S19, the remaining copper ratio in the portion of the finite elements 39 to 47 in the region b is obtained as 44%. As a result, the remaining copper ratio in the areas a to c falls within the above range, and therefore the process of step S20 is performed by the determination of step S18 again.

  In the above, for simplification of description, among the 3 × 9 × N finite elements included in the multilayer wiring board 10, 3 × 9 × 1 finite elements in the first row viewed from the Y direction in FIG. Although described in the subject, the same processing is performed on 3 × 9 × N finite elements.

  In the process of step S20, the processor 21 reads the material property information 6d stored in the HDD 23 and executes the structural analysis of the multilayer wiring board 10A. The processor 21 calculates, for example, the density, elastic modulus, thermal expansion coefficient, and the like of the conductive material and non-conductive material of each mesh based on the material information assigned to the finite element of each mesh and the physical property value of the material. The warpage of the plane of the substrate 10A is analyzed.

  Further, for example, the processor 21 calculates the density, elastic modulus, coefficient of thermal expansion, etc. of the copper material and the non-copper material of each region from the material information assigned to the finite element of each region and the physical property value of the material. Calculate and analyze unevenness and the like generated on the mounting surface of the multilayer wiring board.

  Thereafter, a multilayer wiring board is designed based on the structural analysis result. For example, when the copper material and the non-copper material are replaced in a certain finite element by the processing in step S15 or step S19, for example, the change of the wiring arrangement position is performed based on the position of the finite element. Etc. are performed. In addition, for example, a dummy pattern may be provided in a portion corresponding to the finite element in which the non-copper material is replaced with the copper material, so that the ratio of the copper material is increased.

Note that the processing order of each step is not limited to the above. For example, the processing of steps S16 to S19 may be performed before the processing of steps S12 to S15.
Next, an example of manufacturing a multilayer wiring board designed based on the analysis result of the structural analysis method of the second embodiment will be described.

FIG. 11 is a perspective view showing an example of the manufacturing process of a multilayer wiring board designed based on the analysis result of the structural analysis method according to the second embodiment.
FIG. 11 shows a state in which two wiring layers (formed by an insulating layer and a wiring) are stacked.

  Wirings (copper wirings) 61 and 62 are formed on the insulating layer 60, and wirings 64 and 65 are formed on the insulating layer 63. A surface 66 indicated by a dotted line is a surface that divides the regions D and E set during the structural analysis. By the structure analysis method of the second embodiment, replacement of the copper material and the non-copper material was performed so that the remaining copper ratio in each of the regions D and E was within a predetermined range. In the example of FIG. 11, the wirings 61 to 65 are evenly formed across the surface 66.

When such two wiring layers are stacked in the stacking direction of the arrow in FIG. 11, the following structure is obtained.
FIG. 12 is a cross-sectional view showing an example of forming a multilayer wiring board designed based on the analysis result of the structural analysis method of the second embodiment. 12 shows a cross-sectional view taken along line L1-L1 in FIG. 11 after the two wiring layers in FIG. 11 are stacked.

  In the multilayer wiring board designed based on the analysis result of the structural analysis method of the second embodiment, the unevenness in the surface 67 is reduced because the remaining copper ratio in the regions D and E is small. The

On the other hand, when the copper material and the non-copper material are not replaced so that the remaining copper ratio in each of the regions D and E falls within a predetermined range, for example, the following is performed.
FIG. 13 is a perspective view showing an example of the manufacturing process of the multilayer wiring board when the copper material and the non-copper material are not replaced.

  In the example of FIG. 13, there are two wirings 61 and 64 in the region D, and one wiring 65 in the region E, and the variation in the remaining copper ratio between the regions D and E is large. When such two wiring layers are stacked in the stacking direction of the arrow in FIG. 13, the following structure is obtained.

  FIG. 14 is a cross-sectional view showing an example of forming a multilayer wiring board when the copper material and the non-copper material are not replaced. 14 shows a cross-sectional view taken along line L2-L2 of FIG. 13 after the two wiring layers of FIG. 13 are stacked.

When the variation in the remaining copper ratio between the regions D and E is large, as shown in FIG. 13, in the region E where the remaining copper ratio is small, the insulating layer (resin) is pushed in during the lamination, and the surface 67 is uneven.
As described above, in the structural analysis method of the present embodiment, during the structural analysis of the multilayer wiring board, the multilayer wiring board is divided into a plurality of regions on a plane perpendicular to the mounting surface, and the remaining copper ratio in each region is within a predetermined range. Replacement of the copper material and the non-copper material is performed so as to fit inside. Thereby, the variation in the remaining copper ratio between the regions is reduced, and unevenness in the surface direction of the multilayer wiring board is reduced. Since the unevenness of the mounting surface is reduced, the occurrence of mounting defects (for example, electrical connection defects such as electronic components or short circuits) is suppressed.

  Further, in the structure analysis method of the present embodiment, a plurality of meshes larger than the finite element are set in each wiring layer, and the copper material is used so that the remaining copper ratio in each mesh is within a predetermined range. Replacement with non-copper material is performed. Thereby, the variation in the remaining copper ratio between meshes decreases, and a multilayer wiring board with less warpage can be realized.

(Third embodiment)
Hereinafter, another example of dividing the multilayer wiring board into a plurality of regions on a surface perpendicular to the mounting surface in the process of step S16 in FIG. 4 will be described.

FIG. 15 is a top view of a semiconductor device showing another example of region division.
FIG. 16 is a cross-sectional view of a semiconductor device showing another example of region division. FIG. 16 shows a cross-sectional view taken along line L3-L3 in FIG.

The semiconductor device 70 includes a multilayer wiring board 71, a mounting board 72, and an electronic component 73.
The multilayer wiring board 71 includes a plurality of wiring layers formed of wiring and insulating layers, but is not shown in FIGS. 15 and 16.

The mounting substrate 72 is a package substrate, for example, and is electrically connected to the multilayer wiring substrate 71 by bumps 74.
The electronic component 73 is, for example, an LSI (Large Scale Integration circuit), and is disposed on the mounting substrate 72.

  In the example of FIGS. 15 and 16, the region located immediately below the mounting substrate 72 mounted on the multilayer wiring substrate 71 is divided into regions F, G, and H. The material information assigned to the finite elements hatched among the finite elements in each region F to H indicates the material of the copper material, and the material information assigned to the other finite elements is not. This indicates a copper material.

  When the multilayer wiring board 71 is divided into the regions F to H as shown in FIGS. 15 and 16 in the process of step S16 in FIG. 4, the remaining copper ratio in the regions F to H is calculated in the process of step S17. Will be calculated. In this case, as shown in FIG. 7, the calculation range can be narrowed compared with the case of calculating the remaining copper ratio in the areas a to c obtained by dividing the entire multilayer wiring board 10, so that the calculation amount can be reduced.

In the example illustrated in FIG. 16, the remaining copper ratio in the region F is calculated to be 54%, the remaining copper ratio in the region G is 58%, and the remaining copper ratio in the region H is calculated to be 54%.
When the predetermined range when the material information is rewritten and the copper material and the non-copper material are replaced is 55 to 60%, the remaining copper ratio is out of the above range in the regions F and H. ing. Therefore, the process of step S19 is performed.

FIG. 17 is a cross-sectional view of the semiconductor device after rewriting the material information.
FIG. 17 is a cross-sectional view taken along line L3-L3 in FIG.
In the example of FIG. 17, the material information assigned to the finite elements in the regions F and H is rewritten, and the ratio of the copper material to the non-copper material is increased. As a result, the remaining copper ratio in the regions F and H calculated in step S17 increases. In the example of FIG. 17, the remaining copper ratio in the regions F and H is 57%, which is within the above range (55 to 60%). Thereby, the variation in the remaining copper ratio between the regions F to H is suppressed, and it is possible to suppress the occurrence of unevenness in the portion (region) where the mounting substrate 72 is actually mounted on the mounting surface of the multilayer wiring substrate 71. For this reason, generation | occurrence | production of mounting defect is suppressed.

  As described above, one aspect of the structural analysis method, the structural analysis apparatus, and the program according to the present invention has been described based on the embodiments. However, these are merely examples, and the present invention is not limited to the above description.

1 Structure analysis device (computer)
2 processor 3 storage unit 4 multilayer wiring board 4a-4c wiring layer 4d mounting surface 4e, 4f surface AC region 6a design data 6b material property information 5, 5a-5i finite element

Claims (5)

A structure analysis method for analyzing a structure of a substrate including a plurality of wiring layers by computer simulation,
Computer
Dividing each of the plurality of wiring layers into a plurality of first regions of a first size;
Based on the design data of the substrate, material information indicating materials included in each of the plurality of first regions is assigned to each of the plurality of first regions,
Dividing the substrate into a plurality of second regions on a surface perpendicular to the mounting surface of the substrate;
Based on the material information assigned to the third region included in each of the plurality of second regions out of the plurality of first regions, the number of conductive materials in each of the plurality of second regions. 1 content rate is obtained,
In each of the plurality of second regions, the material information assigned to the third region is rewritten so that the first content rate falls within the first range, thereby the plurality of second regions. Replace the conductive material and non-conductive material in the region,
A structural analysis method characterized by the above. A plurality of fourth regions larger than the first size are set in each of the plurality of wiring layers,
Of the plurality of first regions, the conductive material in each of the plurality of fourth regions is based on the material information assigned to the fifth region included in each of the plurality of fourth regions. Determining the second content,
In each of the plurality of fourth regions, the material information assigned to the fifth region is rewritten so that the second content rate falls within the second range, thereby the plurality of fourth regions. Replacing the conductive material and the non-conductive material in a region;
The structural analysis method according to claim 1, wherein:   The structural analysis method according to claim 1, wherein the plurality of second regions are set in the substrate in a region located immediately below another substrate disposed on the substrate. . A structural analysis device for analyzing a structure of a substrate including a plurality of wiring layers by computer simulation,
Have a processor,
The processor is
Dividing each of the plurality of wiring layers into a plurality of first regions of a first size;
Based on the design data of the substrate, material information indicating materials included in each of the plurality of first regions is assigned to each of the plurality of first regions,
Dividing the substrate into a plurality of second regions on a surface perpendicular to the mounting surface of the substrate;
Based on the material information assigned to the third region included in each of the plurality of second regions out of the plurality of first regions, the number of conductive materials in each of the plurality of second regions. 1 content rate is obtained,
In each of the plurality of second regions, the material information assigned to the third region is rewritten so that the first content rate falls within the first range, thereby the plurality of second regions. Replace the conductive material and non-conductive material in the region,
A structural analysis device characterized by that. A program for causing a computer to execute processing for analyzing a structure of a substrate including a plurality of wiring layers by computer simulation,
In a substrate including a plurality of wiring layers, each of the plurality of wiring layers is divided into a plurality of first regions of a first size,
Based on the design data of the substrate, material information indicating materials included in each of the plurality of first regions is assigned to each of the plurality of first regions,
Dividing the substrate into a plurality of second regions on a surface perpendicular to the mounting surface of the substrate;
Based on the material information assigned to the third region included in each of the plurality of second regions out of the plurality of first regions, the number of conductive materials in each of the plurality of second regions. 1 content rate is obtained,
In each of the plurality of second regions, the material information assigned to the third region is rewritten so that the first content rate falls within the first range, thereby the plurality of second regions. Replace the conductive material and non-conductive material in the region,
A program for causing the computer to execute processing.

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