JP2012227376A - Layout design method and layout design program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a chip size.SOLUTION: In a layout design method, in a higher-level hierarchy in a hierarchical layout design in which the layout design of a semiconductor integrated circuit is performed for each hierarchy, a layout design device sets, to a chip area 1, a hierarchical block arrangement area 2 that is an area where a hierarchical block having a predetermined function, by which arrangement and wiring are performed at a hierarchy under the higher-level hierarchy, is arranged and that includes a free unit cell arrangement area 3 and a unit cell arrangement area 4 for the hierarchical block. The layout design device performs arrangement and wiring using the unit cell arrangement area of a peripheral area 5, which surrounds the hierarchical block arrangement area 2 in the chip area 1, and the free unit cell arrangement area 3 in the hierarchical block arrangement area 2.

Description

  The present invention relates to a layout design method for a semiconductor integrated circuit and a layout design program.

  As one of layout design methods for a semiconductor integrated circuit, there is a hierarchical layout design in which a semiconductor integrated circuit is divided into a plurality of blocks for each function. Each of the plurality of blocks is referred to as a hierarchical block.

  According to this method, since the scale of a circuit designed at a time can be reduced, the amount of circuit information can be reduced. As a result, it is possible to reduce the load on the computer used for the design (for example, increase in the memory capacity used, load on the CPU (Central Processing Unit), etc.). Also, according to this method, the design work can be advanced in parallel for each hierarchical block, so that the design period can be shortened.

  In the hierarchical layout design, the design is performed for each hierarchy, and in the upper hierarchy, the placement and routing is performed in a state where the hierarchical block placement area where the hierarchical block is placed is set as the placement prohibited area in the chip area. Here, the placement and routing in the upper hierarchy is performed avoiding the hierarchical block placement area.

JP-A-4-333260 JP-A-5-151313 JP 2000-156414 A JP 2005-235804 A

  However, in the hierarchical layout design, as described above, the arrangement and wiring in the upper hierarchy is performed avoiding the hierarchical block arrangement area, and therefore it is necessary to largely bypass the wiring when the scale of the hierarchical block is large.

  If the wiring is largely detoured, the wiring distance becomes long, and the number of circuit elements such as buffer elements provided in the wiring increases accordingly. As a result, the area of the chip region occupied by the unit cells used for circuit elements such as wiring and buffer elements increases, which may increase the chip size.

According to one aspect of the invention, the following layout design method is provided.
In this layout design method, the layout design apparatus includes a hierarchical block having a predetermined function in which placement and routing is performed in a hierarchy below the upper hierarchy in the upper hierarchy in the hierarchical layout design in which the layout design of the semiconductor integrated circuit is performed by hierarchy. An area to be arranged, and a hierarchical block arrangement area including an empty unit cell arrangement area and a unit cell arrangement area for a hierarchical block is set as a chip area, and a peripheral area surrounding the hierarchical block arrangement area in the chip area is set. Placement and wiring is performed using the unit cell placement area and the empty unit cell placement area in the hierarchical block placement area.

  According to the disclosed layout design method and layout design program, the chip size can be reduced.

It is a figure which shows an example of the layout design procedure which concerns on 1st Embodiment. It is a figure which shows an example of the hardware of the layout design apparatus which concerns on 2nd Embodiment. It is a flowchart which shows an example of the layout design procedure which concerns on 2nd Embodiment. It is a block diagram which shows an example of the circuit designed in the upper hierarchy based on 2nd Embodiment. It is a flowchart which shows an example of the procedure of the wiring arrangement | positioning in the upper hierarchy based on 2nd Embodiment. It is a figure which shows an example of the chip layout which concerns on 2nd Embodiment. It is a figure which shows an example of the chip layout which concerns on 2nd Embodiment. It is a figure which shows an example of the chip layout which concerns on 2nd Embodiment. It is a flowchart which shows an example of the procedure of wiring arrangement | positioning of the hierarchical block which concerns on 2nd Embodiment. It is a figure which shows an example of the chip layout which concerns on 2nd Embodiment. It is a figure which shows an example of the chip layout which concerns on 2nd Embodiment. It is a figure which shows an example of the chip layout which concerns on 2nd Embodiment. It is a block diagram which shows the reference example of the circuit designed in an upper hierarchy.

Hereinafter, embodiments will be described with reference to the drawings.
[First Embodiment]
The first embodiment relates to hierarchical layout design. In hierarchical layout design, a semiconductor integrated circuit is divided into a plurality of blocks for each function. Each of the plurality of blocks is referred to as a hierarchical block. In the hierarchical layout design, the design is performed for each hierarchy.

  In the upper hierarchy, placement and routing is performed in a state where the hierarchical block placement area where the hierarchical blocks are placed is set as the chip area. Hierarchical block placement and routing is performed in a lower hierarchy. The highest hierarchy among the upper hierarchy is referred to as the highest hierarchy (top hierarchy). The first embodiment relates to a layout design method in an upper hierarchy.

FIG. 1 is a diagram illustrating an example of a layout design procedure according to the first embodiment.
First, as shown in FIG. 1A, a hierarchical block arrangement area 2 in which hierarchical blocks are arranged is set to a chip area 1. The hierarchical block arrangement area 2 includes an empty unit cell arrangement area 3 and a unit cell arrangement area 4 for a hierarchical block. An area surrounding the hierarchical block arrangement area 2 in the chip area 1 is a peripheral area 5. In the peripheral area 5, a plurality of unit cell arrangement areas are set.

  Next, as shown in FIG. 1B, placement and routing is performed using the unit cell placement area in the peripheral area 5 and the empty unit cell placement area 3 in the hierarchical block placement area 2. Here, the unit cell arrangement area 4 for hierarchical blocks is set as an arrangement prohibition area. In FIG. 1B, the unit cells 6 arranged in the upper hierarchy and the wiring 7 drawn in the upper hierarchy are shown.

  As described above, according to the first embodiment, the hierarchical block arrangement area 2 set in the chip area 1 in the upper hierarchy includes the empty unit cell arrangement area 3, and the empty unit cell arrangement area 3 is used to Placement and wiring in the hierarchy is performed. According to this configuration, unit cells used for circuit elements such as buffer elements provided in the wiring can be arranged in the empty unit cell arrangement region 3.

  Thereby, wiring can be passed over the hierarchical block arrangement | positioning area | region 2, and wiring distance can be shortened. For this reason, it is possible to reduce the area of the chip region 1 occupied by the unit cells used for wiring and circuit elements such as buffer elements, and to reduce the chip size.

  Further, since the wiring distance can be shortened, the influence of wiring delay is reduced, so that timing convergence can be facilitated. In addition, since the wiring distance can be shortened and the number of unit cells used for circuit elements such as buffer elements can be reduced, the power consumption of the semiconductor integrated circuit can be reduced.

[Second Embodiment]
Next, a more specific embodiment of the layout design method of the first embodiment will be described as a second embodiment.

The layout design of the second embodiment is performed by a layout design apparatus.
FIG. 2 is a diagram illustrating an example of hardware of the layout design apparatus according to the second embodiment.

  The entire layout design apparatus 10 is controlled by the CPU 11. A RAM (Random Access Memory) 12 and a plurality of peripheral devices are connected to the CPU 11 via a bus 18.

  The RAM 12 is used as a main storage device of the layout design apparatus 10. The RAM 12 temporarily stores at least part of an OS (Operating System) program and application programs to be executed by the CPU 11. The RAM 12 stores various data necessary for processing by the CPU 11.

  Peripheral devices connected to the bus 18 include a hard disk drive (HDD) 13, a graphic processing device 14, an input interface 15, an optical drive device 16, and a communication interface 17.

  The HDD 13 magnetically writes and reads data to and from the built-in disk. The HDD 13 is used as a secondary storage device of the layout design apparatus 10. The HDD 13 stores an OS program, application programs, and various data. Note that a semiconductor storage device such as a flash memory can also be used as the secondary storage device.

  A monitor 14 a is connected to the graphic processing device 14. The graphic processing device 14 displays an image on the screen of the monitor 14 a in accordance with a command from the CPU 11. Examples of the monitor 14a include a display device using a CRT (Cathode Ray Tube) and a liquid crystal display device.

  A keyboard 15 a and a mouse 15 b are connected to the input interface 15. The input interface 15 transmits signals sent from the keyboard 15a and the mouse 15b to the CPU 11. The mouse 15b is an example of a pointing device, and other pointing devices can also be used. Examples of other pointing devices include a touch panel, a tablet, a touch pad, and a trackball.

  The optical drive device 16 reads data recorded on the optical disc 16a using a laser beam or the like. The optical disk 16a is a portable recording medium on which data is recorded so that it can be read by reflection of light. The optical disc 16a includes a DVD (Digital Versatile Disc), a DVD-RAM, a CD-ROM (Compact Disc Read Only Memory), a CD-R (Recordable) / RW (ReWritable), and the like.

  The communication interface 17 is connected to the network 19. The communication interface 17 transmits and receives data to and from other computers or communication devices via the network 19.

The processing functions of the second embodiment can be realized by the hardware as described above.
Next, a layout design procedure according to the second embodiment will be described.

FIG. 3 is a flowchart showing an example of a layout design procedure according to the second embodiment.
[Step S10] The layout design apparatus 10 performs placement and routing in the upper hierarchy.

[Step S20] The layout design apparatus 10 performs placement and routing of hierarchical blocks.
[Step S30] The layout design apparatus 10 performs verification such as timing analysis and physical verification on the hierarchical block.

  [Step S40] The layout design apparatus 10 performs verification such as timing analysis and physical verification on the upper layer. Step S40 is performed in parallel with step S30.

[Step S50] The layout design apparatus 10 performs final verification in a state where the hierarchical block and the upper hierarchy are synthesized, and ends the processing.
The above steps S10 to S50 may be performed by different layout design apparatuses. That is, the processing function of the layout design apparatus 10 may be realized by a plurality of layout design apparatuses.

Next, details of the wiring arrangement in the upper hierarchy shown in step S10 will be described. First, an outline of a circuit designed in the upper hierarchy will be described.
FIG. 4 is a block diagram illustrating an example of a circuit designed in the upper hierarchy according to the second embodiment. A hierarchical block arrangement area 22 is set in the chip area 21. In this state, the placement and wiring of the flip-flop (FF) circuits 23 and 24 are performed, and further, the wiring 25 connecting the flip-flop circuit 23 and the flip-flop circuit 24 is drawn.

  The wiring elements 25 are provided with buffer elements 26 at regular intervals. Here, the wiring 25 is drawn through the hierarchical block arrangement region 22. The buffer element 26 is also arranged in the hierarchical block arrangement area 22. The wiring 25 may be provided with other circuit elements such as a resistance element and a capacitor element in addition to the buffer element 26.

Next, the wiring arrangement procedure in the upper hierarchy will be described with reference to FIGS.
FIG. 5 is a flowchart illustrating an example of a wiring arrangement procedure in the upper hierarchy according to the second embodiment. 6 to 8 are diagrams illustrating an example of a chip layout according to the second embodiment. Hereinafter, description will be made along the flowchart of FIG. 5 with reference to FIGS.

  [Step S11] As shown in FIG. 6, the layout design apparatus 10 sets a hierarchical block arrangement area 22 in the chip area 21. This step is referred to as a chip floor plan, for example. The hierarchical block arrangement area 22 includes a rectangle surrounded by a side in the X direction and a side in the Y direction that intersects the X direction.

  The hierarchical block arrangement area 22 includes a plurality of empty unit cell arrangement areas and a plurality of unit cell arrangement areas for hierarchical blocks. The empty unit cell arrangement areas are arranged at regular intervals in the X direction and the Y direction. That is, the empty unit cell arrangement area is set in a grid pattern in the hierarchical block arrangement area 22.

  In addition, the empty unit cell arrangement area is set with a certain interval from one end of the hierarchical block arrangement area 22 to the other opposite end. In the example shown in FIG. 6, the empty unit cell arrangement area is set with a unit cell arrangement area for one hierarchical block in between. The ratio of the empty unit cell arrangement area in the hierarchical block arrangement area 22 is, for example, about 25%. This ratio can be appropriately set according to, for example, the scale of the semiconductor integrated circuit to be designed.

  In the example shown in FIG. 6, one hierarchical block arrangement area is set in the chip area 21, but a plurality of other hierarchical block arrangement areas may be set. An area surrounding the hierarchical block arrangement area 22 in the chip area 21 is a peripheral area 21a. A plurality of unit cell arrangement areas are set in the peripheral area 21a.

  [Step S12] As shown in FIG. 7, the layout design apparatus 10 sets the unit cell arrangement area for hierarchical blocks in the hierarchical block arrangement area 22 as an arrangement prohibited area. That is, the empty unit cell arrangement area in the hierarchical block arrangement area 22 and the unit cell arrangement area of the peripheral area 21a are set as arrangement permission areas.

  [Step S13] As shown in FIG. 8, the layout designing apparatus 10 uses the unit cell arrangement area in the peripheral area 21a and the empty unit cell arrangement area in the hierarchical block arrangement area 22 to Perform placement. Here, the arrangement of the unit cells is fixed.

  [Step S14] As shown in FIG. 8, the layout design apparatus 10 performs wiring in the upper hierarchy and ends the process. As a result, the unit cells arranged in the upper hierarchy are connected. Here, the wiring arrangement is fixed.

As described above, placement and routing in the upper hierarchy is performed.
Next, a detailed procedure of the wiring arrangement of the hierarchical block shown in step S20 of FIG. 3 will be described with reference to FIGS.

  FIG. 9 is a flowchart illustrating an example of a wiring layout procedure of the hierarchical block according to the second embodiment. 10 to 12 are diagrams illustrating an example of a chip layout according to the second embodiment. Hereinafter, description will be made along the flowchart of FIG. 9 with reference to FIGS.

  [Step S21] As shown in FIG. 10, the layout design apparatus 10 cancels the setting of the placement prohibited area for the unit cell placement area for the hierarchical block set in step S12.

  [Step S22] As shown in FIG. 10, the layout design apparatus 10 sets an empty unit cell arrangement area in the hierarchical block arrangement area 22 as an arrangement prohibition area. That is, the unit cell arrangement area for hierarchical blocks in the hierarchical block arrangement area 22 is set as an arrangement permission area.

  [Step S23] As shown in FIG. 11, the layout designing apparatus 10 uses the unit cell arrangement area for the hierarchical block in the hierarchical block arrangement area 22 to arrange the unit cells of the hierarchical block. Here, the unit cells arranged in the hierarchical block arrangement area 22 in the upper hierarchy in step S13 are rearranged at the same position as the unit cells of the hierarchical block.

  [Step S24] As shown in FIG. 11, the layout design apparatus 10 performs wiring of hierarchical blocks in the hierarchical block arrangement area 22. Here, the wiring drawn in the hierarchical block arrangement area 22 in the upper hierarchy in step S14 is rearranged at the same position as the wiring of the hierarchical block.

  [Step S25] As shown in FIG. 12, the layout design apparatus 10 cancels the setting of the placement prohibited area for the empty unit cell placement area. That is, the empty unit cell arrangement area in the hierarchical block arrangement area 22 and the unit cell arrangement area for the hierarchical block are set as arrangement permission areas.

[Step S26] The layout design apparatus 10 optimizes the unit cells and wirings arranged in the hierarchical block arrangement region 22 and ends the process.
As described above, placement and routing of hierarchical blocks is performed.

  In a semiconductor integrated circuit designed and generated based on the above procedure, a functional module placement area in which functional modules realized by hierarchical blocks are placed on a semiconductor substrate, and wiring crossing over the functional module placement area And a circuit element such as a buffer element provided in the wiring.

  In the functional module arrangement area, unused unit cell arrangement areas and unit cell arrangement areas in which unit cells for circuit elements such as buffer elements are arranged are arranged in a grid pattern. Then, unit cells for realizing the functions of the functional modules are arranged in other unit cell arrangement areas in the functional module arrangement area.

  As described above, according to the second embodiment, the hierarchical block arrangement area 22 set in the chip area 21 in the upper hierarchy includes the empty unit cell arrangement area, and this empty unit cell arrangement area is used. Thus, placement and routing in the upper hierarchy is performed. According to this configuration, unit cells used for circuit elements such as buffer elements provided in the wiring can be arranged in the empty unit cell arrangement region.

  Thereby, the wiring can be passed over the hierarchical block arrangement region 22, and the wiring distance can be shortened. For this reason, it is possible to reduce the area of the chip region 21 occupied by the unit cells used for circuit elements such as wiring and buffer elements, and to reduce the chip size.

  Further, since the wiring distance can be shortened, the influence of wiring delay is reduced, so that timing convergence can be facilitated. In addition, since the wiring distance can be shortened and the number of unit cells used for circuit elements such as buffer elements can be reduced, the power consumption of the semiconductor integrated circuit can be reduced.

Here, the case where the wiring is arranged so as to bypass the hierarchical block arrangement area 22 will be described using the example shown in FIG.
FIG. 13 is a block diagram illustrating a reference example of a circuit designed in an upper hierarchy.

  When the wiring 25 connecting the flip-flop circuit 23 and the flip-flop circuit 24 is arranged so as to bypass the hierarchical block arrangement area 22, the wiring distance of the wiring 25 becomes long as shown in FIG. The number of increases.

  On the other hand, in the second embodiment, as shown in FIG. 4, since the wiring 25 can be drawn through the hierarchical block arrangement region 22, the wiring distance can be shortened, and the number of buffer elements 26 can be reduced. Can be reduced.

  Furthermore, according to the second embodiment, the empty unit cell arrangement area in the hierarchical block arrangement area 22 set in the chip area 21 is set as the arrangement prohibition area, and the arrangement and wiring of the hierarchical blocks are performed. That is, the empty unit cell arrangement area in the hierarchy block arrangement area 22 is not used in the arrangement and wiring of the hierarchy block.

  For this reason, even if there is a design change in the upper hierarchy and the position of the empty unit cell arrangement area where the unit cell is arranged is changed, the unit cell arrangement position of the hierarchical block (the unit cell arranged in the upper hierarchy is rearranged) Do not need to be changed. This makes it possible to easily design the hierarchical block.

  Furthermore, according to the second embodiment, the empty unit cell arrangement area is set in a lattice shape in the hierarchical block arrangement area 22. For this reason, unit cells arranged in the upper hierarchy can be distributed in the hierarchical block arrangement area 22. Thereby, it can suppress that the wiring of a hierarchical block is concentrated in part, and can suppress that wiring becomes complicated. Thereby, for example, the number of wiring layers can be suppressed, and the influence of signal noise due to inter-wiring capacitance can be suppressed.

  Furthermore, according to the second embodiment, the empty unit cell arrangement area is set with a certain interval from one end of the hierarchical block arrangement area 22 to the other opposite end. According to this configuration, unit cells for circuit elements such as buffer elements can be arranged at regular intervals so as to cross the hierarchical block arrangement area 22 in the upper hierarchy.

  As a result, circuit elements such as buffer elements can be provided in the wiring crossing the hierarchical block arrangement region 22 drawn in the upper hierarchy at regular intervals. For this reason, even when the scale of the hierarchical block arrangement area 22 is large, it is possible to draw wiring so as to cross the hierarchical block arrangement area 22 in the upper hierarchy.

  The above processing functions can be realized by a computer. In that case, a program describing the processing contents of the functions that the layout design apparatus 10 should have is provided. By executing the program on a computer, the above processing functions are realized on the computer. The program describing the processing contents can be recorded on a computer-readable recording medium. Examples of the computer-readable recording medium include a magnetic storage device, an optical disk, a magneto-optical recording medium, and a semiconductor memory. Examples of the magnetic storage device include a hard disk device (HDD), a flexible disk (FD), and a magnetic tape. Optical discs include DVD, DVD-RAM, CD-ROM / RW, and the like. Magneto-optical recording media include MO (Magneto-Optical disk).

  When distributing the program, for example, a portable recording medium such as a DVD or a CD-ROM in which the program is recorded is sold. It is also possible to store the program in a storage device of a server computer and transfer the program from the server computer to another computer via a network.

  The computer that executes the program stores, for example, the program recorded on the portable recording medium or the program transferred from the server computer in its own storage device. Then, the computer reads the program from its own storage device and executes processing according to the program. The computer can also read the program directly from the portable recording medium and execute processing according to the program. In addition, each time a program is transferred from a server computer connected via a network, the computer can sequentially execute processing according to the received program.

  In addition, at least a part of the above processing functions can be realized by an electronic circuit such as a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), or a PLD (Programmable Logic Device).

The following additional notes are further disclosed with respect to the embodiments including the first and second embodiments described above.
(Appendix 1) The layout design device
In the upper hierarchy in the hierarchical layout design that performs layout design of semiconductor integrated circuits by hierarchy,
A hierarchical block having a hierarchical block having a predetermined function for performing placement and routing in a hierarchy below the upper hierarchy, including a free unit cell placement area and a unit cell placement area for the hierarchy block Set the placement area to the chip area,
Place and route using the unit cell placement area in the peripheral area surrounding the hierarchical block placement area in the chip area and the empty unit cell placement area in the hierarchical block placement area,
A layout design method characterized by that.

(Supplementary Note 2) The layout design apparatus is
In a hierarchy below the upper hierarchy,
The empty unit cell arrangement area in the hierarchical block arrangement area set in the chip area is set as an arrangement prohibition area, and the arrangement and wiring of the hierarchical block is performed.
The layout design method according to appendix 1, wherein:

(Supplementary Note 3) The hierarchical block arrangement area includes a plurality of empty unit cell arrangement areas, and the plurality of empty unit cell arrangement areas are set in a grid pattern in the hierarchical block arrangement area.
The layout design method according to appendix 1 or 2, wherein:

(Supplementary Note 4) The hierarchical block arrangement area includes a plurality of empty unit cell arrangement areas, and the plurality of empty unit cell arrangement areas are spaced from one end of the hierarchical block arrangement area to the opposite other end. Set,
The layout design method according to any one of appendices 1 to 3, wherein:

(Appendix 5) The layout design device
Canceling the setting of the placement prohibition area with respect to the empty unit cell placement area, and performing optimization within the hierarchical block in which placement and routing has been performed,
The layout design method according to appendix 2, characterized in that:

(Appendix 6)
In the upper hierarchy in the hierarchical layout design that performs layout design of semiconductor integrated circuits by hierarchy,
A hierarchical block having a hierarchical block having a predetermined function for performing placement and routing in a hierarchy below the upper hierarchy, including a free unit cell placement area and a unit cell placement area for the hierarchy block Set the placement area to the chip area,
Place and route using the unit cell placement area in the peripheral area surrounding the hierarchical block placement area in the chip area and the empty unit cell placement area in the hierarchical block placement area,
A layout design program characterized by causing processing to be executed.

(Additional remark 7) On the semiconductor substrate, a functional module arrangement area where functional modules having a predetermined function are arranged, wiring crossing over the functional module arrangement area, and circuit elements provided in the wiring are arranged. ,
In the functional module arrangement area, unit cell arrangement areas that are not used and unit cell arrangement areas in which unit cells for the circuit elements are arranged are set in a lattice pattern,
A semiconductor integrated circuit.

DESCRIPTION OF SYMBOLS 1,21 Chip area | region 2,22 Hierarchical block arrangement | positioning area | region 3 Unoccupied unit cell arrangement | positioning area | region 4 Unit cell arrangement | positioning area | region for hierarchical blocks 5,21a Peripheral area | region 6 Unit cell arrange | positioned by the upper hierarchy 7 Wiring drawn by the upper hierarchy 23 , 24 Flip-flop circuit 25 Wiring 26 Buffer element

Claims (5)

Layout design equipment
In the upper hierarchy in the hierarchical layout design that performs layout design of semiconductor integrated circuits by hierarchy,
A hierarchical block having a hierarchical block having a predetermined function for performing placement and routing in a hierarchy below the upper hierarchy, including a free unit cell placement area and a unit cell placement area for the hierarchy block Set the placement area to the chip area,
Place and route using the unit cell placement area in the peripheral area surrounding the hierarchical block placement area in the chip area and the empty unit cell placement area in the hierarchical block placement area;
A layout design method characterized by that. The layout design apparatus comprises:
In a hierarchy below the upper hierarchy,
The empty unit cell arrangement area in the hierarchical block arrangement area arranged in the chip area is set as an arrangement prohibition area, and the arrangement and wiring of the hierarchical block is performed.
The layout design method according to claim 1, wherein: The hierarchical block arrangement area includes a plurality of empty unit cell arrangement areas, and the plurality of empty unit cell arrangement areas are set in a lattice shape in the hierarchical block arrangement area.
3. The layout design method according to claim 1 or 2, wherein The hierarchical block arrangement area includes a plurality of empty unit cell arrangement areas, and the plurality of empty unit cell arrangement areas are set at regular intervals from one end of the hierarchical block arrangement area to the other opposite end. ,
The layout design method according to claim 1, wherein: On the computer,
In the upper hierarchy in the hierarchical layout design that performs layout design of semiconductor integrated circuits by hierarchy,
A hierarchical block having a hierarchical block having a predetermined function for performing placement and routing in a hierarchy below the upper hierarchy, including a free unit cell placement area and a unit cell placement area for the hierarchy block Set the placement area to the chip area,
Place and route using the unit cell placement area in the peripheral area surrounding the hierarchical block placement area in the chip area and the empty unit cell placement area in the hierarchical block placement area,
A layout design program characterized by causing processing to be executed.

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