JP2000260949A - Semiconductor device and semiconductor designing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a design period even when using a hard-macro, by mounting a hard-micro which comprises a buffer independent of an intrinsic function as well as an external terminal for the buffer independent of an intrinsic external terminal for using that function. SOLUTION: A semiconductor device 10 comprises a hard-macro 12 which comprises a specified function as well as an external terminal for using it. The hard-macro 12 comprises a plurality of buffers 14 entirely independent of the function, while an input terminal and output terminal of the buffer 14 are formed as an external terminal entirely independent of the external terminal for using the intrinsic function of the hard-macro 12. So, with the buffer 14 used as a repeater for wiring driving, only a completion of layout design allows first detection at a validation step for operation timing. Thus, the problem of wiring delay error occurring at a wiring 16 is settled in a short time, enabling to reduce design period for the semiconductor device 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a semiconductor design apparatus capable of shortening a design period.

[0002]

2. Description of the Related Art At present, many semiconductor devices are equipped with hard macros such as RAMs and ROMs as the size of semiconductor devices increases. However, when the area occupied by the hard macro in the semiconductor chip increases, the length of wiring to be connected across the hard macro increases, and the delay time becomes a problem. For example, as shown in FIG. 2, a wiring 28 from a primitive cell 24 such as a logic circuit other than the hard macro 22 to an I / O cell 26 serving as an external terminal of the semiconductor device 20 may be very long.

On the other hand, conventionally, in the middle of the wiring 28,
In other words, a wiring delay is reduced by adding a normal buffer (repeater) as a relay point for driving the wiring 28 between the areas where the hard macros 22 are arranged.

In this case, in a conventional semiconductor device, as shown in FIG. 3, an arrangement column (generally, a logic circuit) that can be recognized by an automatic arrangement and wiring tool is arranged between regions where hard macros 22 are arranged. , ROW (row)) are newly provided or provided in advance, and a necessary number of additional buffers 32 are arranged in the arrangement row 30, and power is supplied to these additional buffers 32. Power supply line VDD and ground line VSS,
The wiring connection was redone.

[0005] However, the work of providing such a new arrangement column area or connecting wiring for supplying power to an additional buffer is particularly difficult for an ASIC (application limited I / O).
In a design form requiring a short TAT (design period), such as C), this is a serious problem. Further, depending on the arrangement of the hard macros, the arrangement columns cannot be provided, or even if the arrangement columns can be provided, the arrangement of the hard macros must be changed due to a problem in operation timing. .

On the other hand, it is possible to provide an arrangement column in advance around a hard macro. But,
Since the configuration of the arrangement row changes according to the type and arrangement of the hard macros, the number of work steps increases accordingly. In addition, when the arrangement of the hard macros is changed, the arrangement columns must be redesigned in consideration of the influence, so in the conventional semiconductor device using the hard macros,
There is a problem that the number of design steps increases.

[0007]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a semiconductor design apparatus capable of shortening the design period even when a hard macro is used, in view of the problems based on the prior art. Is to provide.

[0008]

In order to achieve the above object, the present invention provides a semiconductor device having a predetermined function and a hard macro having an external terminal for using the function. The macro includes at least one buffer independent of a function of the hard macro, and an input terminal and an output terminal of the buffer are connected to an external terminal of the hard macro independent of an external terminal for using the function of the hard macro. A semiconductor device characterized by being formed as a terminal is provided. Here, the external terminal of the hard macro means a terminal for connecting to a circuit other than the hard macro, an I / O cell, or the like in the semiconductor device.

Further, the present invention provides a means for generating a hard macro according to claim 1, a means for generating a netlist of a semiconductor device according to claim 1 including the hard macro, and the generated net. Means for arranging and routing the layout of the semiconductor device using a list to generate a layout pattern; means for analyzing operation timing of the semiconductor device based on the layout and wiring information of the layout pattern after layout; Means for detecting a wiring passing around the macro and having an error in the operation timing, and a buffer for detecting the position of a buffer included in the hard macro and optimizing the operation timing of the wiring Means for detecting the connection, and reconnecting the wiring via the detected buffer. Means for updating the list, and is intended to provide a semiconductor design apparatus characterized by having means for correcting the layout pattern.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device and a semiconductor designing apparatus according to the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.

FIG. 1 is a conceptual diagram of one embodiment of a semiconductor device according to the present invention. The illustrated semiconductor device 10 has, for example, RA
A hard macro 1 such as an M or a ROM having a predetermined function and an external terminal for using the function.
2 By inputting, for example, the size, the aspect ratio, and the like of the hard macro 12 as a parameter by a generator, which is one of the semiconductor design devices, a layout pattern corresponding to the parameter is automatically generated.

As shown in FIG. 1, the hard macro 12
It has a plurality of buffers 14 completely independent of its function, and the input terminal and output terminal of each buffer 14 are hard macro 12 completely independent of external terminals for using the original functions of the hard macro 12. Are formed as external terminals. That is, the hard macro 12 includes
An external terminal for using the original function of the hard macro 12 and an external terminal for using the buffer 14 are provided independently of each other.

In the semiconductor device 10 of the present invention, a buffer 14 independent of the original function of the hard macro 12 is incorporated in the hard macro 12. Therefore, by using the buffer 14 as a repeater for driving the wiring, the wiring generated on the wiring 16 passing around the hard macro 12 can be detected for the first time in the operation timing verification stage after the layout design is completed. The delay error can be solved in a short time, and the design period of the semiconductor device 10 can be shortened.

The hard macro mounted on the semiconductor device of the present invention is not limited to the one automatically generated by the generator. For example, a hard macro custom-designed for a CPU core, an analog circuit, or the like, It may be a macro. Also, the buffer serving as a repeater is preferably arranged in the peripheral portion of the hard macro 12 if the wiring cannot pass over the hard macro 12, but if the wiring can pass over the hard macro 12, It may be arranged at any position.

Next, a semiconductor design apparatus according to the present invention will be described. The semiconductor design device of the present invention is basically a software program such as a CAD tool that operates on hardware such as a workstation. However, the semiconductor design device of the present invention is not limited to a specific hardware configuration or software program at all, and may use other means for realizing the operation of the semiconductor design device of the present invention described below. It is feasible.

Hereinafter, a procedure for designing a semiconductor device of the present invention using the semiconductor designing apparatus of the present invention will be described.

First, as a step 1, a necessary hard macro such as a RAM is generated by using the aforementioned generator. Then, as a step 2, a netlist of the entire semiconductor device is created by performing logic design other than the hard macro together. Using the netlist, the layout of the semiconductor device is arranged and routed using an automatic placement and routing tool, and a layout pattern corresponding to the netlist is generated.

After the layout is completed, as step 3,
From the arrangement information of the hard macro on the semiconductor chip and the information of the external terminal of the hard macro itself, the position of the buffer incorporated in the hard macro, that is, the hard macro is formed corresponding to each buffer. The position of the external terminal is extracted and stored. Step 4
Then, a wiring passing around the hard macro is extracted from the layout wiring information of the layout pattern and stored.

Thereafter, in step 5, information on RC (resistance component and capacitance component) is extracted from the layout and wiring information of the layout pattern, delay calculation is performed based thereon, and operation timing is analyzed based on the delay calculation. I do. As a result, in step 6, it is searched whether or not the wiring causing the error includes the wiring passing around the hard macro stored in step 4, and the corresponding wiring is selected.

In step 7, among the buffers that can be used as repeaters in the hard macro stored in step 3, the buffer closest to the route of the wiring causing the timing error in step 6 can be used. , And the most suitable one is adopted as the repeater. At this time, one buffer is not necessarily used for one wiring, and a necessary number of buffers may be used as needed. The input terminals of the unused buffers are connected to the ground or the power supply.

Subsequently, in step 8, the netlist information is updated so that the erroneous wiring is reconnected via the buffer employed in step 7. Then, the wiring on the layout is redone in the same manner as the updated netlist information. Finally, in step 9, for the wires other than the wires that can be corrected as described above, the buffers are arranged in the existing arrangement row as before, and the buffers are modified by using them as repeaters.

In the above embodiment, the buffer is arranged at the periphery of the hard macro on the assumption that the wiring cannot pass over the hard macro. However, the present invention is not limited to this. If the wiring can pass over the hard macro in accordance with the above, the buffer may be arranged at an arbitrary position of the hard macro. In this case, the external terminals of the buffer may be appropriately changed as necessary, such as forming the external terminal from one side to the other side opposite thereto, or providing a plurality of external terminals for one buffer.

The semiconductor device and the semiconductor design device of the present invention are basically as described above. As described above, the semiconductor device and the semiconductor design device of the present invention have been described in detail. However, the present invention is not limited to the above embodiment, and various improvements and modifications may be made without departing from the gist of the present invention. Of course.

[0024]

As described in detail above, the semiconductor device of the present invention includes a buffer independent of its original function, and is provided with a buffer independent of an original external terminal for using the function. A hard macro having an external terminal is mounted. Further, the semiconductor design device of the present invention generates a layout pattern from the netlist of the semiconductor device of the present invention, analyzes the operation timing of the semiconductor device based on the layout and wiring information of the layout pattern after layout, and executes A wiring with an operation timing error is detected from the wirings passing through the periphery, and a buffer with the optimum wiring operation timing is detected from buffers included in the hard macro, and the buffer through the buffer is detected. The netlist is updated and the layout pattern is corrected so that the wiring is connected again. Therefore, according to the semiconductor device and the semiconductor design device of the present invention, even when a hard macro occupying a relatively large layout area is mounted, a wiring delay error of a wiring to be connected across the hard macro can be reduced for a short time. Settled,
The design period can be significantly reduced. Further, according to the semiconductor device and the semiconductor design device of the present invention, since a buffer serving as a repeater is mounted inside the hard macro, even if the arrangement of the hard macro is redone, the subsequent Can be performed in a short time.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram of one embodiment of a semiconductor device of the present invention.

FIG. 2 is a conceptual diagram of an example of a semiconductor device.

FIG. 3 is a conceptual diagram of an example of an arrangement column.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Semiconductor device 12 Hard macro 14 Buffer 16, 28 Wiring 20 Semiconductor device 22 Hard macro 24 Primitive cell 26 I / O cell 30 Arrangement column 32 Buffer VDD Power supply line VSS Ground line

Claims (2)

[Claims] 1. A semiconductor device comprising a hard macro having a predetermined function and an external terminal for using the function, wherein the hard macro is at least one buffer independent of the function of the hard macro. And an input terminal and an output terminal of the buffer are formed as external terminals of the hard macro independent of external terminals for using the function of the hard macro. 2. A means for generating the hard macro according to claim 1, means for generating a netlist of the semiconductor device according to claim 1 including the hard macro, and using the generated netlist. Means for performing layout and wiring of the layout of the semiconductor device to generate a layout pattern; means for analyzing operation timing of the semiconductor device based on layout and wiring information of the layout pattern after layout; Passed, and
Means for detecting a wiring having an error in the operation timing, and means for detecting a buffer position included in the hard macro and detecting a buffer having an optimum operation timing of the wiring; A semiconductor design apparatus comprising: means for updating the netlist so as to reconnect the wiring via the buffer; and means for correcting the layout pattern.