JP5625921B2 - Circuit design support program, circuit design support method, and circuit design support apparatus - Google Patents

Description

  The present invention relates to a circuit design support program, a circuit design support method, and a circuit design support apparatus.

  When deciding the mounting position and drilling position of a component, and examining whether the substrate will be warped, the characteristics of the printed circuit board are equivalent. There is known a technique of converting into a physical property value and performing a simulation by a finite element method. For example, when the coefficient of thermal expansion is considered as a physical property value, a technique for determining a mounting position of a component based on a region where the substrate expands and a region where the substrate does not expand is known.

  For example, a method is known in which the region where the substrate expands and the region where the substrate does not expand are identified by calculating the ratio of copper present in each region from the arrangement of copper wirings on the substrate. In addition, a method is known in which the wiring direction of the copper wiring in the plane of each layer is considered in consideration.

JP 2007-80111 A

  In order to calculate an equivalent physical property value with high accuracy, a simulation with a large amount of calculation such as finite element analysis is executed. On the other hand, for example, in Patent Document 1, a wiring pattern is registered in advance, and a physical property equivalent value for the registered wiring pattern is calculated, thereby reducing calculation cost.

  However, this method has a problem that it takes time for the simulation because a simulation is separately performed when there is no match with the registered wiring pattern.

  The present invention has been made in view of these points, and an object of the present invention is to provide a circuit design support program, a circuit design support method, and a circuit design support device that calculate an equivalent property value with a small amount of calculation.

In order to achieve the above object, a disclosed circuit design support program is provided. This program causes a computer to execute the following processing.
A substrate model to be processed is divided into a plurality of cells. An indicator of the effect that the wiring provided in each cell has on the board model in at least one direction on the plane of the board model is the ratio of the wiring occupying each cell and the continuity of the wiring of the cell in the aforementioned direction. It is calculated based on the parameter indicating An equivalent physical property value of the wiring is calculated based on the calculated index. The calculated equivalent property value is output to the display device.

  The printed circuit board finite element method simulation considering the influence of the wiring pattern can be performed at high speed.

1 is a diagram illustrating a circuit design support apparatus according to a first embodiment. It is a figure which shows one structural example of the hardware of the circuit design assistance apparatus of 2nd Embodiment. It is a block diagram which shows the function of the circuit design support apparatus of 2nd Embodiment. It is a figure which shows an example of a board | substrate model. It is a figure explaining reception of the input of the material physical property value for every layer. It is a figure explaining an equivalent property value parameter input screen. It is a figure explaining the calculation result of a remaining copper rate calculation part. It is a figure explaining an equivalent property value parameter input screen. It is a figure explaining the compound rule calculation in a plane. It is a figure explaining calculation of the equivalent physical property value included to the thickness direction. It is a block diagram which shows the function which a remaining copper ratio calculation part has. It is a figure explaining a cell. It is a figure explaining the calculation method of various parameters. It is a figure explaining the calculation method of various parameters. It is a figure explaining the calculation method of various parameters. It is a figure explaining the calculation method of various parameters. It is a figure explaining the calculation method of various parameters. It is a figure explaining the process of a contribution calculation part. It is a flowchart which shows the process of a remaining copper ratio calculation part.

Hereinafter, a circuit design support apparatus according to an embodiment will be described in detail with reference to the drawings.
First, the circuit design support apparatus according to the embodiment will be described, and then the embodiment will be described more specifically.

<First Embodiment>
FIG. 1 is a diagram illustrating a circuit design support apparatus according to the first embodiment.
The circuit design support apparatus (computer) 1 according to the first embodiment includes a board model information storage unit 1a, a wiring information storage unit 1b, a division unit 1c, an index calculation unit 1d, and an equivalent property value calculation unit 1e. And an output unit 1f.

  The substrate model information storage unit 1a stores a substrate model for which an equivalent property value is calculated. This substrate model may be a single layer substrate or a multilayer substrate. A substrate model 2 shown in FIG. 1 is a multilayer substrate, and FIG. 1 shows one of them.

  In the wiring information storage unit 1b, information on wiring to be performed on the board model 2 is stored. In FIG. 1, the wiring 3 performed on one layer of the substrate model 2 is shown. In FIG. 1, the board model information storage unit 1 a and the wiring information storage unit 1 b are provided in the circuit design support apparatus 1. However, either one or both of the board model information storage unit 1a and the wiring information storage unit 1b may be provided outside the circuit design support device 1.

  The dividing unit 1c divides the substrate model 2 into a plurality of cells. In FIG. 1, cells 4a to 4f obtained by dividing the substrate model 2 into six are indicated by dotted lines. Here, the lengths of the sides of the cells 4a to 4f are preferably determined based on the width of the wiring 3 (pen width). For example, the length of the sides of the cells 4a to 4f can be set to a slightly smaller value (for example, 90%) of the pen width of the wiring 3. By setting it to 90%, it is possible to achieve a balance between the processing speed and the analysis accuracy.

  Hereinafter, for convenience of explanation, an X axis and a Y axis that are orthogonal to each other are defined. It is assumed that the X axis is provided in parallel with the horizontal side of the substrate model 2 in FIG. 1 and the Y axis is provided in parallel with the vertical side of the substrate model 2.

  The index calculation unit 1 d calculates an index indicating the influence that the wiring 3 provided in the cells 4 a to 4 f has on the substrate model 2 in the X-axis direction and the Y-axis direction on the plane of the substrate model 2. Specifically, the index calculating unit 1d determines the proportion of the wiring 3 in each of the cells 4a to 4f (hereinafter referred to as “wiring remaining ratio”) and the continuity of the wiring of the cells in the X-axis direction and the Y-axis direction. An index is calculated based on the parameter indicating. Here, the wiring remaining rate can be determined based on, for example, the presence or absence of the wiring 3 existing at each vertex of the cells 4a to 4f. For example, in the case of 0, the ratio is 0. In the case of one, the ratio is 0.25. In the case of two, the ratio is 0.5. In the case of three, the ratio is 0.75. In the case of four, the ratio is 1.0. In addition, the index calculation part 1d can calculate a wiring residual ratio easily by making the presence or absence of the wiring in each vertex into a wiring residual ratio. FIG. 1 shows a table T indicating the wiring remaining rate of each cell. The table # 4a corresponds to the cell 4a. Similarly, the tables # 4b, # 4c, # 4d, # 4e, and # 4f correspond to the cells 4b, 4c, 4d, 4e, and 4f, respectively.

  A wiring 3 exists at each of the vertices P1, P2, P5, and P6 of the cell 4a. For this reason, the ratio of the cells 4a is set to 1.0 (100%). Moreover, the wiring 3 exists in each of the vertices P2 and P6 of the cell 4b, and the wiring 3 does not exist in each of the vertices P3 and P7. For this reason, the ratio of the cell 4b is set to 0.5 (50%). For the cells 4c to 4f, the ratio can be obtained in the same manner as the cells 4a and 4b.

The parameter indicating the continuity of the cell wiring in the above-described direction can be obtained based on the presence / absence of the wiring at each vertex of the adjacent cell, for example.
Then, the index calculation unit 1d determines a first parameter according to the number of wirings present at the vertices connected by the sides parallel to the X-axis direction of each of the cells 4a to 4f. When the number of wirings existing at the vertices connected by the sides parallel to the X-axis direction is zero, the first parameter is determined to be zero. In the case of one, the first parameter is determined to be 50. In the case of two, the first parameter is determined to be 100. The index calculation unit 1d calculates the first parameter for each of two sides parallel to the X-axis direction of one cell. Then, the index calculation unit 1d determines the larger one of the obtained first parameters as a parameter indicating the continuity of the cell in the X-axis direction (hereinafter referred to as X parameter). Note that by calculating a parameter indicating continuity based on the number of wirings present at the apex, the index calculating unit 1d can easily calculate a parameter indicating continuity.

  For example, since the wiring 3 exists at both the vertices P1 and P2 connected by the lower side of the cell 4a, the first parameter for the vertices P1 and P2 is set to 100. Since both the vertices P5 and P6 connected by the upper side of the cell 4a have the wiring 3, the first parameter for the vertices P5 and P6 is determined to be 100. The index calculation unit 1d determines that 100 is the X parameter of the cell 4a because all the obtained first parameters are 100.

  As another example, since the wiring 3 exists at the vertex P2 connected by the lower side of the cell 4b and the wiring 3 does not exist at the vertex P3, the first parameter for the vertices P2 and P3 is determined to be 50. . Of the vertices P6 and P7 connected by the upper side of the cell 4a, the wiring 3 exists at the vertex P6 and the wiring 3 does not exist at the vertex P7, so the first parameter for the vertices P6 and P7 is determined to be 50. . Since the calculated first parameters are all 50, the index calculation unit 1d determines 50 as the X parameter of the cell 4b. The X parameters can be obtained for the cells 4c to 4f in the same manner as the cells 4a and 4b.

  Further, the index calculation unit 1d determines that the second parameter is 0 when the number of wirings existing at the vertexes connected by the sides parallel to the Y-axis direction of each cell is zero. In the case of one, the second parameter is determined to be 50. In the case of two, the second parameter is determined to be 100. The index calculation unit 1d calculates the second parameter for each of two sides parallel to the Y-axis direction of one cell. Then, the index calculation unit 1d determines the larger one of the obtained two second parameters as a parameter indicating the continuity of the cell in the Y-axis direction (hereinafter referred to as Y parameter).

  For example, since the wiring 3 exists at each of the vertices P1 and P5 connected by the left side of each cell 4a, the second parameter for the vertices P1 and P5 is determined to be 100. Since both the vertices P2 and P6 connected by the right side of the cell 4a have the wiring 3, the second parameter for the vertices P2 and P6 is determined to be 100. Since the calculated second parameters are all 100, the index calculation unit 1d determines 100 as the Y parameter of the cell 4a.

  As another example, since the wiring 3 exists at the vertices P2 and P6 connected by the left side of the cell 4b, the second parameter for the vertices P2 and P6 is determined to be 100. Since neither of the vertices P3 and P7 connected by the right side of the cell 4b has the wiring 3, the second parameter for the vertices P3 and P7 is determined to be zero. The index calculation unit 1d determines the larger 100 of the two obtained second parameters as the Y parameter of the cell 4b. For the cells 4c to 4f, the Y parameter can be obtained in the same manner as the cells 4a and 4b. FIG. 1 illustrates the wiring remaining ratio, the X parameter, and the Y parameter obtained for each of the cells 4a to 4f. The index calculation unit 1d calculates an index indicating the influence of the wiring 3 on the substrate model 2 in each of the X-axis direction and the Y-axis direction using the wiring remaining rate, the X parameter, and the Y parameter. This index calculation method will be described in detail in the second embodiment.

  The equivalent property value calculation unit 1e calculates an equivalent property value of the wiring based on the index calculated by the index calculation unit 1d. An example of a method for calculating an equivalent property value is given in the second embodiment.

The output unit 1 f outputs the calculated equivalent property value to the display device 5. Further, the output unit 1 f may output the index calculated by the index calculation unit 1 d to the display device 5.
According to this circuit design support device 1, the index calculation unit 1 d uses the wiring remaining rate, the X parameter, and the Y parameter to indicate the influence of the wiring 3 on the board model 2 in each of the X axis direction and the Y axis direction. Was calculated. Then, the equivalent property value calculation unit 1e calculates the equivalent property value of the wiring based on the index calculated by the index calculation unit 1d. Therefore, the equivalent physical property value can be calculated without performing a process such as preparing a pattern that matches the wiring pattern in the database in advance. Also, the equivalent physical property value of the wiring is calculated using the X parameter and the Y parameter indicating the continuity of the cell wiring in the X-axis direction and the Y-axis direction. Therefore, the accuracy of simulation can be increased. In addition, the equivalent physical property values of the cells 4a to 4f can be quickly calculated in consideration of the influence of the wiring direction as compared with the case where the equivalent physical property values are calculated by directly performing a finite analysis method or the like.

  The dividing unit 1c, the index calculating unit 1d, the equivalent property value calculating unit 1e, and the output unit 1f can be realized by functions provided in a CPU (Central Processing Unit) included in the circuit design support apparatus 1. The board model information storage unit 1a and the wiring information storage unit 1b can be realized by a data storage area provided in a RAM (Random Access Memory), a hard disk drive (HDD), or the like included in the circuit design support device 1. it can.

Hereinafter, the embodiment will be described more specifically.
<Second Embodiment>
FIG. 2 is a diagram illustrating a configuration example of hardware of the circuit design support device according to the second embodiment.

The entire circuit design support apparatus 10 is controlled by the CPU 101. The CPU 101 is connected to the RAM 102 and a plurality of peripheral devices via the bus 108.
The RAM 102 is used as a main storage device of the circuit design support apparatus 10. The RAM 102 temporarily stores at least part of an OS (Operating System) program and application programs to be executed by the CPU 101. The RAM 102 stores various data used for processing by the CPU 101.

  Peripheral devices connected to the bus 108 include a hard disk drive 103, a graphic processing device 104, an input interface 105, a drive device 106, and a communication interface 107.

  The hard disk drive 103 magnetically writes data to and reads data from a built-in disk. The hard disk drive 103 is used as a secondary storage device of the circuit design support apparatus 10. The hard disk drive 103 stores an OS program, application programs, and various data. As the secondary storage device, a semiconductor storage device such as a flash memory can be used.

  A monitor 104 a is connected to the graphic processing device 104. The graphic processing device 104 displays an image on the screen of the monitor 104a in accordance with a command from the CPU 101. Examples of the monitor 104a include a liquid crystal display device using a CRT (Cathode Ray Tube).

  A keyboard 105 a and a mouse 105 b are connected to the input interface 105. The input interface 105 transmits signals sent from the keyboard 105a and the mouse 105b to the CPU 101. Note that the mouse 105b is an example of a pointing device, and other pointing devices can also be used. Examples of other pointing devices include a touch panel, a tablet, a touch pad, and a trackball.

  The drive device 106 reads data recorded on a portable recording medium such as an optical disc on which data is recorded so as to be readable by reflection of light or a USB (Universal Serial Bus) memory. For example, when the drive device 106 is an optical drive device, data recorded on the optical disc 200 is read using a laser beam or the like. Examples of the optical disc 200 include Blu-ray (registered trademark), DVD (Digital Versatile Disc), DVD-RAM, CD-ROM (Compact Disc Read Only Memory), CD-R (Recordable) / RW (ReWritable), and the like. .

  The communication interface 107 is connected to the network 50. The communication interface 107 transmits and receives data to and from other computers or communication devices via the network 50.

With the hardware configuration as described above, the processing functions of the present embodiment can be realized.
The following functions are provided in the circuit design support apparatus 10 having such a hardware configuration.

FIG. 3 is a block diagram illustrating functions of the circuit design support apparatus according to the second embodiment.
The gerber data storage unit 20 stores gerber data indicating the location of wiring of each layer included in the board model to be designed. 3 shows the case where the Gerber data storage unit 20 is provided outside the circuit design support device 10, the circuit design support device 10 may have a Gerber data storage unit 20.

The circuit design support apparatus 10 includes an analysis unit 11 that performs thermal strain analysis of a board model to be analyzed.
The analysis unit 11 includes a display unit 14 that displays, on the monitor 104a, an input screen of various conditions for the board model to be analyzed by the designer in thermal strain analysis.

  The analysis unit 11 also receives input of various conditions for the board model to be analyzed by the designer. Moreover, the analysis part 11 reads the Gerber data stored in the Gerber data storage part 20 by a designer's instruction | indication. Then, based on the accepted conditions, the analysis unit 11 calculates the ratio of copper wiring remaining in the entire board model (hereinafter referred to as “average remaining copper ratio”) and the degree of contribution in the remaining copper ratio calculation unit 12. . Further, when a specific region on the board specified by the designer exists, the analysis unit 11 can also calculate the average remaining copper ratio and the contribution degree for the region. Here, the degree of contribution is an index indicating the influence of wiring provided in each cell described later on the board model in at least one direction on the plane of the board model.

  Thereafter, the analysis unit 11 calculates an equivalent physical property value in the equivalent physical property value calculation unit 13 based on the average remaining copper rate and the contribution degree calculated by the remaining copper rate calculation unit 12. The analysis unit 11 can also display the average remaining copper rate and contribution calculated by the remaining copper rate calculating unit 12 and the equivalent physical property value calculated by the equivalent physical property value calculating unit 13 on the monitor 104a on the display unit 14. .

  Thereafter, the analysis unit 11 performs thermal strain analysis based on the calculated equivalent physical property value. Hereinafter, an example of the analysis procedure will be described by dividing it into nine steps. Each process is set for convenience of explanation, and the number of processes and the separation of processes are not limited to those in the present embodiment. Also, some processes may be omitted, some processes may be replaced with other processes, or other processes may be added.

  [Step 1] By the operation of the designer, the analysis unit 11 reads a file in which outline information of a board model to be analyzed on which a plurality of electronic components (for example, BGA (Ball Grid Array)) are mounted is stored. Examples of the file include an IDF file (an intermediate file developed in order to make the data of the three-dimensional CAD and the PCB design CAD compatible). Then, the analysis unit 11 displays the outline of the substrate model of the read file on the monitor 104a. The analysis unit 11 stores the read file in a board outline information storage unit described later.

FIG. 4 is a diagram illustrating an example of the substrate model.
FIG. 4 shows the board model 30 displayed on the monitor 104a. The substrate model 30 has a plurality of IC (Integrated Circuit) component models 31, 32, and 33 mounted thereon. Hereinafter, for convenience of explanation, an X axis and a Y axis that are orthogonal to each other are defined. The X axis is provided in parallel with one side of the substrate model 30 in FIG. 4, and the Y axis is provided in parallel with the other side of the substrate model 30.

  [Step 2] When the designer designates a component model to be evaluated from among a plurality of electronic components mounted on the board model 30, the analysis unit 11 identifies the component model to be evaluated. Hereinafter, a case where the analysis unit 11 specifies the IC component model 31 will be described.

  The analysis unit 11 determines the mold size, chip size, chip layout (offset amount from the center of the component), interposer thickness, solder bump height, solder bump diameter, land height, X axis of the specified IC component model 31. An input screen for various parameters such as the direction, the number of solder bumps in the Y-axis direction, and the pitch of the solder bumps is displayed on the monitor 104a. And the analysis part 11 receives the input of the various parameters by a designer's operation. And the analysis part 11 produces the mesh of the IC component model 31 based on the received parameter. In addition, the analysis unit 11 stores the received parameters and the created mesh in an evaluation IC area storage unit to be described later.

[Step 3] The analysis unit 11 accepts selection of the shape of the board model 30 by the operation of the designer.
[Step 4] The analysis unit 11 displays an input screen of the layer configuration (the number of layers of substrates) of the substrate model 30 on the monitor 104a. And the analysis part 11 receives the input of the layer structure of the board | substrate model 30 by a designer's operation. Moreover, the analysis part 11 receives the input of the material of a conductor layer, and the material of a resin layer. Further, the analysis unit 11 can also accept an input such as whether or not the surface layer of the board model 30 is a conductor layer.

  [Step 5] The analysis unit 11 displays an input screen of material property values for each layer of the substrate model 30 on the monitor 104a. And the analysis part 11 receives the input of the material physical property value for every layer of the board | substrate model 30 by a designer's operation.

FIG. 5 is a diagram for explaining acceptance of input of material property values for each layer.
The monitor 104a shown in FIG. 5 includes a board model name: sample1. A table T1 for accepting input of material property values for each layer of brd is displayed. The table T1 includes columns for layer configuration, material name, DB selection, Young's modulus, Poisson's ratio, and thermal expansion coefficient. Information arranged in the horizontal direction is associated with each other.

  In the column of the layer configuration, information for identifying the layer configuration is set. L1, L2, L3, and L4 are information for identifying the conductor layers of each layer. For example, L1 indicates the first conductor layer. PP1, PP2, and PP3 are information for identifying the resin layers of the respective layers. For example, PP1 indicates the first resin layer.

  In the DB selection column, a selection button B1 for calling a database storing Young's modulus, Poisson's ratio, and thermal expansion coefficient based on the material set in the material name column is arranged. When the designer presses the selection button B1, the analysis unit 11 calls a database (not shown) and displays a material data selection screen on the monitor 104a. When the designer selects material data, the analysis unit 11 sets the material name, Young's modulus, Poisson's ratio, and thermal expansion coefficient in the table T1. The designer can also manually input the material name, Young's modulus, Poisson's ratio, and thermal expansion coefficient.

[Step 6] When the designer presses the lower right button B2 of the monitor 104a, the analysis unit 11 displays an equivalent property value parameter input screen on the monitor 104a.
FIG. 6 is a diagram for explaining an equivalent property value parameter input screen.

  The monitor 104a shown in FIG. 6 includes a board model name: sample1. A table T2 that accepts input of equivalent physical property value parameters for each layer of the brd is displayed. The table T2 includes columns of layer configuration, material name, thickness, Gerber selection, average remaining copper ratio, and average remaining copper ratio (parts). Information arranged in the horizontal direction is associated with each other.

In the column of the layer configuration and material name, the same information as that set in the table T1 is set.
In the thickness column, the thickness value of each layer is set by the designer.

In the Gerber selection column, a selection button B3 for calling a database storing Young's modulus, Poisson's ratio, and thermal expansion coefficient based on the material set in the material name column is arranged.
In the column of the average remaining copper ratio, the average remaining copper ratio of the entire board model 30 calculated by the remaining copper ratio calculating unit 12 is set.

  In the column of the average remaining copper ratio (components), the average remaining copper ratio of the IC component model 31 calculated by the remaining copper ratio calculating unit 12 is set. In FIG. 6, one average remaining copper ratio (component) column is provided, but the average remaining copper ratio (component) column is provided according to the number of IC component models selected in step 2.

  In addition, as shown in FIG. 6, the column of an average remaining copper ratio and an average remaining copper ratio (components) is initially blank. When the designer presses the selection button B3, the analysis unit 11 calls the Gerber data storage unit 20 shown in FIG. 3, and displays a Gerber data selection screen (not shown) on the monitor 104a.

  [Step 7] When the analysis unit 11 receives selection of Gerber data by the designer's operation, the remaining copper ratio calculation unit 12 is activated. The remaining copper ratio calculation unit 12 calculates the average remaining copper ratio of the entire selected layer and the average remaining copper ratio around the IC component model 31 received in step 2. In addition, the remaining copper ratio calculation unit 12 calculates the average X-axis direction contribution and the average Y-axis direction contribution taking into consideration the entire selected layer and the wiring direction of the copper wiring of the IC component model 31 received in step 2. To do. A method for calculating the average remaining copper ratio, the average X-axis direction contribution, and the average Y-axis direction contribution will be described in detail later.

  And the remaining copper ratio calculation part 12 sets the calculated average remaining copper ratio in the column of the average remaining copper ratio of Table T2, and calculates the average remaining copper ratio of the IC component model 31 in the column of an average remaining copper ratio (components). Set to. The analysis unit 11 displays this table T2 on the monitor 104a.

FIG. 7 is a diagram illustrating a calculation result of the remaining copper ratio calculation unit.
The monitor 104a displays a substrate layer selection tab TB1, a table T3, and a button B4.

  The designer clicks the board layer selection tab TB1, and selects the board model 30 layer (board layer) that displays the average remaining copper ratio, the average X-axis direction contribution, and the average Y-axis direction contribution on the monitor 104a. can do.

  When the analysis unit 11 receives the selection of the board layer selection tab TB1 by the designer, the analysis unit 11 obtains a table T3 in which the average remaining copper ratio, the average X-axis direction contribution, and the average Y-axis direction contribution of the selected board layer are described. It is displayed on the monitor 104a. FIG. 7 shows a table T3 indicating the average remaining copper ratio, average X-axis direction contribution, and average Y-axis direction contribution of the substrate layer L1 selected by the designer. In the table T3, a region area, an average remaining copper ratio, an average contribution in the X-axis direction, and an average contribution in the Y-axis direction are set for each of the substrate model 30 and the IC component model 31. In FIG. 7, the columns of the evaluation IC area 2 and the evaluation IC area 3 are blank.

When the designer presses the lower right button B4 of the monitor 104a, the analysis unit 11 displays the equivalent property value parameter input screen on the monitor 104a again.
FIG. 8 is a diagram for explaining an equivalent property value parameter input screen.

A table T2 and a button B5 are displayed on the monitor 104a.
The average remaining copper ratio of the board model 30 calculated by the remaining copper ratio calculating unit 12 is set in the column of the average remaining copper ratio of the table T2 displayed on the monitor 104a shown in FIG. Further, the average remaining copper ratio of the IC component model 31 calculated by the remaining copper ratio calculating unit 12 is set in the column of the average remaining copper ratio of the table T2.

  [Step 8] When the designer presses the lower right button B5 of the monitor 104a, the analysis unit 11 converts the board outline information input in step 1 and the evaluation IC area information input in step 2 into the information. Based on this, a substrate mesh is created. In creating the substrate mesh, the analysis unit 11 performs mesh division of the shape and separately activates the equivalent property value calculation unit 13 to calculate the equivalent property value of the substrate model 30 on which the wiring is performed.

  The equivalent physical property value calculation unit 13 calculates the thickness of each layer input in step 6, the basic material physical property value input in step 5, the average remaining copper ratio calculated in step 7, and the average contribution in the X-axis direction. Based on the average contribution in the Y-axis direction, an equivalent physical property value with directivity in the X-axis direction and the Y-axis direction is calculated. Then, the equivalent property value calculation unit 13 assigns a calculation result to the created element. To calculate the equivalent physical property value, first, the Young's modulus, the Poisson's ratio, and the thermal expansion coefficient for each layer taking into account the average contribution in the X-axis direction and the average contribution in the Y-axis direction are calculated (in-plane compound rule). Then, an equivalent physical property value including the thickness direction (Z-axis direction) is calculated according to the composite law of the laminated material. The analysis unit 11 displays the calculated equivalent physical property value on the monitor 104a. Hereinafter, an example of a method for calculating the equivalent property value will be described.

FIG. 9 is a diagram for explaining in-plane compound rule calculation.
Each parameter when two materials (copper wiring and resin in FIG. 9) exist in one layer of the substrate model 30 is defined as shown in FIG. The Z-axis direction is a method that is orthogonal to the X-axis direction and the Y-axis direction. In FIG. 9, the parameters on the base end side of the arrows are parameters input to the calculation formula, and the parameters on the front end side indicate calculation results. When the original material property value is isotropic, the values of parameters in the X-axis direction, the Y-axis direction, and the Z-axis direction are the same for the Young's modulus, Poisson's ratio, and thermal expansion coefficient.

  As described above, the equivalent property value calculation unit 13 calculates the equivalent property value for each layer. Young's modulus in the X-axis direction is E3x = E1x × KX + E2x × (1−KX). Y-axis direction Young's modulus E3y = E1y × KY + E2y × (1−KY). The Young's modulus in the Z-axis direction is E3z = E1z × ZAN + E2z × (1−ZAN).

  The Poisson's ratio in the X-axis direction is ν3x = ν1x × KX + ν2x × (1−KX). The Poisson's ratio in the Y-axis direction is ν3y = ν1y × KY + ν2y × (1−KY). The Poisson's ratio in the Z-axis direction is ν3z = ν1z × ZAN + ν2z × (1−ZAN).

  The thermal expansion coefficient in the X-axis direction α3x = {(α1x × E1x × KX) + (α2x × E2x × (1−KX))} / E3x. Y-axis direction thermal expansion coefficient α3y = {(α1y × E1y × KY) + (α2y × E2y × (1-KY))} / E3y. The coefficient of thermal expansion in the Z-axis direction is α3z = {(α1z × E1z × ZAN) + (α2z × E2z × (1-ZAN))} / E3z.

  Next, the equivalent property value calculation unit 13 calculates the equivalent property value including the thickness direction according to the composite law of the laminated material. The analysis unit 11 displays the equivalent physical property value including the calculated thickness direction on the monitor 104a.

  FIG. 10 is a diagram for explaining calculation of equivalent physical property values including the thickness direction. The equivalent physical property value obtained for each layer is defined as shown in FIG. In FIG. 10, the parameters on the base end side of the arrows are parameters input to the calculation formula, and the parameters on the front end side indicate calculation results. Further, in FIG. 10, it is assumed that the copper foil layer and the resin layer have already been calculated in a situation where the equivalent physical property values of the single layer have been calculated. The thickness of each layer of the substrate model 30 is set in the plate thickness column. Further, t = t1 + t2 +... + Tn.

Young's modulus including the thickness direction in the X-axis direction Ex = {(E1X × t1 ³ ) + (E2X × ((t1 + t2) ³ −t1 ³ )) +... + (EnX × (t ³ − (t− a ^{tn) 3))} / {} t 3/8}. Young's modulus including the thickness direction in the Y-axis direction Ey = {(E1Y × t1 ³ ) + (E2Y × ((t1 + t2) ³ −t1 ³ )) +... + (EnY × (t ³ − (t− a ^{tn) 3))} / {} t 3/8}. Young's modulus Ez = t / {(t1 / E1Z) + (t2 / E2Z) +... + (Tn / EnZ)} including the thickness direction in the Z-axis direction.

  The Poisson's ratio including the thickness direction in the X-axis direction is νx = ν1X × t1 / t + ν2X × t2 / t +... + ΝnX × tn / t. Poisson's ratio including the thickness direction in the Y-axis direction is νy = ν1Y × t1 / t + ν2Y × t2 / t +... + ΝnY × tn / t. Poisson's ratio including the thickness direction in the Z-axis direction is νz = ν1Z × t1 / t + ν2Z × t2 / t +... + ΝnZ × tn / t.

  Further, the thermal expansion coefficient αx = {(α1X × E1X × t1) + (α2X × E2X × t2) +... + (ΑnX × EnX × tn)} / {(E1X) including the thickness direction in the X-axis direction × t1) + (E2X × t2) +... + (EnX × tn)}. Coefficient of thermal expansion αy = {(α1Y × E1Y × t1) + (α2Y × E2Y × t2) +... + (ΑnY × EnY × tn)} / {(E1Y × t1) ) + (E2Y × t2) +... + (EnY × tn)}. Thermal expansion coefficient αz = {(α1Z × E1Z × t1) + (α2Z × E2Z × t2) +... + (ΑnZ × EnZ × tn)} / {(E1Z × t1) including the thickness direction in the Z-axis direction ) + (E2Z × t2) +... + (EnZ × tn)}.

  [Step 9] Next, the analysis unit 11 performs thermal strain analysis using, for example, a finite element method program. Specifically, the analysis unit 11 adds a temperature load condition to mesh data in which equivalent physical property values are defined. Then, numerical calculation is performed by a finite element method program. The analysis unit 11 displays the result of the thermal strain analysis on the monitor 104a.

  By performing numerical calculation with equivalent physical property values considering the influence (contribution) of the wiring direction, simulation can be performed in a situation closer to the actual machine. Therefore, for example, even when a coarse model with a short calculation time is used, a certain degree of reliability is ensured, so that the simulation time can be shortened.

Hereinafter, the calculation method of the average remaining copper ratio, the average X-axis direction contribution, and the average Y-axis direction contribution will be described in detail.
FIG. 11 is a block diagram illustrating functions of the remaining copper ratio calculation unit.

  The remaining copper ratio calculation unit 12 includes a board outer shape information storage unit 121, an evaluation IC region storage unit 122, a cell size determination unit 123, a parameter calculation unit 124, an average remaining copper ratio calculation unit 125, and a contribution calculation unit. 126.

Here, the cell size determining unit 123 is an example of a dividing unit. The parameter calculation unit 124, the average remaining copper ratio calculation unit 125, and the contribution calculation unit 126 are examples of an index calculation unit.
The board outline information storage unit 121 stores a file in which outline information of the board model 30 read by the analysis unit 11 in step 1 is stored.

The evaluation IC area storage unit 122 stores information on parameters and meshes of the IC component model 31 specified by the analysis unit 11 in step 2.
The cell size determination unit 123 divides each layer of the board model 30 stored in the board outline information storage unit 121 into a plurality of rectangular cells. The cell size determination unit 123 determines the size of the cell to be divided.

FIG. 12 is a diagram illustrating a cell.
An arbitrary region 34 of the board model 30 to be designed shown in FIG. 12 is shown enlarged. In the region 34, a copper foil wiring 35 is provided.

  The cell size determination unit 123 reads the pen (for copper foil coating) width h <b> 1 of the wiring 35 included in the Gerber data stored in the Gerber data storage unit 20. Then, a value obtained by multiplying the read pen width h1 by a predetermined ratio is determined as the width h2 of one side of the cell 36. In the present embodiment, as an example, a value obtained by multiplying the read pen width h1 by 0.9 (90%) is determined as the width h2 of one side of the cell 36. As the cell size increases, the processing time decreases, but the accuracy of thermal strain analysis decreases. The cell size may be set to an arbitrary size by the designer.

The parameter calculation unit 124 calculates various parameters used when calculating the average X-axis direction contribution and the average Y-axis direction contribution.
13 to 17 are diagrams for explaining a method for calculating various parameters. Hereinafter, the direction from the left side to the right side of the paper surface is defined as the positive direction of the X axis, and the direction from the lower side of the paper surface toward the upper side is defined as the positive direction of the Y axis.

  First, the parameter calculation unit 124 sets the four cells 36 in the first row of the region 34 as processing targets. Then, the parameter calculation unit 124 determines whether or not the wiring 35 exists at each of the vertices P12, P13, P14, and P15 existing in the positive direction of the X axis from the vertex P11 set as the base point. Then, the parameter calculation unit 124 sets “1” to the vertex where the wiring 35 exists, and sets “0” to the vertex where the wiring 35 does not exist. Then, the parameter calculation unit 124 creates an array A1 that sequentially stores values set in the positive direction of the X axis. Note that “1” in the array A1 corresponds to the number of rows. The array in the nth row is denoted as “array An”. In FIG. 13, each value of the array A1 is shown enclosed in parentheses. In the example shown in FIG. 13, the array is A1 (1, 1, 0, 0, 0).

  When the creation of the array A1 in the first row is completed, the parameter calculation unit 124 sets the cell 36 in the second row that is moved by one cell 36 in the Y-axis direction as a processing target. Then, an array A2 (1, 1, 0, 0, 0) for the vertices P16, P17, P18, P19, and P20 is created and stored. Similarly, the parameter calculation unit 124 creates and stores an array A3 in the third row and an array A4 in the fourth row.

  Next, the parameter calculation unit 124 responds to combinations of vertex values between adjacent vertices of the array A1, that is, between vertices P11 and P12, between vertices P12 and P13, between vertices P13 and P14, and between vertices P14 and P15. Array B1 is created. This array B1 is information indicating the continuity of the wiring 35 in the X-axis direction. Specifically, the parameter calculation unit 124 sets “0” when the values of the adjacent vertices in the created array A1 are all zero. If any one of the adjacent vertex values is 0, “50” is set. When the values of adjacent vertices are both 1, “100” is set. In FIG. 13, each value of the array B1 is enclosed in {}. In the example shown in FIG. 13, the array is B1 (100, 50, 0, 0, 0).

  The parameter calculation unit 124 associates each value of the created array B1 with the side of the cell 36. For example, the first {100} of the array B1 is associated with the side of the cell 36 between the vertices P11 and P12. The second {50} of the array B1 is associated with the side of the cell 36 between the vertices P12 and P13. Each numerical value of the array B1 corresponds to the first parameter of the first embodiment.

When the creation of the array B1 is completed, the parameter calculation unit 124 creates and stores the arrays B2, B3, and B4 based on the arrays A2, A3, and A4.
Next, the parameter calculation unit 124 compares the continuity of the wiring on the lower side and the upper side of each cell 36 in the first row, and associates the larger one with the cell 36 as information indicating the continuity of the cell 36 in the X-axis direction. Specifically, the parameter calculation unit 124 compares values in each column of the arrays B1 and B2. Then, an array C1 storing the larger value is created. Each numerical value of the array C1 corresponds to the X parameter of the first embodiment. FIG. 14 shows a process for creating the array C1. In FIG. 14, each value of the array C1 is surrounded by []. For example, the first [100] of the created array C1 is associated with the cell 36 surrounded by the vertices P11, P12, P16, and P17. The second [50] of the array C1 is associated with the cell 36 surrounded by the vertices P12, P13, P17, and P18. The parameter calculation unit 124 stores the created array C1 (100, 50, 0, 0).

Further, the parameter calculation unit 124 creates and stores arrays C2, C3, and C4 in the same manner as the array C1.
Next, the parameter calculation unit 124, between vertices adjacent in the Y-axis direction of each cell 36 in the first row, that is, between vertices P11 and P16, between vertices P12 and P17, between vertices P13 and P18, and between vertices P14 and P19. An array D1 corresponding to the combination of the array A1 values of the vertices between the vertices and the vertices P15 and P20 is created. This array D1 is information indicating the continuity of the wiring 35 in the Y-axis direction. FIG. 15 shows a process for creating the array D1. The parameter calculation unit 124 compares the values of the columns of the created arrays A1 and A2. If the corresponding vertex values are all 0, “0” is set. If any one of the corresponding vertex values is 0, “50” is set. If all corresponding vertex values are 1, “100” is set. In the example of FIG. 15, each value of the array D1 is enclosed by <>. The parameter calculation unit 124 stores the created array D1 (100, 100, 0, 0, 0). Each numerical value of the array D1 corresponds to the second parameter of the first embodiment. The parameter calculation unit 124 creates and stores arrays D2, D3, and D4 in the same manner as the array D1.

  Next, the parameter calculation unit 124 compares the continuity of the wiring on the left side and the right side of each cell 36 in the first row, and associates the larger one with the cell 36 as information indicating the continuity of the cell 36 in the Y-axis direction. Specifically, the parameter calculation unit 124 compares adjacent values in the array D1. Then, an array E1 storing the larger value is created. Each numerical value of the array E1 corresponds to the Y parameter of the first embodiment. FIG. 16 shows a process for creating the array E1. In FIG. 16, each value of the array E1 is surrounded by []. For example, the first [100] of the created array E1 is associated with the cell 36 surrounded by the vertices P11, P12, P16, and P17. Further, the second [50] of the array E1 is associated with the cell 36 surrounded by P12, P13, P17, and P18. The parameter calculation unit 124 stores the created array E1 (100, 50, 0, 0). Further, the parameter calculation unit 124 creates and stores arrays E2, E3, and E4 in the same manner as the array E1.

  Next, the parameter calculation unit 124 generates a dot d1 at the center of each cell 36. Then, the parameter calculation unit 124 stores an array F1 in which “1” is set for the dot d1 where the wire 35 exists and “0” is set for the dot d1 where the wire 35 does not exist. FIG. 17 shows a process for creating the array F1. In FIG. 17, each value of the array F1 is shown enclosed in parentheses. The parameter calculation unit 124 stores the created array F1 (1, 1, 0, 0). Further, the parameter calculation unit 124 creates and stores arrays F2, F3, and F4 in the same manner as the array F1. The accuracy of the thermal strain analysis is increased by calculating the average remaining copper ratio based on the stored array F1. Note that the calculation processing of the array F1 can be omitted.

  Next, the parameter calculation unit 124 creates an array Gn indicating the remaining copper ratio of each cell 36 based on each vertex of each cell 36 and the presence or absence of wiring at the dot d1. For example, for the cell 36 surrounded by the vertices P11, P12, P16, and P17, the parameter calculation unit 124 determines whether or not the vertices P11 and P12 are wired from the array A1 (1, 1, 0, 0, 0). Judge that. Further, the presence / absence of wiring at the vertices P16 and P17 is determined from the array A2 (1, 1, 0, 0, 0). The presence / absence of the wiring of the dot d1 is determined from the array F1 (1, 1, 0, 0).

  In the present embodiment, the number of vertices and dots d1 (0 to 5) where the wiring 35 exists is converted into the remaining copper ratio. For example, when the number of vertices where the wiring 35 exists and the number of dots d1 are zero, the remaining copper ratio is set to 0%. When the number of vertices where the wiring 35 exists and the number of dots d1 are one, the remaining copper ratio is 20%. If the number of vertices where the wiring 35 exists and the number of dots d1 are two, the remaining copper ratio is 40%. When the number of vertices and dots d1 where the wiring 35 exists is 3, the remaining copper ratio is 60%. When the number of vertices and dots d1 where the wiring 35 exists is 4, the remaining copper ratio is 80%. When the number of vertices and dots d1 where the wiring 35 exists is 5, the remaining copper ratio is set to 100%. And the array Gn which memorize | stored the remaining copper rate for every cell 36 is created, and it memorize | stores. In the example illustrated in FIG. 17, the array G1 (100, 60, 0, 0) is obtained. Each numerical value of the array G1 corresponds to the wiring remaining rate of the first embodiment.

  When the creation of the array F1 is omitted, the number of vertices where the wiring 35 exists is converted into the remaining copper ratio. For example, when the number of vertices where the wiring 35 exists is 0, the remaining copper ratio is set to 0%. When the number of vertices where the wiring 35 exists is 1, the remaining copper ratio is 25%. When the number of vertices where the wiring 35 exists is two, the remaining copper ratio is set to 50%. When the number of vertices where the wiring 35 exists is 3, the remaining copper ratio is set to 75%. When the number of vertices where the wiring 35 exists is four, the remaining copper ratio is set to 100%.

  Based on the array Cn, En, Gn of the entire board model 30 calculated by the parameter calculation unit 124, the average remaining copper ratio calculation unit 125 calculates the average remaining copper ratio of the entire board model 30 and the selected IC component model 31. The average remaining copper ratio of the arranged region is calculated.

  Specifically, the average remaining copper ratio calculation unit 125 sets a region (hereinafter referred to as a setting region) of 105% of the surface area of the IC component model 31 so as to surround the IC component model 31 mounted on the board model 30. Set. And the average remaining copper ratio of a setting area | region is calculated by taking the average of the remaining copper ratio of each cell 36 which exists in a setting area | region. The following formula (1) is used to calculate the average remaining copper ratio.

Average residual copper ratio = Σ (Gi (j)) / ij (1)
Here, i represents the number of cells 36 in the X-axis direction of the range to be calculated, and j represents the number of cells 36 in the Y-axis direction of the range to be calculated.

FIG. 18 is a diagram for explaining the processing of the contribution calculation unit.
For example, Gi (j) in Expression (1) indicates the value of the i-th array Gn in the X-axis direction and the j-th array Gn in the Y-axis direction when the lower left of the region 34 is the base point. That is, the value of the array G1 of the cell 36 surrounded by the vertices P11, P12, P16, and P17 is expressed as G1 (1). In addition, the value of the array G1 of the cells 36 surrounded by the vertices P12, P13, P17, and P18 is expressed as G1 (2).

  The contribution degree calculation unit 126 is based on the array Cn, En, Gn and i, j of the whole substrate model 30 calculated by the parameter calculation unit 124, and the average X-axis direction contribution degree and average of the setting region. The Y-axis direction contribution is calculated.

The following equation (2) is used to calculate the average X-axis direction contribution. The following equation (3) is used to calculate the average Y-axis direction contribution.
Average X-axis direction contribution = Σ (Ci (j) × Gi (j) / ij (2)
Average Y-axis direction contribution = Σ (Ei (j) × Gi (j) / ij (3)
Hereinafter, the processes of the average remaining copper ratio calculation unit 125 and the contribution degree calculation unit 126 are performed for the area 34a surrounded by the six cells 36 in the area 34, the average remaining copper ratio, the average X-axis direction contribution, and the average Y-axis direction. A case where the contribution is calculated will be described as an example. In the region 34a, i = 3 and j = 2. By substituting i and j into equation (1), the average remaining copper ratio is (G1 (1) + G1 (2) + G1 (3) + G2 (1) + G2 (2) + G2 (3) / 2 × 3) = (100 + 60 + 0 + 40 + 60 + 40) / 6 = 50. Further, when i and j are substituted into equation (2), the average contribution in the X-axis direction is (C1 (1) × G1 (1) + C1 (2) × G1 (2) + C1 (3) × G1 (3 ) + C2 (1) × G2 (1) + C2 (2) × G2 (2) + C2 (3) × G2 (3) / 2 × 3 = (100 × 1.0 + 50 × 0.6 + 0 × 0 + 100 × 0.4 + 50 × 0.6 + 0 × 0.4) / 6 = (100 + 30 + 0 + 40 + 30 + 0) /6=33.3 In addition, when i and j are substituted into Equation (3), the average contribution in the Y-axis direction is (E1 (1 ) × G1 (1) + E1 (2) × G1 (2) + E1 (3) × G1 (3) + E2 (1) × G2 (1) + E2 (2) × G2 (2) + E2 (3) × G2 (3) ) / 2 × 3 = (100 × 1.0 + 100 × 0.6 + 0 × 0 + 50 × 0.4 + 50 × 0.6 + 50 × 0.4) / 6 = (100 + 60 + 0 + 20 + 30 + 20) /6=38.3.

As shown in FIG. 7, the analysis unit 11 displays the calculated average remaining copper ratio, average X-axis direction contribution, and average Y-axis direction contribution on the monitor 104a.
Next, the process of the remaining copper ratio calculation part 12 is demonstrated using a flowchart.

FIG. 19 is a flowchart showing the processing of the remaining copper ratio calculation unit.
[Step S <b> 1] The cell size determination unit 123 determines the size of the cell 36. Thereafter, the process proceeds to step S2.

[Step S2] The parameter calculation unit 124 creates an array An, An + 1,... From the position serving as the base point of the layer selected in step 7. Thereafter, the process proceeds to step S3.
[Step S3] The parameter calculation unit 124 creates an array Bn, an array Bn + 1,... That store information indicating the continuity of the wiring 35 in the X-axis direction. Thereafter, the process proceeds to step S4.

  [Step S4] The parameter calculation unit 124 compares the array Bn created in step S3 with the array Bn + 1, and the arrays Cn and Cn + 1 indicating the continuity of the wiring 35 in the X-axis direction of the cell 36 storing the larger value. Create ... Then, the process proceeds to step S5.

  [Step S5] The parameter calculation unit 124 compares the array An created in step S2 with the array An + 1, and the arrays Dn, Dn + 1,.・ ・ Create Then, the process proceeds to step S6.

  [Step S6] The parameter calculation unit 124 compares the values of the columns of the arrays D1 and D2. Then, an array En, En + 1,... Storing the larger value is created. Then, the process proceeds to step S7.

[Step S <b> 7] The parameter calculation unit 124 creates arrays Fn, Fn + 1,... Indicating the presence or absence of the wiring 35 at the center of the cell 36. Thereafter, the process proceeds to operation S8.
[Step S8] The parameter calculation unit 124 creates an array Gn, Gn + 1,... Thereafter, the process proceeds to operation S9.

  [Step S9] The average remaining copper ratio calculation unit 125 includes the arrays Gn, Gn + 1,... Created in Step S8, the number i of vertices in the X-axis direction of the calculation target range, and Y of the calculation target range. By substituting the number j of vertices in the axial direction into Equation (1), the average remaining copper ratio of the entire board model 30 and the average remaining copper ratio of the set region are calculated. Then, the process proceeds to step S10.

  [Step S10] The contribution calculation unit 126 includes the arrays Dn, Dn + 1,... Created in Step S5, the arrays Gn, Gn + 1,... Created in Step S8, and the X-axis direction of the calculation target range. Substituting the number i of vertices i and the number j of vertices in the Y-axis direction of the calculation target range into Equation (2), the average contribution in the X-axis direction of the entire substrate model 30 and the set region is calculated. Further, the contribution calculation unit 126 includes the arrays En, En + 1,... Created in step S6, the arrays Gn, Gn + 1,... Created in step S8, and the vertex in the X-axis direction of the range to be calculated. And the number j of vertices in the Y-axis direction of the calculation target range are substituted into Equation (3) to calculate the average contribution in the Y-axis direction of the entire substrate model 30 and the set region. Then, the process shown in FIG. 19 is complete | finished.

This is the end of the description of the processing in FIG.
In the present embodiment, the arrays Bn, Bn + 1,... Are created in step S3 after the arrays An, An + 1,. However, the present invention is not limited to this. For example, the creation of the array Bn may be started when the array An is created (before the creation of the array An + 1 is started). Alternatively, the calculation of the corresponding element (0, 50, or 100) of the array Bn may be started at the time when information on two adjacent vertices of the array An is acquired.

  In this embodiment, arrays Cn to Gn are created after creating arrays An and An + 1 and arrays Bn and Bn + 1 of all rows. However, the present invention is not limited to this. For example, the creation of the arrays Cn and Dn may be started when the arrays An + 1 and Bn + 1 are created.

Further, the order of creating the arrays Cn, Dn, En, and Fn is not particularly limited.
As described above, according to the circuit design support device 10, the remaining copper ratio calculation unit 12 has the arrays Cn and Cn + 1 in consideration of the continuity of the wirings in a plurality of cells connected in the X axis direction and the Y axis direction on the substrate. ,..., En, En + 1,..., Gn, Gn + 1,. And the remaining copper ratio calculation part 12 computed the average X-axis direction contribution and the average Y-axis direction contribution based on the created arrangement | sequence. Then, the analysis unit 11 calculates the equivalent physical property value of the element material based on the calculated average X-axis direction contribution and average Y-axis direction contribution. Thereby, compared with the case where the equivalent physical property value of an element material is calculated using only finite element analysis, the processing can be performed at high speed. Moreover, since the analysis can be performed in an environment close to an actual product as compared with the case where the analysis is performed using only the remaining copper ratio, the accuracy of the analysis can be improved.

  In addition, since the equivalent physical property value is output for each layer, the designer, for example, when the thermal expansion coefficient of the lower layer of the multilayer board is small and the thermal expansion coefficient of the upper layer is large, It is possible to change the wiring pattern so as to increase the coefficient of thermal expansion.

  Note that the processing performed by the circuit design support device 10 may be distributed by a plurality of devices. For example, one device performs the remaining copper ratio calculation process to calculate the average remaining copper rate, the average X-axis direction contribution, and the average Y-axis direction contribution, and the other devices calculate the calculated values. The thermal strain analysis may be performed using

  As described above, the circuit design support program, the circuit design support method, and the circuit design support apparatus of the present invention have been described based on the illustrated embodiment, but the present invention is not limited to this, and the configuration of each unit is as follows. Any structure having a similar function can be substituted. Moreover, other arbitrary structures and processes may be added to the present invention.

Further, the present invention may be a combination of any two or more configurations (features) of the above-described embodiments.
The above processing functions can be realized by a computer. In that case, a program describing the processing contents of the functions that the circuit design support apparatuses 1 and 10 should have is provided. By executing the program on a computer, the above processing functions are realized on the computer. The program describing the processing contents can be recorded on a computer-readable recording medium. Examples of the computer-readable recording medium include a magnetic storage device, an optical disk, a magneto-optical recording medium, and a semiconductor memory. Examples of the magnetic storage device include a hard disk drive, a flexible disk (FD), and a magnetic tape. Examples of the optical disk include a DVD, a DVD-RAM, and a CD-ROM / RW. Examples of the magneto-optical recording medium include an MO (Magneto-Optical disk).

  When distributing the program, for example, a portable recording medium such as a DVD or a CD-ROM in which the program is recorded is sold. It is also possible to store the program in a storage device of a server computer and transfer the program from the server computer to another computer via a network.

  The computer that executes the program stores, for example, the program recorded on the portable recording medium or the program transferred from the server computer in its own storage device. Then, the computer reads the program from its own storage device and executes processing according to the program. The computer can also read the program directly from the portable recording medium and execute processing according to the program. In addition, each time a program is transferred from a server computer connected via a network, the computer can sequentially execute processing according to the received program.

  Further, at least a part of the above processing functions can be realized by an electronic circuit such as a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), or a PLD (Programmable Logic Device).

Regarding the above first to second embodiments, the following additional notes are further disclosed.
(Supplementary note 1)
Divide the substrate model to be processed into multiple cells,
An index indicating the influence of wiring provided in the plurality of cells on the substrate model with respect to at least one direction on the plane of the substrate model is a ratio of the wiring occupying each of the plurality of cells, and the plurality of the plurality of cells. And a parameter indicating the continuity of the wiring in the direction in the adjacent cell among the cells of
Based on the calculated index, the equivalent physical property value of the wiring is calculated,
Outputting the calculated equivalent property value to a display device;
A circuit design support program characterized by causing processing to be executed.

  (Supplementary note 2) The circuit design support program according to supplementary note 1, wherein a parameter indicating the continuity in the direction is calculated based on the presence or absence of the wiring at each vertex of the adjacent cell.

  (Supplementary note 3) The circuit design support program according to supplementary note 1 or 2, wherein the ratio of the wirings is calculated based on the number of wirings present at each vertex of each of the plurality of cells.

  (Supplementary Note 4) For each of the plurality of cells, calculating the index by taking an average of a sum of values obtained by multiplying a parameter indicating the continuity and a ratio of the wiring occupied in the adjacent cells. 4. The circuit design support program according to any one of appendices 1 to 3,

(Additional remark 5) The circuit design support program of Additional remark 1 characterized by determining the length of the edge | side of these cells based on the width | variety of the said wiring.
(Appendix 6) The substrate model to be processed has a plurality of layers,
In the computer,
The circuit design support program according to appendix 1, wherein a process for causing the display device to display the equivalent physical property value for each layer is executed.

(Supplementary note 7)
Divide the substrate model to be processed into multiple cells,
An index indicating the influence of wiring provided in the plurality of cells on the substrate model with respect to at least one direction on the plane of the substrate model is a ratio of the wiring occupying each of the plurality of cells, and the plurality of the plurality of cells. And a parameter indicating the continuity of the wiring in the direction in the adjacent cell among the cells of
Based on the calculated index, the equivalent physical property value of the wiring is calculated,
Outputting the calculated equivalent property value to a display device;
A circuit design support method characterized by the above.

(Supplementary Note 8) A dividing unit that divides a substrate model to be processed into a plurality of cells;
An index indicating the influence of wiring provided in the plurality of cells on the substrate model with respect to at least one direction on the plane of the substrate model is a ratio of the wiring occupying each of the plurality of cells, and the plurality An index calculation unit for calculating based on a parameter indicating the continuity of the wiring in the direction in the adjacent cell among the cells,
Based on the calculated index, an equivalent property value calculation unit that calculates an equivalent property value of the wiring;
An output unit for outputting the calculated equivalent physical property value to a display device;
A circuit design support apparatus comprising:

DESCRIPTION OF SYMBOLS 1, 10 Circuit design support apparatus 1a Substrate model information storage part 1b Wiring information storage part 1c Division | segmentation part 1d Index calculation part 1e, 13 Equivalent property value calculation part 1f Output part 2, 30 Substrate model 3, 35 Wiring 4a-4f, 36 Cell 5 Display device 11 Analysis unit 12 Remaining copper ratio calculation unit 121 Substrate outline information storage unit 122 Evaluation IC area storage unit 123 Cell size determination unit 124 Parameter calculation unit 125 Average remaining copper ratio calculation unit 126 Contribution calculation unit 14 Display unit 20 Gerber data storage 31, 32, 33 IC part model 34, 34a Area B1-B5 Button P1-P8 Vertex T, T1, T2, T3 Table

Claims (7)

On the computer,
Divide the substrate model to be processed into multiple cells,
An index indicating the influence of wiring provided in the plurality of cells on the substrate model with respect to at least one direction on the plane of the substrate model is a ratio of the wiring occupying each of the plurality of cells, and the plurality of the plurality of cells. And a parameter indicating the continuity of the wiring in the direction in the adjacent cell among the cells of
Based on the calculated index, calculate the equivalent physical property value of the cell ,
Outputting the calculated equivalent property value to a display device;
A circuit design support program characterized by causing processing to be executed.   2. The circuit design support program according to claim 1, wherein a parameter indicating the continuity in the direction is calculated based on the presence / absence of the wiring at each vertex of the adjacent cell.   3. The circuit design support program according to claim 1, wherein the wiring ratio is calculated based on the number of wirings existing at each vertex of each of the plurality of cells.   The circuit design support program according to claim 1, wherein lengths of sides of the plurality of cells are determined based on a width of the wiring. The substrate model to be processed has a plurality of layers,
In the computer,
The circuit design support program according to claim 1, wherein a process for causing the display device to display the equivalent physical property value for each layer is executed. Computer
Divide the substrate model to be processed into multiple cells,
An index indicating the influence of wiring provided in the plurality of cells on the substrate model with respect to at least one direction on the plane of the substrate model is a ratio of the wiring occupying each of the plurality of cells, and the plurality of the plurality of cells. And a parameter indicating the continuity of the wiring in the direction in the adjacent cell among the cells of
Based on the calculated index, calculate the equivalent physical property value of the cell ,
Outputting the calculated equivalent property value to a display device;
A circuit design support method characterized by the above. A dividing unit for dividing the substrate model to be processed into a plurality of cells;
An index indicating the influence of wiring provided in the plurality of cells on the substrate model with respect to at least one direction on the plane of the substrate model is a ratio of the wiring occupying each of the plurality of cells, and the plurality of the plurality of cells. An index calculation unit for calculating based on a parameter indicating the continuity of the wiring in the direction in the adjacent cell among the cells,
Based on the calculated index, an equivalent property value calculation unit that calculates an equivalent property value of the cell ;
An output unit for outputting the calculated equivalent physical property value to a display device;
A circuit design support apparatus comprising:

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