JP2016126593A - Model creation program, model creation method, and information processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten an analysis time by efficiently simplifying an analytic model.SOLUTION: A board having a wiring pattern is divided into a plurality of regions, a wiring pattern in each region is converted into a pattern identifier corresponding to the wiring pattern about each region, and the possibility/impossibility of connection of adjacent regions with each other is determined on the basis of the converted first pattern identifier. when it is determined that the adjacent regions can be connected, the adjacent regions are connected with each other, and a result of the connection is outputted as an analytic model.SELECTED DRAWING: Figure 9

Description

  This case relates to a model creation program, a model creation method, and an information processing apparatus.

  In recent years, electronic devices have been highly integrated, highly functional, and downsized. In such an electronic device, it is required to accurately perform a thermal analysis of a substrate (for example, a printed wiring board) on which an electronic component or the like is mounted. In particular, with the increase in the density of electronic components and the like on the substrate, it is difficult to design exhaust heat on the substrate. For this reason, high-accuracy thermal analysis in consideration of the wiring pattern on the substrate is required.

  Therefore, the substrate is divided into a plurality of minute rectangular areas, and in each rectangular area, the equivalent thermal conductivity in the direction of mutually orthogonal axes (for example, x, y, z axes of orthogonal coordinates) is calculated, and thermal analysis is performed. The technique to do is known. The equivalent thermal conductivity means a thermal conductivity that is given by regarding a part including a plurality of materials as one block.

JP 2006-313522 A JP 2004-227337 A JP 2005-050137 A JP-A-11-260818

  In the above-described method, in order to improve the accuracy of the thermal analysis of the substrate, it is conceivable to increase the number of divisions of the rectangular area and to refine the thermal analysis model of the substrate. However, if the thermal analysis model is detailed, the calculation load of the thermal analysis simulation based on the thermal analysis model increases, and it takes a lot of analysis time.

  In one aspect, the purpose of this case is to efficiently simplify the analysis model and shorten the analysis time.

  The model creation program in this case is a program for causing a computer to execute a process for creating an analysis model of a substrate having a wiring pattern, and causes the computer to execute the following processes (1) to (4).

(1) A process of dividing the substrate into a plurality of first regions.
(2) For each of the plurality of first regions, a process of converting the first wiring pattern in each first region into a first pattern identifier corresponding to the first wiring pattern.
(3) A process of determining whether or not the adjacent first areas included in the plurality of first areas can be combined based on the converted first pattern identifier.
(4) A process of combining the adjacent first regions when it is determined that they can be combined.

  According to one embodiment, the analysis model can be efficiently simplified and the analysis time can be shortened.

It is a block diagram which shows an example of a function structure of the information processing apparatus which has a model creation function as one Embodiment of this invention. It is a block diagram which shows an example of the hardware constitutions of the information processing apparatus which implement | achieves the model creation function as one Embodiment of this invention. It is a figure explaining the outline | summary of the simplification procedure of the analysis model in this embodiment. It is a figure explaining the specific example of the board | substrate division | segmentation in this embodiment, and pattern number conversion. It is a figure which shows an example of the cell pattern table used by the pattern number conversion shown in FIG. It is a figure explaining the example of recognition of the wiring pattern at the time of pattern number conversion in this embodiment. It is a figure explaining the specific example of the cell synthesis | combination in this embodiment. It is a figure which shows an example of the joint pattern table used by the cell composition shown in FIG. It is a flowchart explaining operation | movement of the information processing apparatus of this embodiment. 10 is a flowchart for explaining a procedure of cell synthesis processing in the X direction shown in FIG. 9. It is a figure which shows the specific example of the cell synthetic | combination process of the X direction shown in FIG. 9 and FIG. 10, and the cell synthetic | combination process of a Y direction.

  Hereinafter, embodiments of a model creation program, a model creation method, and an information processing apparatus disclosed in the present application will be described in detail with reference to the drawings. However, the embodiment described below is merely an example, and there is no intention to exclude application of various modifications and techniques not explicitly described in the embodiment. That is, the present embodiment can be implemented with various modifications without departing from the spirit of the present embodiment. Each figure is not intended to include only the components shown in the figure, and may include other functions. And each embodiment can be suitably combined in the range which does not contradict a processing content.

[1] Hardware Configuration of Information Processing Device that Implements Model Creation Function First, the hardware configuration of an information processing device (computer, model creation device) 10 that implements the model creation function of the present embodiment with reference to FIG. Will be described. FIG. 2 is a block diagram illustrating an example of the hardware configuration.

  The computer 10 includes a processor 11, a RAM (Random Access Memory) 12, an HDD (Hard Disk Drive) 13, a graphic processing device 14, an input interface 15, an optical drive device 16, a device connection interface 17, and a network interface 18 as components. . These components 11 to 18 are configured to be able to communicate with each other via a bus 19.

  The processor (processing unit) 11 controls the entire computer 10. The processor 11 may be a multiprocessor. The processor 11 is, for example, a CPU (Central Processing Unit), an MPU (Micro Processing Unit), a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), a PLD (Programmable Logic Device), or an FPGA (Field Programmable Gate Array). Or one. Further, the processor 11 may be a combination of two or more types of elements of CPU, MPU, DSP, ASIC, PLD, and FPGA.

  A RAM (storage unit) 12 is used as a main storage device of the computer 10. The RAM 12 temporarily stores at least part of an OS (Operating System) program and application programs to be executed by the processor 11. The RAM 12 stores various data necessary for processing by the processor 11. The application program may include a model creation program executed by the processor 11 in order to realize the model creation function of the present embodiment by the computer 10.

  The HDD (storage unit) 13 magnetically writes and reads data to and from the built-in disk. The HDD 13 is used as an auxiliary storage device of the computer 10. The HDD 13 stores an OS program, application programs, and various data. Note that a semiconductor storage device (SSD: Solid State Drive) such as a flash memory can be used as the auxiliary storage device.

  A monitor 14 a is connected to the graphic processing device 14. The graphic processing device 14 displays an image on the screen of the monitor 14 a in accordance with a command from the processor 11. Examples of the monitor 14a include a display device using a CRT (Cathode Ray Tube) and a liquid crystal display device.

  A keyboard 15a and a mouse 15b are connected to the input interface 15. The input interface 15 transmits signals sent from the keyboard 15a and the mouse 15b to the processor 11. The mouse 15b is an example of a pointing device, and other pointing devices can also be used. Examples of other pointing devices include a touch panel, a tablet, a touch pad, and a trackball.

  The optical drive device 16 reads data recorded on the optical disc 16a using laser light or the like. The optical disc 16a is a portable non-temporary recording medium on which data is recorded so as to be readable by reflection of light. Examples of the optical disc 16a include DVD (Digital Versatile Disc), DVD-RAM, CD-ROM (Compact Disc Read Only Memory), CD-R (Recordable) / RW (ReWritable), and the like.

  The device connection interface 17 is a communication interface for connecting peripheral devices to the computer 10. For example, the device connection interface 17 can be connected to a memory device 17a or a memory reader / writer 17b. The memory device 17a is a non-temporary recording medium equipped with a communication function with the device connection interface 17, for example, a USB (Universal Serial Bus) memory. The memory reader / writer 17b writes data to the memory card 17c or reads data from the memory card 17c. The memory card 17c is a card-type non-temporary recording medium.

  The network interface 18 is connected to the network 18a. The network interface 18 transmits / receives data to / from other computers or communication devices via the network 18a.

  The computer 10 having the hardware configuration as described above can realize the model creation function of the present embodiment described later with reference to FIGS.

  In addition, the computer 10 implement | achieves the model creation function of this embodiment by, for example, running the program (model creation program etc.) recorded on the computer-readable non-transitory recording medium. A program describing the processing contents to be executed by the computer 10 can be recorded in various recording media. For example, a program to be executed by the computer 10 can be stored in the HDD 13. The processor 11 loads at least a part of the program in the HDD 13 into the RAM 12 and executes the loaded program.

  A program to be executed by the computer 10 (processor 11) can also be recorded on a non-transitory portable recording medium such as the optical disk 16a, the memory device 17a, and the memory card 17c. The program stored in the portable recording medium becomes executable after being installed in the HDD 13 under the control of the processor 11, for example. Further, the processor 11 can also read and execute the program directly from the portable recording medium.

[2] Functional Configuration of Information Processing Device Having Model Creation Function Next, the functional configuration of the information processing device (computer) 10 having the model creation function of the present embodiment will be described with reference to FIG. FIG. 1 is a block diagram illustrating an example of the functional configuration.

  The computer 10 has at least functions as a processing unit 20, a storage unit 30, and an input unit 40, as shown in FIG. 1, in order to create an analysis model of a board (for example, a printed wiring board) having a wiring pattern. Yes.

  The processing unit 20 is, for example, a processor 11 as shown in FIG. 2, and by executing the above-described model creation program, a dividing unit 21, a converting unit 22, a combining unit 23, an equivalent thermal conductivity calculating unit 24, and an output unit. The function as 25 is fulfilled.

  The storage unit 30 is, for example, a RAM 12 and an HDD 13 as shown in FIG. 2, and stores and stores various information for realizing the model creation function. The various information includes a wiring pattern image 31, a cell pattern table 32, a coupling pattern table 33, material property data 34, a thermal analysis model 35, and the like.

  The input unit 40 inputs a two-dimensional wiring pattern image 31 (for example, see FIG. 4A) on the board on which the thermal analysis model 35 is to be created, to the computer 10. Hereinafter, the image 31 may be referred to as a two-dimensional wiring pattern image 31 or a wiring pattern image 31. The input unit 40 inputs the cell pattern table 32, the coupling pattern table 33, the material property data 34, and the like to the computer 10. The function as the input unit 40 is realized by, for example, the input interface 15, the optical drive device 16, the device connection interface 17, and the network interface 18 shown in FIG.

  That is, the various types of information 31 to 34 may be input by operating the keyboard 15a and the mouse 15b connected to the input interface 15. Various types of information 31 to 34 may be input from the optical disc 16 a connected to the optical drive device 16. The various types of information 31 to 34 may be input from the memory device 17a, the memory reader / writer 17b, and the memory card 17c connected to the device connection interface 17. The various types of information 31 to 34 may be transmitted and input via the network 18 a connected to the network interface 18.

  The dividing unit 21 reads out the two-dimensional wiring pattern image 31 on the substrate as a substrate on which the thermal analysis model 35 is to be created from the storage unit 30, and a plurality of rectangular regions (first region; for example, FIG. 4B). ). A divided rectangular area or a rectangular area synthesized or combined as described later (second area; see, for example, FIGS. 7B to 7E) may be referred to as a cell.

  For each of the plurality of first regions (each cell) divided by the dividing unit 21, the conversion unit 22 converts the first wiring pattern in each first region into a first pattern identifier corresponding to the first wiring pattern. To do. At that time, the conversion unit 22 uses the cell pattern table (first pattern table) 32 stored in the storage unit 30, as will be described later with reference to FIG. 4, for example, and the first wiring pattern in each first region. Is converted into a first pattern identifier.

  As will be described later with reference to FIG. 5, for example, the cell pattern table 32 associates a first wiring pattern (type of wiring pattern) in each first region (each cell) with a first pattern identifier. In the present embodiment, as shown in FIGS. 4, 5, 7, and 8, the case where the pattern identifiers are pattern numbers “1”, “2”, “3”,. The pattern identifier is not limited to this, and information other than the number (for example, character information, symbol information) that can specify the type of the wiring pattern in each cell may be used as the pattern identifier.

  Based on the first pattern identifier converted by the conversion unit 22, the combining unit 23 determines whether or not the adjacent first regions (adjacent cells) included in the plurality of first regions can be combined. When it is determined that the combination is possible, the combining unit 23 combines adjacent first regions as described later with reference to, for example, FIGS. 7B to 7E. Hereinafter, “join” may be referred to as “merge” or “composite”.

  For the second region (cell 31b; see FIG. 7) obtained by combining the first regions (cell 31a; see FIGS. 4 and 7), the synthesizer 23 has a second wiring pattern in the second region. A second pattern identifier corresponding to is set. At that time, the synthesizer 23 uses the combined pattern table (second pattern table) 33 stored in the storage unit 30, as described later with reference to FIG. 2nd pattern number) is set.

  As will be described later with reference to FIG. 8, for example, the combined pattern table 33 is a second of the second areas obtained by combining the combinations of the first pattern identifiers of the adjacent first areas and the first areas of the combinations. Corresponds to the pattern identifier.

  The synthesizer 23 replaces the set second pattern identifier with the first pattern identifier and replaces the second area with the first area, and then uses the combined cell pattern table 33 to generate the first pattern identifier based on the first pattern identifier. The combination of regions is repeatedly performed (for example, see FIG. 7).

  Further, the synthesizing unit 23 determines that the combination of the first pattern identifiers associated with the second pattern identifiers in the combined pattern table 33 can be combined (see FIG. 8). On the other hand, the synthesizing unit 23 determines that the combination of the first pattern identifiers that are not associated with the second pattern identifiers in the combined pattern table 33 cannot be combined (see FIG. 8).

  The equivalent thermal conductivity calculation unit 24 stores the combined cells obtained by the combining unit 23, the wiring pattern (type of wiring pattern) specified by the pattern identifier for each combined cell, and the storage unit 30. Based on the material property data 34, the equivalent thermal conductivity of each cell is calculated. The material property data 34 is data including thermal resistivity and thermal conductivity of the wiring material included in the substrate.

  The output unit 25 associates the combined cell obtained by the synthesis unit 23 with the equivalent thermal conductivity of each cell calculated by the equivalent thermal conductivity calculation unit 24, and serves as a thermal analysis model (analysis model) 35. The data is output to the storage unit 30 and stored.

[3] Outline of Analysis Model Simplification Procedure Next, an outline of an analysis model simplification procedure in the present embodiment will be described with reference to FIG.

  In the present embodiment, the two-dimensional wiring pattern image on the substrate on which the thermal analysis model 35 is to be created is divided into a plurality of cells. Further, the equivalent thermal conductivity in each cell is patterned as a pattern number corresponding to the wiring pattern in each cell by using a cell pattern table 32 as shown in FIG. Is done. In the cell pattern table 32 shown in FIG. 3A, when the wiring pattern penetrates the cell in the left-right direction, the pattern number “1” is set, and when the wiring pattern penetrates the cell vertically, the pattern number “ 2 "is set.

  As shown in FIG. 3B, when the pattern numbers of the wiring patterns in two cells adjacent in the left-right direction are both “1”, these two cells have the wiring pattern in the cell. Can be merged into one cell of pattern number “1”. That is, the equivalent thermal conductivity in the cell is patterned by the pattern number for each cell, and the cells can be joined (merged) based on the pattern number using the joint pattern table 33 prepared in advance. The equivalent thermal conductivity is calculated after completing the cell coupling.

  As described above, in this embodiment, by combining the cells in the thermal analysis model 35 using the cell pattern table 32 and the combination pattern table 33 prepared in advance, the thermal analysis model 35 is efficiently simplified, and the analysis time is reduced. Is greatly shortened.

  Here, the anisotropy of the equivalent thermal conductivity increases depending on the wiring pattern in each cell. When adjacent cells are joined, the anisotropy of the equivalent thermal conductivity in the joined cells depends on the wiring pattern in the joined cells. Therefore, even if the cells are joined based on the pattern number, the anisotropy of the equivalent thermal conductivity in the cells after the joining is preserved.

[4] Specific Example of Analysis Model Simplification Procedure Next, a specific example of the analysis model simplification procedure in the present embodiment will be described with reference to FIGS. 4 to 8.

  First, specific examples of substrate division and pattern number conversion in the present embodiment will be described with reference to FIGS. FIG. 4 is a diagram for explaining a specific example thereof. FIG. 5 is a diagram showing an example (part) of the cell pattern table 32 used in the pattern number conversion shown in FIG. FIG. 6 is a diagram for explaining a recognition example (deemed example) of a wiring pattern at the time of pattern number conversion in the present embodiment.

  In the example shown in FIG. 4, a two-dimensional wiring pattern image 31 as shown in FIG. 4A is input, and the two-dimensional wiring pattern image 31 is converted into 4 × 4 cells (rectangular shapes) as shown in FIG. Area) 31a. That is, it is divided into a total of 16 cells, 4 columns in the X direction and 4 rows in the Y direction. In the figure, the bold line indicates the wiring pattern on the substrate.

  And the wiring pattern in each cell 31a shown to (B) is converted into a pattern number like (C) by the conversion part 22 using the cell pattern table 32 shown in FIG. For example, in (B), the wiring pattern in each cell 31a that forms the first column (first column) from the left side is a pattern that penetrates each cell 31a in the left-right direction (X direction). Therefore, the wiring pattern of the four cells 31a in the first column is converted into the pattern number “1” based on the cell pattern table 32 shown in FIG. Similarly, the wiring pattern of the four cells 31a in the second column is also converted to the pattern number “1”.

  In addition, the wiring patterns in the four cells 31a in the fourth row are all patterns that penetrate each cell 31a in the vertical direction (Y direction). Therefore, the wiring pattern of the four cells 31a in the fourth column is converted into the pattern number “2” based on the cell pattern table 32 shown in FIG. Furthermore, the wiring patterns in the four cells 31a in the third row are respectively given pattern numbers “7”, “3”, “4”, “8” in order from the top in the light of the cell pattern table 32 shown in FIG. Is converted to

  In addition, when a plurality of wiring patterns pass from one same side to the same other side in each cell 31a, the conversion unit is considered after regarding the plurality of wiring patterns as one wiring pattern. The pattern number conversion by 22 is performed. For example, as shown in each of FIGS. 6A to 6E, the conversion unit 22 uses the right side for a left cell in which a plurality of wiring patterns pass from the same one side to the other side. Like a cell, a plurality of wiring patterns are recognized as one wiring pattern. The conversion unit 22 recognizes the wiring pattern of each cell in this way, and performs pattern number conversion using the cell pattern table 32 for the recognized cell. For example, the wiring patterns (A) to (E) shown in FIG. 6 are converted into pattern numbers “1”, “1”, “2”, “4”, and “8”, respectively.

  As shown in FIG. 5, for example, the cell pattern table 32 associates the type of the wiring pattern (first wiring pattern) in each cell (each first region) 31a with the pattern number (first pattern identifier). The conversion unit 22 refers to the cell pattern table 32 as shown in FIG. 5 and converts the wiring pattern in each cell 31a into a pattern number corresponding to the type of the wiring pattern.

  Next, a specific example of cell synthesis in this embodiment will be described with reference to FIGS. FIG. 7 is a diagram for explaining a specific example thereof. FIG. 8 is a diagram showing an example (part) of the combined pattern table 33 used in the cell synthesis shown in FIG.

  The combining unit 23 refers to the combined pattern table 33 based on the pattern number converted by the converting unit 22 as shown in FIG. 7A, for example, so that the adjacent cells 31a and 31a can be combined. Judging.

  For example, as shown in FIG. 8, the combination pattern table 33 includes a combination of pattern numbers of adjacent cells 31a and 31a and a pattern number of a cell (second area) 31b obtained by combining the cells 31a and 31a of the combination. (Second pattern identifier) is associated.

  In the combined pattern table 33 shown in FIG. 8, when adjacent cells 31a and 31a can be combined, the combination of the pattern numbers of the adjacent cells 31a and 31a that can be combined corresponds to the pattern number of the combined cell 31b. Attached.

  For example, when the pattern numbers of two cells 31a and 31a adjacent in the left-right direction (X direction) are both “1”, the pattern number of the combined cell 31b is also “1” as shown in the remarks column. . Therefore, in the combined pattern table 33, the pattern number combination “1” and “1” of the left and right cells 31a and 31a is associated with the pattern number “1” of the combined cell 31b.

  Similarly, for example, when the pattern numbers of two cells 31a and 31a adjacent in the vertical direction (Y direction) are “7” and “8”, respectively, as shown in the remarks column, the pattern number of the combined cell 31b Is “9”. Therefore, in the combined pattern table 33, the pattern number combination “7”, “8” of the upper and lower cells 31a, 31a is associated with the pattern number “9” of the combined cell 31b.

  As described above, in the combined pattern table 33, when the pattern number of the combined cell 31b is associated with the combination of the pattern numbers of the adjacent cells 31a and 31a, the combining unit 23 selects the adjacent cells 31a and 31a. It is determined that can be combined. On the other hand, when the pattern number of the cell 31b after the combination is not associated with the combination of the pattern numbers of the adjacent cells 31a and 31a in the combined pattern table 33, the combining unit 23 cannot combine the adjacent cells 31a and 31a. It is judged that.

  For example, in the combined pattern table 33 shown in FIG. 8, when the pattern numbers of two cells 31a and 31a adjacent in the left-right direction are “1” and “2”, respectively, when these cells 31a and 31a are combined, the wiring pattern The two will cross each other. For this reason, as shown in the remarks column, cells with pattern numbers “1” and “2” are not combined, and combinations of pattern numbers of left and right cells 31a and 31a “1” and “2” The pattern numbers of the cells 31b after the combination are not associated with each other (described as “no combination” in FIG. 8).

  When the combining unit 23 determines that the adjacent cells 31a and 31a can be combined, the combining unit 23 combines the adjacent cells 31a and 31a as shown in FIGS. That is, the synthesis unit 23 sets a pattern number (second pattern identifier) corresponding to the wiring pattern (second wiring pattern) in the cell 31b for the cell 31b obtained by combining the cells 31a and 31a. . At that time, the synthesizer 23 refers to the combined pattern table 33 as shown in FIG. 8 and sets a pattern for the combined cell 31b. The combining unit 23 replaces the pattern number set in the combined cell 31b with the first pattern identifier, replaces the combined cell 31b with the cell 31a as the first area, and then combines the combined cell pattern table 33. Is used to repeatedly combine cells 31a and 31a based on the first pattern identifier.

  In the example shown in FIG. 7, each cell 31a obtained as shown in (A) is combined with a cell 31a adjacent in the left-right direction (X direction) as shown in (B). 7B, the cells in the first column and the cells in the second column in FIG. 7A are combined for each row, and the cells in the third column and the cells in the fourth column are combined for each row. Is done. At this time, since the combined pattern numbers are associated with any cell combination, it is determined that the cells 31a and 31a can be combined, and as shown in FIG. 7B, the cells 31a and 31a are combined. Combining is performed, and the combined cell 31b is obtained.

  With the cell combination from (A) to (B) of FIG. 7, the pattern number of each cell 31b after combination is set as follows. When the combination of the pattern numbers of the left and right cells 31a and 31a is “1” and “1”, the pattern number of the combined cell 31b is “1”. When the combination of the pattern numbers of the left and right cells 31a and 31a is “7” and “2”, the pattern number of the combined cell 31b is “7”. When the combination of the pattern numbers of the left and right cells 31a and 31a is “3” and “2”, the pattern number of the combined cell 31b is “7”. When the combination of the pattern numbers of the left and right cells 31a and 31a is “4” and “2”, the pattern number of the combined cell 31b is “8”. When the combination of the pattern numbers of the left and right cells 31a and 31a is “8” and “2”, the pattern number of the combined cell 31b is “8”.

  Similarly, in the example shown in FIG. 7, each cell 31b obtained as shown in (B) is combined with a cell 31b adjacent in the left-right direction (X direction) as shown in (C). In FIG. 7C, the cells in the first column and the cells in the second column in FIG. 7B are combined for each row. At this time, since the combined pattern numbers are associated with each cell combination, it is determined that the cells 31b and 31b can be combined, and as shown in FIG. 7C, the cells 31b and 31b. The cells are combined and a combined cell is obtained. When the combination of the pattern numbers of the left and right cells 31b and 31b is “1” and “7”, the pattern number of the combined cell is “7”. When the combination of the pattern numbers of the left and right cells 31b and 31b is “1” and “8”, the pattern number of the combined cell is “8”.

  Further, in the example shown in FIG. 7, each cell obtained as shown in (C) is combined with a cell adjacent in the vertical direction (Y direction) as shown in (D). In FIG. 7D, the cells in the first row and the cells in the second row are joined from the top in FIG. 7C, and the cells in the third row and the cells in the fourth row are joined. At this time, since any cell combination is associated with the pattern number after combination (not shown in FIG. 8), it is determined that the cells can be combined, and as shown in FIG. The upper and lower cells are joined together to obtain a joined cell. When the combination of the pattern numbers of the upper and lower cells is “7” and “7”, the pattern number of the combined cell is “7”. When the combination of the pattern numbers of the upper and lower cells is “8” and “8”, the pattern number of the combined cell is “8”.

  Furthermore, in the example shown in FIG. 7, each cell obtained as shown in (D) is combined with a cell adjacent in the vertical direction (Y direction) as shown in (E). In FIG. 7E, the upper and lower cells in FIG. 7D are combined. At this time, since the combined pattern number is associated with the cell combination, it is determined that the cells can be combined, and as shown in FIG. 7E, the upper and lower cells are combined. , A combined cell is obtained. When the combination of the pattern numbers of the upper and lower cells is “7” and “8”, the pattern number of the combined cell is “9”.

  As a result of cell combination, when a plurality of wiring patterns pass from one side to another side in the combined cell 31a, the plurality of wiring patterns are regarded as one wiring pattern, The pattern number of the merged cell is set. That is, as in the example described above with reference to each of FIGS. 6A to 6E, the left cell in which a plurality of wiring patterns pass from one side to the other side is the right cell. As described above, a plurality of wiring patterns are recognized as one wiring pattern. Thus, after recognizing the wiring pattern of the combined cell, the pattern number of the combined cell is registered in the combined pattern table 33. For example, the pattern numbers of the cells after combining (A) to (E) shown in FIG. 6 are “1”, “1”, “2”, “4”, and “8”, respectively.

[5] Operation of Information Processing Device of this Embodiment Next, the operation of the information processing device 10 of this embodiment will be described with reference to FIGS. 9 to 11. FIG. 9 is a flowchart for explaining the operation of the information processing apparatus 10 according to the present embodiment. FIG. 10 is a flowchart for explaining the procedure of the cell compositing process in the X direction (step S6) shown in FIG. FIG. 11 is a diagram illustrating a specific example of the cell compositing process in the X direction (step S6) and the cell compositing process in the Y direction (step S7) shown in FIG. 9 and FIG.

  First, the operation of the information processing apparatus (computer) 10 according to the present embodiment will be described with reference to the flowchart shown in FIG. 9 (steps S1 to S9).

  In the storage unit 30 of the computer 10, a cell pattern table 32, a coupling pattern table 33, and material property data 34 are stored in advance. In addition, a two-dimensional wiring pattern image (substrate image) 31 of the substrate on which the thermal analysis model 35 is to be created is input and stored in the storage unit 30 by the input unit 40 (step S1).

  The input two-dimensional wiring pattern image 31 is divided into M × N cells (rectangular regions) 31 a by the dividing unit 21. That is, the image 31 is divided into M in the X direction (left and right direction) and divided into N in the Y direction (up and down direction) (step S2). M and N are integers of 2 or more.

  A pattern number corresponding to the wiring pattern in each divided cell 31 a is acquired from the cell pattern table 32 by the conversion unit 22. That is, the wiring pattern of each cell 31a is converted into a pattern number corresponding to the wiring pattern (step S3). Then, the combining unit 23 sets the number of times of combining (number of times of combining) to 0 (step S4), and then executes cell combining processing (cell combining processing) by the following steps S5 to S9.

  That is, the synthesis unit 23 adds 1 to the current number of synthesis, and then performs cell synthesis processing in the X direction (step S6) and performs cell synthesis processing in the Y direction (step S7). After performing these cell combining processes, the combining unit 23 determines whether or not the number of combined cells is 0 (step S8). When the number of combined cells is 0 (YES route in step S8), the combining unit 23 ends the cell combining process.

  If the number of combined cells is not 0 (NO route in step S8), the combining unit 23 determines whether or not the current combining number has reached a predetermined combining number set in advance (step S8). S9). When the current number of times of synthesis has not reached the predetermined number of times of synthesis (NO route of step S9), the synthesis unit 23 returns to the process of step S5. The predetermined number of times of synthesis may be preset and stored in the storage unit 30 using the input unit 40 or the like.

  On the other hand, when the current number of times of synthesis has reached the predetermined number of times of synthesis (YES route in step S9), the synthesis unit 23 ends the cell synthesis process. When the synthesis unit 23 finishes the cell synthesis process, the equivalent thermal conductivity of each cell is equivalent based on the synthesized cell, the wiring pattern specified by the pattern number for each synthesized cell, and the material property data 34. Calculated by the thermal conductivity calculator 24. Then, the combined cells obtained by the synthesis unit 23 and the equivalent thermal conductivity of each cell calculated by the equivalent thermal conductivity calculation unit 24 are associated with each other and stored in the storage unit 30 as the thermal analysis model 35. The

Next, the procedure of the cell synthesis process in the X direction (step S6) shown in FIG. 9 will be described according to the flowchart shown in FIG. 10 (steps S11 to S20). In the flowchart shown in FIG. 10, for X _i = 1 to M / 2 (M is the number of divisions in the X direction), 2X _i −1 and 2X _i columns are combined. The coordinate display (X _i , Y _i ) specifies each cell. For example, as shown in FIG. 11, each cell is associated with the coordinate display (1, 1) to (8, 8). . FIG. 11 illustrates the case where M = N = 8.

Note that the Y-direction cell synthesis process (step S7) shown in FIG. 9 replaces the X-direction division number M with the Y-direction division number N in the process shown in FIG. 10, and Y _i = 1 to N / 2 (N is The number of Y-direction divisions) is executed in the same manner as the cell synthesis process in the X direction by synthesizing 2Y _i −1 and 2Y _i rows. However, when the cell synthesis process in the X direction is completed, the synthesis unit 23 proceeds to the process of step S7 in FIG. 9, whereas when the cell synthesis process in the Y direction is completed, the synthesis unit 23 The process proceeds to step S8.

The synthesizer 23 first sets Y _i = 1 (step S11) and sets X _i = 1 (step S12). The combining unit 23 combines the cell (2X _i −1, Y _i ) and the cell (2X _i , Y _i ), and combines them using the combined pattern table 33 based on the pattern numbers of these cells ( The pattern number after the combination is calculated and acquired (step S13). A pattern number after synthesis (after combination) may be referred to as a synthesis pattern number.

When the combined pattern number corresponding to the combination of the pattern numbers of the cell (2X _i −1, Y _i ) and the cell (2X _i , Y _i ) is not present in the combined pattern table 33 (NO route of step S14), the combining unit 23 Returns the cell (wiring pattern) synthesized in step S13 to the original state (step S20). Thereafter, the combining unit 23 ends the cell combining process in the X direction.

When the combined pattern number corresponding to the combination of the pattern numbers of the cell (2X _i −1, Y _i ) and the cell (2X _i , Y _i ) is present in the combined pattern table 33 (YES route of step S14), the combining unit 23 Adds 1 to the current X _i (step S15). Then, the synthesizer 23 determines whether X _i after adding 1 is M / 2 or less (step S16). If X _i is equal to or less than M / 2 (YES route of step S16), the synthesis unit 23 returns to the process of step S13 and repeatedly executes the same process.

On the other hand, when X _i is larger than M / 2 (NO route of step S16), the synthesizer 23 adds 1 to the current Y _i (step S17). Then, the synthesizer 23 determines whether Y _i after adding 1 is N or less (step S18). When Y _i is N or less (YES route of step S18), the composition unit 23 returns to the process of step S12 and repeatedly executes the same process. If Y _i is larger than N (NO route in step S18), the combining unit 23 replaces the current M with M / 2 (step S19), and then ends the cell combining process in the X direction.

Here, with reference to FIGS. 11A to 11E, specific examples of the cell synthesis process in the X direction (step S <b> 6) and the cell synthesis process in the Y direction (step S <b> 7) shown in FIGS. 9 and 10. explain. FIG. 11 shows an example where M = N = 8 as described above. Further, a description will be given of a combination of cells to be combined when a combined pattern number exists in the combined pattern table 33, that is, when it is not determined that combining is not possible. Further, a case where the predetermined number of synthesis is 2 will be described. In FIGS. 11A to 11D, two adjacent cells surrounded by coordinate display (X _i , Y _i ) by a broken line are combined.

  When the number of times of synthesis is 1, the 8 × 8 cells shown in FIG. 11A are obtained by the first cell synthesis process in the X direction (step S6 in FIG. 9; steps S11 to S19 in FIG. 10). 11 is synthesized into 4 × 8 cells as shown in FIG. Thereafter, the 4 × 8 cells shown in FIG. 11B are obtained by the first cell synthesis process in the Y direction (step S7 in FIG. 9; steps similar to steps S11 to S19 in FIG. 10). 11 is synthesized into 4 × 4 cells as shown in FIG.

  After the cell synthesis process in the Y direction, a NO determination is made in step S8 of FIG. 9 and a NO determination is made in step S9. In step S5, 1 is added to the current number of synthesis 1, so that the number of synthesis is 2. Then, by the second cell synthesis process in the X direction (step S6 in FIG. 9; steps S11 to S19 in FIG. 10), 4 × 4 cells shown in FIG. Are combined into 2 × 4 cells as shown in FIG. Thereafter, by the second cell synthesis process in the Y direction (step S7 in FIG. 9; steps similar to steps S11 to S19 in FIG. 10), 2 × 4 cells shown in FIG. 11 is synthesized into 2 × 2 cells as shown in (E) of FIG.

  Thereafter, the determination at step S8 in FIG. 9 is NO, and the current number of synthesis reaches the predetermined number of synthesis 2 (YES route at step S9). Therefore, at this point, the cell combining process is finished, and 2 × 2 cells as shown in FIG. 11E are obtained as the combined cells.

  As described above, according to the computer 10 of this embodiment, by combining the cells in the thermal analysis model 35 using the cell pattern table 32 and the coupling pattern table 33 prepared in advance, the thermal analysis model 35 can be efficiently obtained. This simplifies the analysis time required for thermal analysis of the substrate.

  That is, according to the method of the present embodiment, the process of combining adjacent cells can be easily performed by simply referring to the two types of tables 32 and 33, so that the thermal analysis model 35 can be created at high speed.

  Further, since the number of cells of the thermal analysis model 35 is reduced and the thermal analysis model 35 is simplified, it is possible to reduce the number of times of calculation of the equivalent thermal conductivity, and to further speed up the creation of the thermal analysis model 35. Is possible.

  Furthermore, since it is not necessary to maintain the value of the equivalent thermal conductivity of each cell before cell connection, it is possible to save the memory usage.

[6] Others While the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made without departing from the spirit of the present invention. It can be changed and implemented.

  For example, in the above-described embodiment, the case where the two-dimensional wiring pattern image 31 is divided into 4 × 4 or 8 × 8 cells has been described, but the present invention is not limited to these numbers. In the above-described embodiment, the case where the thermal analysis model 35 is created as the analysis model has been described. However, the present invention is not limited to this, and a case where various analysis models other than thermal analysis are created. In addition, the present invention is applied in the same manner as in the above-described embodiment, and the same effects as those in the above-described embodiment can be obtained.

[7] Supplementary Notes The following supplementary notes are further disclosed with respect to the embodiments including the above embodiments.

(Appendix 1)
A program for causing a computer to execute a process for creating an analysis model of a board having a wiring pattern,
Dividing the substrate into a plurality of first regions;
For each of the plurality of first regions, the first wiring pattern in each first region is converted into a first pattern identifier corresponding to the first wiring pattern,
Based on the converted first pattern identifier, it is determined whether or not the adjacent first regions included in the plurality of first regions can be combined,
When it is determined that the combination is possible, the adjacent first regions are combined.
A model creation program for causing a computer to execute processing.

(Appendix 2)
The first wiring pattern in each first region is converted into the first pattern identifier using a first pattern table that associates the first wiring pattern in each first region with the first pattern identifier. ,
The model creation program according to appendix 1, which causes the computer to execute processing.

(Appendix 3)
For the second area obtained by combining the first areas, a second pattern identifier corresponding to the second wiring pattern in the second area is set.
Replacing the set second pattern identifier with the first pattern identifier and replacing the second area with the first area, and then repeatedly combining the first areas based on the first pattern identifier;
The model creation program according to appendix 1 or appendix 2, which causes the computer to execute processing.

(Appendix 4)
Using a second pattern table that associates the combination of the first pattern identifiers of the adjacent first regions with the second pattern identifier of the second region obtained by combining the first regions of the combination, Setting the second pattern identifier for the second region;
The model creation program according to appendix 3, which causes the computer to execute processing.

(Appendix 5)
It is determined that the combination of the first pattern identifiers associated with the second pattern identifier in the second pattern table can be combined, while the second pattern identifier is associated in the second pattern table. It is determined that the combination of the first pattern identifiers that are not combined is not possible,
The model creation program according to appendix 4, which causes the computer to execute processing.

(Appendix 6)
A model creation method for creating an analysis model of a board having a wiring pattern,
Computer
Dividing the substrate into a plurality of first regions;
For each of the plurality of first regions, the first wiring pattern in each first region is converted into a first pattern identifier corresponding to the first wiring pattern,
Based on the converted first pattern identifier, it is determined whether or not the adjacent first regions included in the plurality of first regions can be combined,
A model creation method in which the adjacent first regions are coupled when it is determined that they can be coupled.

(Appendix 7)
The computer uses the first pattern table associating the first wiring pattern in each first region with the first pattern identifier to assign the first wiring pattern in each first region to the first pattern. The model creation method according to attachment 6, wherein the model is converted into an identifier.

(Appendix 8)
The computer
For the second area obtained by combining the first areas, a second pattern identifier corresponding to the second wiring pattern in the second area is set.
Replacing the set second pattern identifier with the first pattern identifier and replacing the second area with the first area, and then repeatedly combining the first areas based on the first pattern identifier; The model creation method according to appendix 6 or appendix 7.

(Appendix 9)
The computer associates the combination of the first pattern identifiers of the adjacent first regions with the second pattern identifier of the second region obtained by combining the first regions of the combination. The model creation method according to appendix 8, wherein the second pattern identifier is set for the second region using

(Appendix 10)
The computer determines that the combination of the first pattern identifiers associated with the second pattern identifiers in the second pattern table can be combined, while the second pattern identifiers in the second pattern table. The model creation method according to appendix 9, wherein it is determined that the combination of the first pattern identifiers that are not associated with each other cannot be combined.

(Appendix 11)
An information processing apparatus for creating an analysis model of a board having a wiring pattern,
A processing unit and a storage unit;
The processor is
Dividing the substrate into a plurality of first regions;
For each of the plurality of first regions, the first wiring pattern in each first region is converted into a first pattern identifier corresponding to the first wiring pattern,
Based on the converted first pattern identifier, it is determined whether or not the adjacent first regions included in the plurality of first regions can be combined,
An information processing apparatus that combines the adjacent first regions when it is determined that they can be combined.

(Appendix 12)
The storage unit stores a first pattern table that associates the first wiring pattern and the first pattern identifier in each first region;
The information processing according to appendix 11, wherein the processing unit converts the first wiring pattern in each first region into the first pattern identifier using the first pattern table stored in the storage unit. apparatus.

(Appendix 13)
The processor is
For the second area obtained by combining the first areas, a second pattern identifier corresponding to the second wiring pattern in the second area is set.
Replacing the set second pattern identifier with the first pattern identifier and replacing the second area with the first area, and then repeatedly combining the first areas based on the first pattern identifier; The information processing apparatus according to appendix 11 or appendix 12.

(Appendix 14)
The storage unit associates the combination of the first pattern identifiers of the adjacent first regions with the second pattern identifier of the second region obtained by combining the first regions of the combination. Save the table,
The information processing apparatus according to appendix 13, wherein the processing unit sets the second pattern identifier for the second region using the second pattern table stored in the storage unit.

(Appendix 15)
The processing unit determines that the combination of the first pattern identifiers associated with the second pattern identifiers in the second pattern table can be combined, while the second pattern table includes the second pattern identifiers. The information processing apparatus according to appendix 14, wherein it is determined that the combination of the first pattern identifiers that are not associated with identifiers cannot be combined.

10 Computer (Information processing device with model creation function)
11 Processor (Processor)
12 RAM (storage unit)
13 HDD (storage unit)
14 graphic processing device 14a monitor 15 input interface 15a keyboard 15b mouse 16 optical drive device 16a optical disk 17 device connection interface 17a memory device 17b memory reader / writer 17c memory card 18 network interface 18a network 19 bus 20 processing unit 21 division unit 22 conversion unit 23 Composition unit 24 Equivalent thermal conductivity calculation unit 25 Output unit 30 Storage unit 31 Two-dimensional wiring pattern image (wiring pattern image, substrate, substrate image)
31a cell (rectangular area; first area)
31b cell (rectangular area; second area)
32 cell pattern table (first pattern table)
33 Combined pattern table (second pattern table)
34 Material property data 35 Thermal analysis model (analysis model)

Claims (7)

A program for causing a computer to execute a process for creating an analysis model of a board having a wiring pattern,
Dividing the substrate into a plurality of first regions;
For each of the plurality of first regions, the first wiring pattern in each first region is converted into a first pattern identifier corresponding to the first wiring pattern,
Based on the converted first pattern identifier, it is determined whether or not the adjacent first regions included in the plurality of first regions can be combined,
When it is determined that the first areas can be combined, the adjacent first regions are combined.
A model creation program for causing a computer to execute processing. The first wiring pattern in each first region is converted into the first pattern identifier using a first pattern table that associates the first wiring pattern in each first region with the first pattern identifier. ,
The model creation program according to claim 1 which makes a computer perform processing. For the second area obtained by combining the first areas, a second pattern identifier corresponding to the second wiring pattern in the second area is set.
Replacing the set second pattern identifier with the first pattern identifier and replacing the second area with the first area, and then repeatedly combining the first areas based on the first pattern identifier;
The model creation program according to claim 1 or 2 which makes said computer perform processing. Using a second pattern table that associates the combination of the first pattern identifiers of the adjacent first regions with the second pattern identifier of the second region obtained by combining the first regions of the combination, Setting the second pattern identifier for the second region;
The model creation program according to claim 3 which makes said computer perform processing. The combination of the first pattern identifiers associated with the second pattern identifier in the second pattern table is determined to be combinable, while the second pattern identifier is associated in the second pattern table. It is determined that the combination of the first pattern identifiers that are not combined is not possible,
The model creation program according to claim 4 which makes said computer perform processing. A model creation method for creating an analysis model of a board having a wiring pattern,
Computer
Dividing the substrate into a plurality of first regions;
For each of the plurality of first regions, the first wiring pattern in each first region is converted into a first pattern identifier corresponding to the first wiring pattern,
Based on the converted first pattern identifier, it is determined whether or not the adjacent first regions included in the plurality of first regions can be combined,
A model creation method in which the adjacent first regions are coupled when it is determined that they can be coupled. An information processing apparatus for creating an analysis model of a board having a wiring pattern,
A processing unit and a storage unit;
The processor is
Dividing the substrate into a plurality of first regions;
For each of the plurality of first regions, the first wiring pattern in each first region is converted into a first pattern identifier corresponding to the first wiring pattern,
Based on the converted first pattern identifier, it is determined whether or not the adjacent first regions included in the plurality of first regions can be combined,
An information processing apparatus that combines the adjacent first regions when it is determined that they can be combined.

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