JP2016034005A - Method for manufacturing wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board which allows a semiconductor device to be operated with stability.SOLUTION: A method for manufacturing a wiring board comprises the steps of: preparing a dielectric plate 1 having many product forming regions M, and a marginal region N surrounding each product forming region M; forming, in each product forming region M, first and second pads 4 and 5, and wiring conductors 2 including inter-pad connection conductors 6, and forming conductors 9 for electrical conduction which are connected to the second pads 5 and extend from the product forming region M to the marginal region N; forming a solder resist layer 3 so that the first and second pads 4 and 5 and the conductors 9 for electrical conduction in the marginal region N are exposed, and at least other parts of the wiring conductors 2 are covered; depositing an electrolytic gold plating layer 7 on each second pad 5; and etching the conductors 9 for electrical conduction so that parts of the conductors 9 for electrical conduction in the marginal region N are left at least electrically connected to parts of the second pads 5.SELECTED DRAWING: Figure 10

Description

  The present invention relates to a method of manufacturing a wiring board for mounting a semiconductor element or the like.

  12 (a) and 12 (b) show a conventional wiring board B for mounting a semiconductor element such as a semiconductor integrated circuit element. Here, FIG. 12A is a cross-sectional view taken along the line XX shown in FIG. As shown in FIG. 12A, the wiring board B has a semiconductor element mounting portion 21a for mounting a semiconductor element at the center of the upper surface and a circuit board mounting portion 21b for mounting a circuit board around the semiconductor element mounting portion 21b. The insulating plate 21 having a plurality of through holes 21c penetrating vertically, the upper and lower surfaces of the insulating plate 21 and the wiring conductor 22 deposited in the through holes 21c, and the solder deposited on the upper and lower surfaces of the insulating plate 21 And a resist layer 23. The insulating plate 21 and the solder resist layer 23 are made of a resin-based insulating material containing a thermosetting resin such as an epoxy resin. The wiring conductor 22 is made of copper.

The wiring conductor 22 deposited on the upper surface of the insulating plate 21 includes a first pad 24 and a second pad 25 as shown in FIG. The first pad 24 and the second pad 25 are exposed in the openings 23a and 23b provided in the solder resist layer 23 on the upper surface side, respectively. The first pad 24 is disposed on the semiconductor element mounting portion 21a, and the electrodes of the semiconductor element are connected via solder. The second pad 25 is disposed on the circuit board mounting portion 21b, and a connection pad of another circuit board is connected via solder. The second pads 25 and some of the first pads 24 are electrically connected to each other via inter-pad connection conductors 26. The surface of the first pad 24 is exposed from copper, and the surface of the second pad 25 is covered with a gold plating layer 27 by an electrolytic plating method.
Then, the electrode of the semiconductor element is connected to the first pad 24 via solder, and the connection pad of another circuit board is connected to the second pad 25 via solder, whereby the semiconductor element and another circuit are connected. A composite substrate on which the substrate is mounted is completed. The first pad 24 has a small area because it is connected to the electrode of the semiconductor element, whereas the second pad 25 is connected to a connection pad of another circuit board, so that the first pad 24 is connected. It has a much larger area.

  The wiring conductor 22 attached to the lower surface of the insulating plate 21 includes a plurality of third pads 28. The third pad 28 is exposed in the opening 23c provided in the solder resist layer 23 on the lower surface side. The composite substrate described above is mounted on the external substrate by connecting the electrode of the external substrate to the third pad 28 via solder.

Next, an example of a method for manufacturing such a conventional wiring board B will be described with reference to FIGS.
In this wiring board B, in consideration of productivity, a plurality of product forming areas M, which are individual products, are arranged vertically and horizontally, and a disposal margin area having a predetermined width surrounding each product forming area M. It is produced from a collective substrate consisting of N. A large number of wiring boards B are produced simultaneously by cutting the aggregate substrate along the product formation region M.
In this example, for the sake of convenience, one product forming region M and the surrounding margin region N are illustrated and described.
Moreover, each figure (a) is sectional drawing in the YY cut line in each figure (b).

  First, as shown in FIG. 13, an insulating plate 21 having a plurality of through holes 21c is prepared.

  Next, as shown in FIG. 14, a plurality of wiring conductors 22 including the first pad 24, the second pad 25, and the inter-pad connection conductor 26 are formed in the product formation region M, and the product formation region M and the waste are discarded. A conductive conductor 29 extending from the second pad 25 to the disposal margin region N is formed in the substitution region N. The conductive conductors 29 are electrically connected to each other in the discard margin region N.

  Next, as shown in FIG. 15, a solder resist layer 23 for exposing the first and second pads 24, 25 and the conductive conductor 29 in the disposal margin region N is formed in the product formation region M on the insulating plate 21. Form.

  Next, as shown in FIG. 16, a plating resist layer R <b> 1 that exposes the second pad 25 and covers the first pad 24 and the conductive conductor 29 in the disposal margin region N is formed.

  Next, as shown in FIG. 17, a gold plating layer 27 is deposited on the surface of the second pad 25 exposed from the plating resist layer R1 by electrolytic plating.

  Next, as shown in FIG. 18, the plating resist layer R1 is removed.

  Next, as shown in FIG. 19, the first and second pads 24 and 25 are covered, and a part of the conductive conductor 29 in the disposal margin region N and the conductive conductor 29 near the outer periphery of the product forming region M is formed. An etching resist layer R2 that exposes the film is formed.

  Next, as shown in FIG. 20, the conductive conductor 29 exposed from the etching resist layer R2 is removed by etching to make the second pads 25 electrically independent from each other.

  Next, as shown in FIG. 21, the etching resist layer R2 is removed with, for example, an etching solution. Thereafter, by cutting along the product formation region M, a wiring board B as shown in FIG. 12 is formed.

By the way, in the above manufacturing method, for example, when the etching resist layer R2 is removed, the first pad 24 connected to the second pad 25 is corroded by the well-known galvanic corrosion and becomes small. The first pad 24 may not be formed to a predetermined size.
Galvanic corrosion is a phenomenon in which a base metal is corroded when metals having different potentials form an electric circuit through an electrolyte solution. Is big.
In the above-described manufacturing method, the first pad 24 with a small area where copper, which is a base metal, is exposed, and the second pad 25, with a large area where gold, which is a noble metal, is exposed, are connected between the pads 26. As a result of being electrically connected to each other via, for example, an electric circuit is formed via the etching solution used to remove the above-described etching resist layer R2, and copper, which is a base metal, is greatly corroded.
When the first pad 24 cannot be formed to a predetermined size, the connection between the semiconductor element and the first pad 24 may be incomplete, and the semiconductor element may not be stably operated.

JP 2005-79129 A

  According to the present invention, a pad to which an electrode of a semiconductor element is connected is formed in a predetermined size, whereby the electrode of the semiconductor element and the pad are completely connected. Accordingly, it is an object of the present invention to provide a method for manufacturing a wiring board capable of stably operating a semiconductor element.

The method for manufacturing a wiring board according to the present invention includes a plurality of first pads with copper exposed on the surface and a plurality of second pads with a gold plating layer deposited on the surface. A method of manufacturing a wiring board in which the first pad and the second pad are electrically connected to each other via an inter-pad connecting conductor, and the following steps (1) to (8) It is characterized by performing.
(1) A step of preparing an insulating plate in which a large number of product forming regions to be the wiring board are arranged vertically and horizontally with a disposal margin region having a predetermined width around each of the product forming regions. A plurality of wiring conductors including the first and second pads and the inter-pad connecting conductors are formed in the formation region, and are electrically connected to the second pads, respectively, and are discarded from the product formation region. (3) exposing the first and second pads and the conductive conductor in the discard margin region to individually extend to the region and forming a conductive conductor electrically connected to each other in the discard margin region; And forming a solder resist layer covering at least the remaining portion of the wiring conductor (4) exposing the second pad and the first pad And (5) depositing the gold plating layer on the surface of the second pad exposed from the plating resist layer by an electrolytic plating method. Step (6) Step of removing the plating resist layer (7) Step of forming an etching resist layer that covers the first and second pads and exposes the conductive conductor in the abandonment region (8) The conductive conductor exposed from the etching resist layer is etched so that the second pads are electrically independent from each other, and at least a part of the conductive conductor in the disposal margin region is part of the second pad. The process of leaving it exposed while being electrically connected to the pad

According to the method for manufacturing a wiring board of the present invention, at the time of etching the conductive conductor, at least a part of the conductor is left in the margin area while being electrically connected to the second pad. Therefore, in the first and second pads connected to each other, the exposed area of the second pad covered with the gold plating layer is matched with a part of the first pad connected to this and the conductive conductor. The difference from the exposed area can be reduced.
For this reason, the corrosion of the 1st pad by the above-mentioned galvanic corrosion can be controlled.
As a result, it is possible to form the first pad to a predetermined size and to completely connect the electrode of the semiconductor element and the first pad, and to stably operate the semiconductor element. The manufacturing method of can be provided.

1A and 1B are a schematic cross-sectional view and a top view showing an example of an embodiment of a wiring board according to the present invention. 2A and 2B are a schematic cross-sectional view and a top view showing an example of a form for each manufacturing process of the wiring board of the present invention. FIGS. 3A and 3B are a schematic cross-sectional view and a top view showing an example of a form for each manufacturing process of the wiring board of the present invention. FIGS. 4A and 4B are a schematic cross-sectional view and a top view showing an example of a form for each manufacturing process of the wiring board of the present invention. FIGS. 5A and 5B are a schematic cross-sectional view and a top view showing an example of a form for each manufacturing process of the wiring board of the present invention. 6A and 6B are a schematic cross-sectional view and a top view showing an example of a form for each manufacturing process of the wiring board of the present invention. FIGS. 7A and 7B are a schematic cross-sectional view and a top view showing an example of a form for each manufacturing process of the wiring board of the present invention. FIGS. 8A and 8B are a schematic cross-sectional view and a top view showing an example of a form for each manufacturing process of the wiring board of the present invention. FIGS. 9A and 9B are a schematic cross-sectional view and a top view showing an example of a form for each manufacturing process of the wiring board of the present invention. FIGS. 10A and 10B are a schematic cross-sectional view and a top view showing an example of a form for each manufacturing process of the wiring board of the present invention. FIGS. 11A and 11B are enlarged top views of main parts showing an example of another embodiment of the present invention. 12A and 12B are a schematic cross-sectional view and a top view showing an example of an embodiment of a conventional wiring board. FIGS. 13A and 13B are a schematic cross-sectional view and a top view showing an example of a form for each manufacturing process of a conventional wiring board. 14 (a) and 14 (b) are a schematic cross-sectional view and a top view showing an example of a form for each manufacturing process of a conventional wiring board. 15 (a) and 15 (b) are a schematic cross-sectional view and a top view showing an example of a form for each manufacturing process of a conventional wiring board. 16 (a) and 16 (b) are a schematic cross-sectional view and a top view showing an example of a form for each manufacturing process of a conventional wiring board. FIGS. 17A and 17B are a schematic cross-sectional view and a top view showing an example of a form for each manufacturing process of a conventional wiring board. 18 (a) and 18 (b) are a schematic cross-sectional view and a top view showing an example of a form for each manufacturing process of a conventional wiring board. FIGS. 19A and 19B are a schematic cross-sectional view and a top view showing an example of a form for each manufacturing process of a conventional wiring board. 20 (a) and 20 (b) are a schematic cross-sectional view and a top view showing an example of a form for each manufacturing process of a conventional wiring board. FIGS. 21A and 21B are a schematic cross-sectional view and a top view showing an example of a form for each manufacturing process of a conventional wiring board.

Next, an example of an embodiment of the wiring board according to the present invention will be described in detail with reference to FIGS. Here, FIG. 1A is a cross-sectional view taken along the line VV shown in FIG.
As shown in FIG. 1A, the wiring board A has a semiconductor element mounting portion 1a for mounting a semiconductor element at the center of the upper surface and an external substrate mounting portion 1b for mounting an external substrate around the semiconductor element mounting portion 1b. Insulating plate 1 having a plurality of through holes 1c penetrating vertically, wiring conductor 2 deposited in the upper and lower surfaces of insulating plate 1 and through hole 1c, and solder deposited on the upper and lower surfaces of insulating plate 1 And a resist layer 3. The insulating plate 1 and the solder resist layer 3 are made of a resin-based insulating material containing a thermosetting resin such as an epoxy resin. The wiring conductor 2 is made of copper.
The insulating plate 1 has a single-layer structure in this example, but may have a multilayer structure in which a plurality of insulating layers made of the same or different electrical insulating materials are stacked.

The wiring conductor 2 deposited on the upper surface of the insulating plate 1 includes a first pad 4 and a second pad 5 as shown in FIG. The first pad 4 and the second pad 5 are exposed in the openings 3a and 3b provided in the solder resist layer 3 on the upper surface side, respectively. The first pad 4 is disposed on the semiconductor element mounting portion 1a, and the electrodes of the semiconductor element are connected via solder. The second pad 5 is disposed on the circuit board mounting portion 1b, and a connection pad of another circuit board is connected via solder. The second pads 5 and some of the first pads 4 are electrically connected to each other via inter-pad connection conductors 6. The surface of the first pad 4 is exposed from copper, and the surface of the second pad 5 is coated with a gold plating layer 7 by electrolytic plating.
Then, the electrode of the semiconductor element is connected to the first pad 4 via solder, and the connection pad of another circuit board is connected to the second pad 5 via solder, whereby the semiconductor element and another circuit are connected. A composite substrate on which the substrate is mounted is completed. The first pad 4 has a small area because it is connected to the electrode of the semiconductor element, whereas the second pad 5 is connected to a connection pad of another circuit board, so that the first pad 4 The area is much larger than 4.

  The wiring conductor 2 attached to the lower surface of the insulating plate 1 includes a plurality of third pads 8. The third pad 8 is exposed in the opening 3c provided in the solder resist layer 3 on the lower surface side. The composite substrate described above is mounted on the external substrate by connecting the electrode of the external substrate to the third pad 8 via solder.

Next, an example of the method for manufacturing the wiring board A according to the present invention will be described with reference to FIGS.
In this wiring board A, in consideration of productivity, a plurality of product forming areas M, which are individual products, are arranged vertically and horizontally, and a disposal margin area having a predetermined width surrounding each product forming area M. It is produced from a collective substrate consisting of N. Then, by cutting the collective substrate along the product formation region M, a large number of wiring boards A are simultaneously produced.
In this example, for the sake of convenience, one product forming area M and the surrounding margin area Y are illustrated and described.
Moreover, each figure (a) is sectional drawing in the WW cut line in each figure (b).

First, as shown in FIG. 2, an insulating plate 1 having a plurality of through holes 1c is prepared.
The insulating plate 1 is formed by thermosetting an insulator in which a glass cloth is impregnated with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. The through hole 1c is formed by drilling, laser processing, or blasting. The diameter of the through hole 1c is about 50 to 250 μm.

Next, as shown in FIG. 3, a plurality of wiring conductors 2 including the first pad 4, the second pad 5, and the inter-pad connection conductor 6 are formed in the product formation region M, and the product formation region M and the waste are discarded. A conductive conductor 9 extending from the second pad 5 to the disposal margin region N is formed in the substitution region N. The conductive conductors 9 are electrically connected to each other in the discard margin region N.
The wiring conductor 2 is formed by, for example, a well-known subtractive method. The width of the wiring conductor 2 is about 10 to 30 μm, and the thickness is about 10 to 20 μm.

Next, as shown in FIG. 4, in the product formation region M on the insulating plate 1, the first and second pads 4, 5 and the conductor for conduction 9 in the disposal margin region N and the vicinity of the outer periphery of the product formation region M A solder resist layer 3 exposing a part of the conductive conductor 9 is formed.
The solder resist layer 3 is formed by, for example, applying or pasting a resin paste or film made of an electrically insulating material containing a thermosetting resin such as an epoxy resin or a polyimide resin on the insulating plate 1 and thermosetting it. Is done.

Next, as shown in FIG. 5, a plating resist layer R <b> 1 that exposes the second pad 5 and covers the first pad 4 and the conductive conductor 9 in the disposal margin region N is formed.
The plating resist layer R1 is formed by sticking a photosensitive resin film on the insulating plate 1 using a vacuum press machine and exposing and developing so as to have a pattern exposing the second pad 5. Is done.

Next, as shown in FIG. 6, a gold plating layer 7 is deposited on the surface of the second pad 5 exposed from the plating resist layer R1 by electrolytic plating.
When the gold plating layer 7 is formed, it may be deposited on the surface of the second pad 5 in the order of electrolytic nickel plating and electrolytic gold plating, for example. The thickness of the gold plating layer 7 is about 1 to 3 μm.

  Next, as shown in FIG. 7, the plating resist layer R1 is removed. When removing, an etching solution such as a sodium hydroxide aqueous solution may be used.

Next, as shown in FIG. 8, an etching resist layer R <b> 2 that covers the first and second pads 4 and 5 and exposes the conductive conductor 9 in the disposal margin region N is formed.
At this time, a part of the conductive conductor 9 connected to the second pad 5 is covered with the etching resist layer R2 in the disposal margin region N.
The etching resist layer R2 is formed by sticking a photosensitive resin film on the insulating plate 1 using a vacuum press and discarding a part of the conductive conductor 9 connected to the second pad 5 in the margin region N. And is exposed and developed so as to have a pattern exposing the remaining conductive conductor 9.

  Next, as shown in FIG. 9, the conductive conductor 9 exposed from the etching resist layer R2 is removed by etching. Thereby, each 2nd pad 5 will be in an electrically independent state. Further, a part of the conductive conductor 9 in the disposal margin region N remains in a state of being electrically connected to the second pad 5.

Next, as shown in FIG. 10, the etching resist layer R2 is removed. For removal, an etching solution such as a sodium hydroxide aqueous solution may be used.
Thereafter, by cutting along the product formation region M, a wiring board A as shown in FIG. 1 is formed. For the cutting, for example, a dicing apparatus may be used.

As described above, according to the method for manufacturing a wiring board of the present invention, at the time of etching the conductive conductor 9, at least a part of the conductor 9 is left in the disposal margin region N while being electrically connected to the second pad 5. ing. Therefore, in the first and second pads 4 and 5 connected to each other, the exposed area of the second pad 5 covered with the gold plating layer 7, and the first pad 4 connected to the first pad 4 and the conduction pad The difference from the exposed area where a part of the conductor 9 is combined can be reduced.
For this reason, the corrosion of the 1st pad 4 by the galvanic corrosion mentioned above can be suppressed. As a result, the first pad 4 can be formed in a predetermined size so that the semiconductor element and the first pad 4 can be completely connected and the semiconductor element can be stably operated. Can be provided.
By the way, it is known that the influence of galvanic corrosion is large when the surface area of the noble metal with respect to the base metal is 15 times or more, and the influence is small when the surface area is less than 15 times.
For this reason, when a part of the conductive conductor 9 is left in the disposal margin region N, the exposed area of the first pad 4 and a part of the conductive conductor 9 is 1/15 of the area of the second pad 5. It is important to leave it larger than twice. The effect which suppresses galvanic corrosion becomes it low that it is 1/15 times or less.
In addition, the area of the second pad 5 is 15 times as large as the area of the first pad 4 and the area of the second pad 5 is 15 times as large as the area of the first pad 4. In some cases, the second pads 5 having a small area, which is less than the above, are mixed. In this case, only a part of the conductive conductor 9 connected to the second pad 5 having a large area may be left. Thereby, the galvanic corrosion of the 1st pad 4 electrically connected with the 2nd pad 5 of a large area can be suppressed.

In addition, this invention is not limited to an example of above-mentioned embodiment, A various change is possible if it is a range which does not deviate from the summary of this invention. For example, in the example of the above-described embodiment, an example in which a part of the conductive conductor 9 connected to the second pad 5 is left in the discard margin region N is shown, but as shown in FIG. A dummy portion D that is branched and exposed from the conductive conductor 19 is formed. As shown in FIG. 11B, the dummy portion D and the second pad 15 are formed when the conductive conductor 19 is etched. You can leave it connected.

DESCRIPTION OF SYMBOLS 1 Insulation board 2 Wiring conductor 3 Solder resist layer 4 1st pad 5 2nd pad 6 Inter-pad connection conductor 7 Gold plating layer 9 Conductive conductor A Wiring board M Product formation area N Throw margin R1 Plating resist R2 Etching resist

Claims (4)

A plurality of first pads having copper exposed on the surface, and a plurality of second pads having a gold plating layer deposited on the surface, a part of the first pads, A wiring board manufacturing method in which two pads are electrically connected to each other via an inter-pad connecting conductor, wherein the following steps (1) to (8) are performed: Production method.
(1) A step of preparing an insulating plate in which a large number of product forming regions to be the wiring board are arranged vertically and horizontally with a disposal margin region having a predetermined width around each of the product forming regions. A plurality of wiring conductors including the first and second pads and the inter-pad connection conductors are formed in the formation region, and are electrically connected to each of the second pads and discarded from the product formation region. (3) forming conductive conductors that extend individually to the surrogate area and are electrically connected to each other in the discard margin area; and (3) the first and second pads and the conductive conductor in the discard margin area. And a step of forming a solder resist layer covering at least the remaining portion of the wiring conductor (4) exposing the second pad and exposing the first pad And (5) depositing the gold plating layer on the surface of the second pad exposed from the plating resist layer by electrolytic plating. (6) Step of removing the plating resist layer (7) Step of forming an etching resist layer that covers the first and second pads and exposes the conductive conductor in the margin region (8) The conductive conductor exposed from the etching resist layer is etched so that the second pads are electrically independent from each other, and at least a part of the conductive conductor in the disposal margin region is part of the second pad. Leaving it exposed to be electrically connected to the pad   In the step (8), a part of the conductive conductor left exposed so as to be electrically connected to the second pad is the first electrically connected to the part. 2. The method of manufacturing a wiring board according to claim 1, wherein an exposed area combined with the pad is larger than 1/15 times an area of the second pad electrically connected to the part.   The second pad includes a large area pad having an area of 15 times or more of the first pad and a small area pad having an area of less than 15 times the first pad. In the step (8), the second pad 3. The method of manufacturing a wiring board according to claim 1, wherein a part of the conductor is left in a state of being electrically connected only to the large area pad.   The conductive conductor in the discard margin region includes a dummy portion that is branched and exposed from the conductive conductor, and the dummy portion is electrically connected to the second pad in the step (8). 4. The method for manufacturing a wiring board according to claim 1, wherein the wiring board is left in a state.

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