JP2013153055A - Manufacturing method of wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a wiring board which allows for excellent deposition of a tin plating layer on a first connection pad, when depositing a tin plating layer on a first connection pad formed on one principal surface of a wiring board by electrolytic plating, and depositing a nickel plating layer and a gold plating layer sequentially on the other principal surface of a wiring board by electrolytic plating.SOLUTION: A plating conduction wire 9 for electrically connecting first connection pads 5 formed on the first principal surface and second connection pads 6 formed on the second principal surface commonly is formed only on the second principal surface. Subsequently, charges for electrolytic plating are supplied via the plating conduction wire 9, in a state where a plating mask M2 for exposing the first connection pads 5 and covering the second connection pads 6 and the plating conduction wire 9 is formed only on the second principal surface, thus depositing an electrolytic tin plating layer 7 on the surface of the first connection pads 5.

Description

  The present invention relates to a method of manufacturing a wiring board used for mounting a semiconductor element.

  Conventionally, as shown in FIGS. 7A and 7B, a wiring board 20 on which a semiconductor element S having a peripheral arrangement of electrode terminals T on a lower surface outer periphery is mounted by flip chip connection has a large number of through holes 12. A solder resist layer is formed by depositing a plurality of wiring conductors 13 made of copper from the upper surface to the lower surface of an insulating substrate 11 made of a resin-based insulating material, and further exposing a part of the wiring conductors 13 on the upper and lower surfaces thereof. 14 is attached.

  A mounting portion for mounting the semiconductor element S is provided at the center of the upper surface of the wiring board 20, and a large number of semiconductor element connection pads 15 for connecting to the electrodes T of the semiconductor element S are provided on the mounting portion. It is formed by a part of the wiring conductor 13. The semiconductor element S is mounted on the wiring board 20 by bringing the electrodes T of the semiconductor element S into contact with the semiconductor element connection pads 15 and connecting them via solder.

  The lower surface of the wiring board 20 serves as an external connection surface for connection to an external electric circuit board, and a large number of external connection pads 16 for connection to the external electric circuit board are provided on the external connection surface. It is formed by a part of the wiring conductor 13. Then, the wiring board 20 is mounted on the external electric circuit board by connecting the external connection pads 16 and the external electric circuit board via solder.

  By the way, in such a wiring board 20, in order to prevent the oxidation of the semiconductor element connection pad 15 and to improve the connection with the electrode T of the semiconductor element S, a tin is formed on the exposed surface of the semiconductor element connection pad 15. In some cases, the plating layer 17 is deposited. Nickel in which a nickel plating layer and a gold plating layer are sequentially deposited on the exposed surface of the external connection pad 16 in order to prevent oxidation of the external connection pad 16 and improve the connection with the external electric circuit board. -A gold plating layer 18 may be deposited.

  Thus, in order to deposit the tin plating layer 17 on the surface of the semiconductor element connection pad 15 and to deposit the nickel-gold plating layer 18 on the surface of the external connection pad 16, an electrolytic plating method has been conventionally employed. Yes.

  Here, in the conventional wiring board 20, the tin plating layer 17 is deposited on the surface of the semiconductor element connection pad 15 by electrolytic plating, and the nickel-gold plating layer 18 is coated on the surface of the external connection pad 16 by electrolytic plating. A method of wearing will be described with reference to FIGS.

  First, as shown in FIG. 8A, a wiring board panel 20P is prepared in which a large number of product areas X to be the wiring board 20 are integrally formed around the product area X via a margin area Y. In each product region X, the semiconductor element connection pad 15 is formed on the upper surface, and the external connection pad 16 is formed on the lower surface. 8 to 13, for the sake of simplicity, one product area X and the surrounding margin area Y are partially shown.

  As shown in FIG. 10, the wiring board panel 20 </ b> P extends from some of the wiring conductors 13 in the product region X on the upper surface of the insulating substrate 11 to the disposal margin region Y and is electrically connected in common in the disposal margin region Y. A plated conductive wire 19 made of copper is provided. The plating conductive line 19 in the disposal margin region Y is completely exposed from the solder resist layer 14. In addition, some of the different wiring conductors 13 in the product region X are connected by the plating conduction wire 19, and a part of the plating conduction wire 19 is exposed from the opening 14 a provided in the solder resist layer 14.

  Furthermore, as shown in FIG. 11, similarly, on the lower surface of the insulating substrate 11, some of the wiring conductors 13 in the product region X extend to the disposal margin region Y and are electrically connected in common in the disposal margin region Y. A plating conduction line 19 made of copper is provided. The plating conductive line 19 in the disposal margin region Y is completely exposed from the solder resist layer 14. In addition, some of the different wiring conductors 13 in the product region X are connected by the plating conduction wire 19, and a part of the plating conduction wire 19 is exposed from the opening 14 a provided in the solder resist layer 14.

  Each of the semiconductor element connection pads 15 and the external connection pads 16 in the product region X are electrically connected to each other through the through holes 12, and the semiconductor element connection pads 15 and the external connection pads connected to each other are connected. All of the semiconductor element connection pads 15 and the external connection pads 16 are electrically and commonly connected by electrically connecting one of the 16 through the plating conduction line 19.

  Next, as shown in FIG. 8B, a first plating mask M1 is formed on the upper and lower surfaces of the wiring board panel 20P. The first plating mask M1 covers the entire upper surface of the wiring board panel 20P and also covers the exposed portion of the plating conductive line 19 from the solder resist layer 14 on the lower surface. As a result, only the external connection pads 16 in the product region X are selectively exposed.

  Next, as shown in FIG. 8 (c), a nickel plating layer and a gold plating layer are sequentially deposited on the surface of the external connection pad 16 exposed from the first plating mask M1 by an electrolytic plating method. Layer 18 is formed. In this case, the electroplating is performed by supplying the electric charge for electroplating to each external connection pad 16 through the plating conductive line 19. At this time, the nickel-gold plating layer 18 is not deposited on the semiconductor element connection pad 15 and the plating conductive line 19 covered with the first plating mask M1.

  Next, as shown in FIG. 8D, the first plating mask M1 is removed. As a result, a wiring board panel 20P in which the nickel-gold plating layer 18 is deposited only on the external connection pads 16 is obtained.

  Next, as shown in FIG. 8E, a second plating mask M2 is formed on the upper and lower surfaces of the wiring board panel 20P. The second plating mask M2 covers the entire lower surface of the wiring board panel 20P and also covers the exposed portion of the plating conductive line 19 from the solder resist layer 14 on the upper surface. Further, the semiconductor element connection pad 15 is exposed. As a result, only the semiconductor element connection pads 15 in the product region X are selectively exposed.

  Next, as shown in FIG. 9F, a tin plating layer 17 is deposited on the surface of the semiconductor element connection pad 15 exposed from the second plating mask M2 by electrolytic plating. In this case, electrolytic plating is performed by supplying electric charges for electrolytic plating to the respective semiconductor element connection pads 15 through the plating conductive lines 19. At this time, the tin plating layer 17 is not deposited on the external connection pads 16 and the plating conductive lines 19 covered with the second plating mask M2.

  Next, as shown in FIG. 9G, the second plating mask M2 is removed. As a result, a wiring board panel 20P in which the nickel-gold plating layer 18 is applied to the external connection pads 16 and the tin plating layer 17 is applied to the semiconductor element connection pads 15 is obtained. At this time, neither the nickel-gold plating layer 18 nor the tin plating layer 17 is deposited on the exposed portion of the plating conductive wire 19, and the copper is exposed.

  Next, as shown in FIG. 9H, an etching mask M3 is formed on the upper and lower surfaces of the wiring board panel 20P. The etching mask M3 covers the semiconductor element connection pads 15 and the external connection pads 16, and exposes the plating conductive lines 19 exposed from the solder resist layer 14.

  Next, as shown in FIG. 9I, the plating conductive line 19 exposed from the etching mask M3 is removed by etching. As a result, as shown in FIGS. 12 and 13, predetermined ones of the semiconductor element connection pads 15 and the external connection pads 16 are electrically independent from each other.

  Finally, as shown in FIG. 9 (j), the etching mask M3 is removed, and then the wiring board panel 20P is cut along the boundary of each product region X to thereby form the wiring board as shown in FIG. 20 is obtained. The plating masks M1 and M2 and the etching mask M3 are obtained by pressing a dry film resist having photosensitivity to the upper and lower surfaces of the wiring board panel 20P and exposing and developing it into a predetermined pattern by using a photolithography technique. It is formed by doing.

  However, according to such a conventional method of manufacturing the wiring substrate 20, when the second plating mask M2 is formed, as shown in the enlarged cross-sectional view of the main part in FIG. 14, the solder resist layer in the second plating mask M2 14, the component that inhibits the deposition of electrolytic tin plating is eluted from the joint portion with the developer for forming the mask M2, and the eluted component adheres to the semiconductor element connection pad 15 in the vicinity of the plating squeeze M2, As a result, the deposition of the tin plating layer 17 on the semiconductor element connection pad 15 is hindered, and it may be difficult to satisfactorily deposit the tin plating layer 17 on all the semiconductor element connection pads 15.

JP 2010-10346 A

  The problem to be solved by the present invention is that a tin plating layer is deposited on the first connection pad formed on one main surface of the wiring board by an electrolytic plating method and is formed on the other main surface of the wiring board. A method of manufacturing a wiring board capable of satisfactorily depositing a tin plating layer on a first connection pad when a nickel plating layer and a gold plating layer are sequentially deposited on the second connection pad by an electrolytic plating method Is to provide.

  The method for manufacturing a wiring board according to the present invention is formed on an insulating substrate having a first main surface and a second main surface, the first main surface, and the surface is covered with an electrolytic tin plating layer. A plurality of first connection pads and the second main surface are formed, are electrically connected to the first connection pads, and the surfaces are sequentially covered with an electrolytic nickel plating layer and an electrolytic gold plating layer. A method of manufacturing a wiring board comprising a plurality of second connection pads, wherein the first connection pads and the second connection are formed on the first main surface and the second main surface. The pad is formed in a state of being electrically connected to each other, and a part of the plating conduction line that electrically connects the first and second connection pads only in common to the second main surface is exposed. Forming the second connection pad and exposing the second connection pad By supplying a charge for electrolytic plating through the plating conduction line in a state where a plating mask covering the first connection pad and the plating conduction line is formed on the first and second main surfaces. A step of selectively and sequentially depositing an electrolytic nickel plating layer and an electrolytic gold plating layer on the surface of the second connection pad; exposing the first connection pad; and connecting the second connection pad and the plating conductive line An electrolytic tin plating layer is selected on the surface of the first connection pad by supplying a charge for electrolytic plating through the plating conduction line in a state where a plating mask to be coated is formed only on the second main surface. An etching mass for exposing the part of the plating conductive line and covering the first connection pad and the second connection pad The is characterized in that performing the step of etching away the portion of the plated conductive lines in the state formed in the first and second major surfaces.

  According to the method for manufacturing a wiring board of the present invention, the plating for electrically connecting the first connection pads formed on the first main surface and the second connection pads formed on the second main surface in common. The conductive line is formed only on the second main surface, and then the first connection pad is exposed and a plating mask that covers the second connection pad and the plating conductive line is formed only on the second main surface. Since an electrolytic tin plating layer is selectively deposited on the surface of the first connection pad by supplying a charge for electrolytic plating through the plating conduction line, a plating mask is formed on the second main surface. In this case, even if a component that inhibits the deposition of electrolytic tin plating is eluted from the plating mask formed on the second main surface, the eluted component is the first formed on the first main surface on the opposite side. Never reach the connection pad. Therefore, the component eluted from the plating mask does not hinder the deposition of the electrolytic tin plating layer on the first connection pad, and as a result, the tin plating layer can be satisfactorily deposited on the first connection pad. .

FIG. 1 is a schematic cross-sectional view and a top view showing an example of a wiring board manufactured by the method for manufacturing a wiring board according to the present invention. FIG. 2 is a schematic cross-sectional view for each process for explaining an embodiment of the method for manufacturing a wiring board of the present invention. FIG. 3 is a schematic cross-sectional view for each step for explaining an embodiment of the method for manufacturing a wiring board of the present invention. FIG. 4 is a bottom view for explaining an embodiment of the method for manufacturing a wiring board according to the present invention. FIG. 5 is a top view for explaining an embodiment of the method for manufacturing a wiring board according to the present invention. FIG. 6 is a bottom view for explaining an embodiment of the method for manufacturing a wiring board according to the present invention. 7A and 7B are a schematic cross-sectional view and a top view showing an example of a wiring board manufactured by a conventional wiring board manufacturing method. FIG. 8 is a schematic cross-sectional view for each process for explaining a conventional method of manufacturing a wiring board. FIG. 9 is a schematic cross-sectional view for each process for explaining a conventional method of manufacturing a wiring board. FIG. 10 is a top view for explaining a conventional method of manufacturing a wiring board. FIG. 11 is a bottom view for explaining a conventional method of manufacturing a wiring board. FIG. 12 is a top view for explaining a conventional method of manufacturing a wiring board. FIG. 13 is a bottom view for explaining a conventional method of manufacturing a wiring board. FIG. 14 is an enlarged cross-sectional view of a main part for explaining a problem in a conventional method of manufacturing a wiring board.

  Next, a method for manufacturing a wiring board according to the present invention will be described with reference to the accompanying drawings. 1A and 1B are a cross-sectional view and a top view showing a wiring board 10 manufactured by the method of manufacturing a wiring board according to the present invention, in which 1 is an insulating substrate, 3 is a wiring conductor, Is a solder resist layer, 5 is a semiconductor element connection pad, 6 is an external connection pad, 7 is an electrolytic tin plating layer, and 8 is an electrolytic nickel-gold plating layer.

  As shown in FIG. 1, a wiring board 10 according to the present invention is formed by attaching a plurality of wiring conductors 3 from the upper surface to the lower surface of an insulating substrate 1 having a large number of through-holes 2, and wiring conductors on upper and lower surfaces thereof. A solder resist layer 4 is applied so that a part of 3 is exposed. The insulating substrate 1 is formed of, for example, an electrically insulating material obtained by impregnating a glass cloth with a thermosetting resin such as an epoxy resin. The wiring conductor 3 is formed of copper such as a copper foil or a copper plating layer. Furthermore, the solder resist layer 4 is formed of an electrically insulating material in which an inorganic insulating filler such as silicon oxide is dispersed in a thermosetting resin such as an epoxy resin.

  A mounting portion for mounting the semiconductor element S is provided in the central portion of the upper surface of the wiring substrate 10, and a large number of semiconductor element connection pads 5 for connecting to the electrodes T of the semiconductor element S are provided on the mounting portion. It is formed by a part of the wiring conductor 3. Then, the semiconductor element S is mounted on the wiring substrate 10 by bringing the electrodes T of the semiconductor element S into contact with the semiconductor element connection pads 5 and connecting them via solder.

  The lower surface of the wiring board 10 is an external connection surface for connection to an external electric circuit board, and a large number of external connection pads 6 for connection to the external electric circuit board are provided on the external connection surface. It is formed by a part of the wiring conductor 3. Then, the wiring board 10 is mounted on the external electric circuit board by connecting the external connection pads 6 and the external electric circuit board via solder.

  In this wiring board 10, a tin plating layer is formed on the exposed surface of the semiconductor element connection pad 5 in order to prevent oxidation of the semiconductor element connection pad 5 and to improve the connection with the electrode T of the semiconductor element S. 7 is applied by electrolytic plating. Nickel in which a nickel plating layer and a gold plating layer are sequentially deposited on the exposed surface of the external connection pad 6 in order to prevent oxidation of the external connection pad 6 and to improve the connection with the external electric circuit board. The gold plating layer 8 is applied by electroplating.

  Here, in this wiring substrate 10, the tin plating layer 7 is deposited on the surface of the semiconductor element connection pad 5 by electrolytic plating, and the nickel-gold plating layer 8 is deposited on the surface of the external connection pad 6 by electrolytic plating. The method of making it demonstrated is demonstrated with reference to FIGS.

  First, as shown in FIG. 2A, a wiring board panel 10P is prepared in which a large number of product areas X to be the wiring board 10 are integrally formed around the product area X through a margin area Y. In each product region X, the semiconductor element connection pads 5 are formed on the upper surface, and the external connection pads 6 are formed on the lower surface. Further, each of the semiconductor element connection pads 5 and the external connection pads 6 are electrically connected to each other through the through holes 2. In FIG. 2 to FIG. 6, for the sake of simplicity, one product region X and the surrounding allowance region Y are partially shown.

  Further, as shown in FIG. 4, the wiring board panel 10 </ b> P extends from some of the wiring conductors 3 in the product region X on the lower surface of the insulating substrate 1 to the disposal margin region Y and is electrically common in the disposal margin region Y. The plating conduction line 9 made of copper connected to the is provided. The plating conductive line 9 in the discard margin region Y is completely exposed from the solder resist 4. In addition, some of the different wiring conductors 3 in the product region X are connected by the plating conductive wire 9, and a part of the plating conductive wire 9 is exposed from the opening 4 a provided in the solder resist layer 4.

  On the other hand, as shown in FIG. 5, the plating conduction line 9 is not provided on the upper surface of the insulating substrate 1. In this case, each of the semiconductor element connection pads 5 and the external connection pads 6 in the product region X are electrically connected to each other through the through holes 2, and the external connection pads 6 are connected to the lower surface side by plating. All the semiconductor element connection pads 5 and the external connection pads 6 are electrically connected in common by being electrically connected in common by the line 9.

  Next, as shown in FIG. 2B, a first plating mask M1 is formed on the upper and lower surfaces of the wiring board panel 10P. The first plating mask M1 covers the entire upper surface of the wiring board panel 10 and covers the exposed portion of the plating conductive line 9 from the solder resist layer 4 on the lower surface. As a result, only the external connection pads 6 in the product region X are selectively exposed. The first plating mask M1 is obtained by thermocompression bonding a dry film resist having photosensitivity to the upper and lower surfaces of the wiring board panel 10P using a vacuum press, and by exposing and developing using a well-known photolithography technique. It is formed.

  Next, as shown in FIG. 2 (c), a nickel plating layer and a gold plating layer are sequentially deposited on the surface of the external connection pad 6 exposed from the first plating mask M1 by an electrolytic plating method, and nickel-gold plating is performed. Layer 8 is formed. In this case, the electroplating is performed by supplying electric charges for electroplating to each external connection pad 6 through the plating conductive line 9. At this time, the nickel-gold plating layer 8 is not deposited on the semiconductor element connection pads 5 and the plating conductive lines 9 covered with the first plating mask M1.

  Next, as shown in FIG. 2D, the first plating mask M1 is removed. As a result, a wiring board panel 10P in which the nickel-gold plating layer 8 is deposited only on the external connection pads 6 is obtained. The first plating mask M1 is removed by peeling the first plating mask M1 using an alkaline stripping solution.

  Next, as shown in FIG. 2E, a second plating mask M2 is formed only on the lower surface of the wiring board panel 10P. The second plating mask M2 covers the entire lower surface of the wiring board panel 10. As a result, the external connection pads 6 and the plating conductive lines 9 are covered with the second plating mask M2, and only the semiconductor element connection pads 5 are selectively exposed. The second plating mask M2 is formed by thermocompression bonding a photosensitive dry film resist to the lower surface of the wiring board panel 10P using a vacuum press, and exposure and development using a well-known photolithography technique. Is done. At this time, even if a component that inhibits the deposition of electrolytic tin plating is eluted from the second plating mask M2 formed on the lower surface of the wiring board panel 10P, the eluted component is present on the upper surface side of the wiring board panel 10P. It does not reach the formed semiconductor element connection pad 5. Therefore, it is possible to satisfactorily deposit the electrolytic tin plating 7 on the surface of the semiconductor element connection pad 5.

  Next, as shown in FIG. 3F, a tin plating layer 7 is deposited on the surface of the semiconductor element connection pad 5 exposed from the second plating mask M2 by electrolytic plating. In this case, electrolytic plating is performed by supplying electric charges for electrolytic plating to the respective semiconductor element connection pads 5 through the plating conductive lines 9. At this time, the second plating mask M2 is formed only on the lower surface side of the wiring board panel 10, and even if a component that inhibits the deposition of electrolytic tin plating is eluted from the second plating mask M2. Since the component does not adhere to the semiconductor element connection pad 5 formed on the upper surface side of the wiring board panel 10P, the component eluted from the second plating mask M2 is electrolytic tin plating on the semiconductor element connection pad 5. It does not inhibit the deposition of the layer 7. Therefore, according to the present invention, the tin plating layer 7 can be satisfactorily applied to the semiconductor element connection pad 5. Note that the tin plating layer 7 is not deposited on the external connection pads 6 and the plating conductive lines 9 covered with the second plating mask M2.

  Next, as shown in FIG. 3G, the second plating mask M2 is removed. As a result, a wiring board panel 10P in which the nickel-gold plating layer 8 is applied to the external connection pads 6 and the tin plating layer 7 is applied to the semiconductor element connection pads 5 is obtained. At this time, neither the nickel-gold plating layer 8 nor the tin plating layer 7 is applied to the plating conductive wire 9, and the copper is exposed. The second plating mask M2 is removed by peeling the second plating mask M2 using an alkaline stripping solution.

  Next, as shown in FIG. 3H, an etching mask M3 is formed on the upper and lower surfaces of the wiring board panel 10P. The etching mask M3 covers the semiconductor element connection pads 5 and the external connection pads 6 and exposes the plating conductive lines 9 exposed from the solder resist layer 4. The etching mask M3 is formed by thermally pressing a photosensitive dry film resist onto the upper and lower surfaces of the wiring board panel 10P by vacuum press and using a well-known photolithography technique to expose and develop. .

  Next, as shown in FIG. 3I, the plating conductive line 9 exposed from the etching mask M3 is removed by etching. Thereby, as shown in FIG. 6, predetermined ones of the external connection pads 6 are electrically independent.

  Finally, as shown in FIG. 3 (j), the etching mask M3 is removed, and then the wiring board panel 10P is cut along the boundary of each product region X to thereby form the wiring board as shown in FIG. 10 is obtained. The etching mask M3 is removed by peeling the etching mask M3 using an alkaline stripping solution.

DESCRIPTION OF SYMBOLS 1 Insulation board | substrate 5 Semiconductor element connection pad (1st connection pad)
6 External connection pad (second connection pad)
7 Electrolytic Tin Plating Layer 8 Electrolytic Nickel Plating Layer and Electrolytic Gold Plating Layer 9 Plating Conduction Line M1 First Plating Mask M2 Second Plating Mask M3 Etching Mask

Claims (1)

  An insulating substrate having a first main surface and a second main surface; a plurality of first connection pads formed on the first main surface and having a surface covered with an electrolytic tin plating layer; A plurality of second connection pads formed on the second main surface, electrically connected to the first connection pads and having a surface sequentially coated with an electrolytic nickel plating layer and an electrolytic gold plating layer; A method of manufacturing a wiring board comprising: the first connection pad and the second connection pad are electrically connected to each other on the first main surface and the second main surface. Forming a plating conduction line that electrically connects the first and second connection pads only in common to the second main surface so that a part thereof is exposed; and 2 connection pads are exposed and the first connection pad and the front The second connection pad by supplying a charge for electrolytic plating through the plating conductive line in a state where a first plating mask for covering the plating conductive line is formed on the first and second main surfaces. A step of selectively depositing an electrolytic nickel plating layer and an electrolytic gold plating layer on the surface of the first and second layers, exposing the first connection pad and covering the second connection pad and the plating conductive line. An electrolytic tin plating layer is selectively formed on the surface of the first connection pad by supplying a charge for electrolytic plating through the plating conduction line in a state where a plating mask is formed only on the second main surface. And applying an etching mask that exposes the part of the plating conductive line and covers the first connection pad and the second connection pad. Method of manufacturing a wiring board of the part of the plated conductive lines in a state formed into two major surfaces and carrying out a step of etching away.