JP2016034001A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device by which variation in gate threshold is less likely to be generated by variation in depth of a recess part.SOLUTION: A semiconductor substrate comprises: a first semiconductor layer of a first conductivity type exposed to an upper surface of the semiconductor substrate; a second semiconductor layer of a second conductivity type arranged at a lower side of the first semiconductor layer; and a third semiconductor layer of the first conductivity type arranged at the lower side of the second semiconductor layer. The semiconductor device comprises: a trench that penetrates through the first semiconductor layer and the second semiconductor layer and reaches the third semiconductor layer; a gate oxide film that covers an inner surface of the trench; a gate electrode arranged in the trench; and a cap oxide film that covers an upper surface of the gate electrode. In second conductivity type impurity concentration distribution in a depth direction of the semiconductor substrate in the second semiconductor layer, a first maximum value and a second maximum value greater than the first maximum value exist. The second maximum value is formed at a lower surface side from the first maximum value.SELECTED DRAWING: Figure 5

Description

  The technology disclosed in this specification relates to a semiconductor device.

  Patent Document 1 discloses a trench gate type IGBT. When a voltage is applied between the collector and the emitter, and a potential higher than the threshold is applied to the gate, the IGBT is turned on.

International Publication No. 2013/121519

  The characteristics of a trench gate type switching semiconductor element such as the IGBT of Patent Document 1 vary greatly depending on the thickness of the gate oxide film at the depth of the peak value of the impurity concentration in the body region. The thicker the gate oxide film at this depth, the higher the gate threshold.

  When the trench gate is formed, a manufacturing error occurs at a position in the depth direction of the upper surface of the gate electrode. For this reason, a recessed recess part may be formed on a gate electrode, and a recess part may not be formed. Further, when the recessed portion is formed, the depth dimension of the recessed portion varies due to an error in the manufacturing process. Further, it is necessary to form a cap oxide film on the upper surface of the gate electrode. Since the position in the depth direction of the upper surface of the gate electrode varies, the position in the depth direction of the cap oxide film also varies. Further, when the cap oxide film is formed, the thickness of the gate oxide film in the vicinity of the cap oxide film increases. Since the position of the cap oxide film in the depth direction varies, the range in which the thickness of the gate oxide film increases also varies. When the range in which the thickness of the gate oxide film increases due to the variation overlaps with the depth of the impurity concentration peak value in the body region, the gate threshold value increases. For this reason, in the conventional semiconductor element structure, the gate threshold value may vary due to the variation in the position of the upper surface of the gate electrode in the depth direction.

  Therefore, the present specification provides a technique related to a semiconductor device in which variation in gate threshold value hardly occurs even when variation in position in the depth direction of the upper surface of the gate electrode occurs.

  The semiconductor device disclosed in this specification includes a semiconductor substrate. The semiconductor substrate is disposed on a lower side of the first semiconductor layer, and is exposed to the first semiconductor layer, and is in contact with the first semiconductor layer. A second semiconductor layer of a type, a first semiconductor layer disposed below the second semiconductor layer, in contact with the second semiconductor layer, and separated from the first semiconductor layer by the second semiconductor layer A conductive third semiconductor layer is provided. The semiconductor device is formed on the upper surface of the semiconductor substrate, has a trench reaching the third semiconductor layer through the first semiconductor layer and the second semiconductor layer, and a gate oxidation covering the inner surface of the trench A gate electrode disposed within the trench and insulated from the semiconductor substrate by the gate oxide film; and a cap oxide film covering an upper surface of the gate electrode. In the second conductivity type impurity concentration distribution in the depth direction of the semiconductor substrate in the second semiconductor layer, there are a first maximum value and a second maximum value larger than the first maximum value. The second maximum value is formed on the lower surface side than the first maximum value.

  In the present specification, “depth” means a position in the thickness direction of the semiconductor substrate.

  The semiconductor device described above will be described using the semiconductor device illustrated in FIG. 1 as an example. In FIG. 1, the first conductivity type is shown as n-type and the second conductivity type is shown as p-type, but the opposite may be possible. The semiconductor device of FIG. 1 includes a first semiconductor layer 220, a second semiconductor layer 222, a third semiconductor layer 224, a gate oxide film 242, a gate electrode 244, and a cap oxide film 246. Since the side surface of the trench near the upper surface of the gate electrode 244 is additionally oxidized when the cap oxide film 246 is formed, the thickness of the gate oxide film 242 is thick in the vicinity of the cap oxide film 246 and thin in the lower side. The depth 250 in FIG. 1 is the depth of the first maximum value, and the depth 252 is the depth of the second maximum value. Since the second maximum value is larger than the first maximum value, the gate threshold value of this semiconductor device is greatly influenced by the thickness of the gate oxide film 242 at the depth 252 of the second maximum value. The position in the depth direction of the upper surface of the gate electrode 244 is likely to vary due to manufacturing errors. In this semiconductor device, since the second maximum value is formed at the depth 252 located on the lower surface side of the first maximum value depth 250, the gate oxide film 242 is unlikely to be thick at the depth 252. For this reason, in this semiconductor device, even if the position in the depth direction of the upper surface of the gate electrode 244 varies, the gate threshold value hardly varies.

  According to the structure of the semiconductor device described above, even if the position of the upper surface of the gate electrode varies during mass production of the semiconductor device, it is possible to suppress the variation in the gate threshold value of each semiconductor device.

FIG. 14 is a cross-sectional view illustrating an example of a semiconductor device disclosed in this specification. The top view of IGBT10 which concerns on embodiment. Sectional drawing of IGBT10 in the III-III line of FIG. Sectional drawing of IGBT10 in the IV-IV line | wire of FIG. The enlarged view of the recess part 48 vicinity of IGBT10. The enlarged view of the recess part 48 vicinity of IGBT10 (when the recess part 48 is deeper than FIG. 5). The graph which shows the impurity concentration distribution in the position of the XX line of FIG. Explanatory drawing of the manufacturing method of IGBT10. Explanatory drawing of the manufacturing method of IGBT10. Explanatory drawing of the manufacturing method of IGBT10. Explanatory drawing of the manufacturing method of IGBT10. FIG. 12 is an enlarged view of the vicinity of the recess portion 48 in FIG. 11. Explanatory drawing of the manufacturing method of IGBT10. Explanatory drawing of the manufacturing method of IGBT10. Sectional drawing of IGBT of a modification. Sectional drawing of IGBT10 when the recessed part 48 is not formed.

  The IGBT 10 according to the embodiment shown in FIGS. 2 to 4 includes a semiconductor substrate 12 and electrodes, insulators, and the like formed on the upper and lower surfaces of the semiconductor substrate 12.

  A plurality of trenches 40 are formed in a concave shape on the upper surface of the semiconductor substrate 12. As shown in FIG. 2, the trenches 40 extend in parallel with each other. The inner surface of each trench 40 is covered with a gate oxide film 42. A gate electrode 44 is disposed inside each trench 40. The gate electrode 44 is insulated from the semiconductor substrate 12 by the gate oxide film 42. The upper surface of the gate electrode 44 is covered with a cap oxide film 46. An interlayer insulating film 47 is formed on the cap oxide film 46. The gate electrode 44 can be connected to the outside at a position not shown.

  An emitter electrode 60 is formed on the upper surface of the semiconductor substrate 12. The emitter electrode 60 is insulated from the gate electrode 44 by the cap oxide film 46 and the interlayer insulating film 47. A collector electrode 62 is formed on the lower surface of the semiconductor substrate 12.

  Inside the semiconductor substrate 12, an emitter region 20, a body contact region 21, a first body region 22, a carrier storage region 24, a second body region 26, a drift region 28, a buffer region 30 and a collector region 32 are formed. .

  The emitter region 20 shown in FIG. 3 is an n-type region and is formed in a range exposed on the upper surface of the semiconductor substrate 12. The emitter region 20 is connected to the emitter electrode 60. As shown in FIG. 2, the emitter region 20 extends long in a direction perpendicular to the gate electrode 44. The emitter region 20 is in contact with the gate oxide film 42.

  The body contact region 21 shown in FIG. 4 is a p-type region containing a high concentration of p-type impurities. The body contact region 21 is formed in a range exposed on the upper surface of the semiconductor substrate 12. As shown in FIG. 2, the body contact region 21 extends long in the direction orthogonal to the gate electrode 44. The body contact region 21 is adjacent to the emitter region 20. The body contact region 21 is connected to the emitter electrode 60.

  The first body region 22 is a p-type region having a p-type impurity concentration lower than that of the body contact region 21. As shown in FIGS. 3 and 4, the first body region 22 is formed below the emitter region 20 and the body contact region 21. The first body region 22 is in contact with the gate oxide film 42 below the emitter region 20. FIG. 7 shows the impurity concentration distribution at the position of the X-ray in FIG. That is, FIG. 7 shows the distribution of the impurity concentration in the first body region 22, the carrier accumulation region 24 and the second body region 26 along the depth direction (thickness direction of the semiconductor substrate 12). The solid line graph in FIG. 7 shows the p-type impurity concentration distribution, and the broken line graph shows the n-type impurity concentration distribution. A p-type impurity concentration distribution in the depth direction similar to that in FIG. 7 is observed at any position on the semiconductor substrate 12. As shown in FIG. 7, a maximum value PH1, a minimum value PL, and a maximum value PH2 of the p-type impurity concentration are formed in the first body region 22. The maximum value PH2 is the maximum value of the p-type impurity concentration in the graph of FIG. The maximum value PH1 is smaller than the maximum value PH2. The minimum value PL is smaller than any of the maximum values PH1 and PH2. The maximum value PH1 is formed at a depth 101. The minimum value PL is formed at a depth 103 located below the maximum value PH1. The maximum value PH <b> 2 is formed at a depth 102 located below the depth 103. Hereinafter, the first body region 22 above the depth 103 having the minimum value PL is referred to as an upper layer 22a, and the first body region 22 below the depth 103 is referred to as a lower layer 22b. The upper layer 22a is a layer having a maximum value PH1, and is widely distributed in layers along the upper surface of the semiconductor substrate 12. The lower layer 22b is a layer having a maximum value PH2, and is widely distributed in layers along the upper surface of the semiconductor substrate 12.

  The carrier accumulation region 24 is an n-type region and is formed below the first body region 22. The carrier accumulation region 24 is separated from the emitter region 20 by the first body region 22. The carrier accumulation region 24 is separated from the drift region 28 by the second body region 26. The carrier accumulation region 24 is in contact with the gate oxide film 42 below the first body region 22. The carrier accumulation region 24 is an intermediate region that separates the first body region 22 and the second body region 26.

  The second body region 26 is a p-type region and is formed below the carrier accumulation region 24. As shown in FIG. 7, the p-type impurity concentration of the second body region 26 is lower than the p-type impurity concentration of the first body region 22. The second body region 26 is separated from the first body region 22 by the carrier accumulation region 24. Second body region 26 is in contact with gate oxide film 42 below carrier accumulation region 24.

  The drift region 28 is an n-type region containing a low concentration n-type impurity. The drift region 28 is formed below the second body region 26. The drift region 28 is separated from the carrier accumulation region 24 by the second body region 26. Drift region 28 is in contact with gate oxide film 42 located at the lower end of trench 40.

  The buffer region 30 is an n-type region containing a high concentration of n-type impurities. The buffer region 30 is formed below the drift region 28.

  The collector region 32 is a p-type region containing a high concentration of p-type impurities. The collector region 32 is formed below the buffer region 30. The collector region 32 is formed on the entire surface facing the lower surface of the semiconductor substrate 12. The collector region 32 is connected to the collector electrode 62.

  5 and 6 are enlarged sectional views in the vicinity of the gate electrode 44. FIG. In FIGS. 5 and 6, the interlayer insulating film 47 is not hatched for easy viewing. As shown in FIG. 5, the upper surface of the gate electrode 44 is located below the upper surface of the semiconductor substrate 12. Therefore, the upper surface of the cap oxide film 46 is also located below the upper surface of the semiconductor substrate 12. Therefore, a recess 48 that is recessed with respect to the upper surface of the semiconductor substrate 12 is formed on the gate electrode 44. The gate oxide film 42 formed on the side surface of the recess 48 has a thickness lower than that of the cap oxide film 46 (that is, the gate oxide film 42 on the side of the gate electrode 44). Thicker than the thickness. Hereinafter, the thick gate oxide film 42 formed on the side surface of the recess portion 48 is referred to as a thick film portion 42a. In addition, the gate oxide film 42 in the vicinity of the upper end of the gate electrode 44 (that is, in the vicinity of the cap oxide film 46) among the gate oxide films 42 on the side of the gate electrode 44 is continuous from the upper end toward the lower side. It is the decreasing part 42b where thickness decreases. A side surface of the reduced portion 42b on the gate electrode 44 side is inclined toward the gate electrode 44 side. On the other hand, the side surface of the reduced portion 42 b on the semiconductor layer side is substantially parallel to the thickness direction of the semiconductor substrate 12. For this reason, the thickness of the reduced portion 42b is thinner toward the lower side. The thickness of the upper end portion (thickest portion) of the reduced portion 42b is smaller than the thickness of the thick film portion 42a. The upper end of the reduced portion 42 b is connected to the cap oxide film 46. Hereinafter, the gate oxide film 42 below the reduced portion 42b is referred to as a thin film portion 42c. The thin film portion 42c has a substantially constant thickness. The thickness of the thin film portion 42c is thinner than the thickness of the reduced portion 42b. As will be described in detail later, the reason why the gate oxide films 42 having different thicknesses such as the thick film portion 42a, the reduced portion 42b, and the thin film portion 42c are formed is that the gate oxide film 42 is partially formed when the cap oxide film 46 is formed. It is for growing up.

  In FIG. 5, the entire thick film portion 42 a and the reduced portion 42 b exist within the depth range of the emitter region 20. The first body region 22 is in contact only with the thin film portion 42c. However, a manufacturing error occurs in the dimension D1 in the depth direction of the recess 48 shown in FIG. 5 (that is, the distance in the thickness direction between the upper surface of the semiconductor substrate 12 and the cap oxide film 46). When the dimension D1 increases due to a manufacturing error, the thick film portion 42a may be in contact with the first body region 22 as shown in FIG. In the example of FIG. 6, the thick film portion 42a is formed at the depth 101 having the maximum value PH1. A thin film portion 42c is formed at a depth 102 having a maximum value PH2. The reduced portion 42 b is disposed between the depth 101 and the depth 102. In the IGBT 10 of the present embodiment, even when the dimension D1 of the recess 48 is the largest within the range of manufacturing error, the reduced portion 42b is positioned above the depth 102. In other words, the thin film portion 42 c is formed at the depth 102 regardless of the depth D 1 of the recess portion 48.

  Next, the operation of the IGBT 10 will be described. During the IGBT operation, a voltage that makes the collector electrode 62 positive is applied between the emitter electrode 60 and the collector electrode 62. In this state, when a voltage equal to or higher than the gate threshold (minimum gate voltage necessary for turning on the IGBT 10) is applied to the gate electrode 44, the IGBT 10 is turned on. That is, when a voltage is applied to the gate electrode 44, a channel is formed in a range in contact with the gate oxide film 42 in the first body region 22, and a channel is formed in a range in contact with the gate oxide film 42 in the second body region 26. . As a result, electrons flow from the emitter region 20 to the collector region 32 through the channel of the first body region 22, the carrier accumulation region 24, the channel of the second body region 26, the drift region 28, and the buffer region 30. Further, holes flow from the collector region 32 to the body contact region 21 through the buffer region 30, the drift region 28, the second body region 26, the carrier accumulation region 24, and the first body region 22. As a result, a current flows through the IGBT 10.

  Here, the gate threshold value of the IGBT 10 greatly varies depending on the p-type impurity concentration in the region where the channel is formed and the thickness of the gate oxide film 42 in contact with the region where the channel is formed. If the p-type impurity concentration of the region where the channel is formed is high, it is difficult to invert the region to n-type, so that it is difficult to form the channel. In the IGBT 10, the p-type impurity concentration is highest at the depth 102 having the maximum value PH2 in the first body region 22 and the second body region 26 where the channel is formed. Therefore, the channel is hardly formed at the depth 102. Further, when the gate insulating film 42 is thick, an electric field is hardly applied from the gate electrode 44 to a region where a channel is formed, and thus a channel is hardly formed. In the IGBT 10, the thickness of the gate oxide film 42 at a depth 102 at which a channel is difficult to be formed greatly affects the gate threshold.

  Here, in the IGBT 10, two maximum values PH <b> 1 and PH <b> 2 are formed in the first body region 22. The depth 102 of the maximum value PH2 is located below the depth 101 of the maximum value PH1. Therefore, even when the recess portion 48 becomes deep as shown in FIG. 6 due to manufacturing errors, the thick film portion 42a and the reduced portion 42b hardly reach the depth 102. That is, the thin film portion 42 c is reliably formed at the depth 102. For this reason, in the IGBT 10, variations in the thickness of the gate oxide film 42 at the depth 102 hardly occur regardless of variations in the dimension D 1 of the recess 48. Therefore, the IGBT 10 having this structure is unlikely to vary in the gate threshold during mass production. Note that even if the thick film portion 42a is formed at the depth 101 of the maximum value PH1, as shown in FIG. 6, the gate threshold value is hardly affected. This is because the maximum value PH1 is smaller than the maximum value PH2.

  The first body region 22 of the IGBT 10 has a maximum value PH1 in addition to the maximum value PH2. For this reason, the value obtained by integrating the p-type impurity concentration in the first body region 22 in the depth direction (that is, the integrated value in the first body region 22 in the graph of FIG. 7) is high. When this integral value is high, it is possible to prevent the depletion layer extending from the boundary between the first body region 22 and the carrier accumulation region 24 from reaching the first body region 22 to reach the emitter region 20 when the IGBT 10 is turned off. it can. Therefore, this IGBT 10 has high withstand voltage characteristics. Further, by providing the two maximum values PH1 and PH2 in this way, the integrated value can be increased without increasing the value of the maximum value PH2. In this way, it is realized that the gate threshold value is further reduced by making the value of the maximum value PH2 relatively low.

(Manufacturing process)
Next, the manufacturing method of IGBT is demonstrated. The IGBT 10 is manufactured from an n-type semiconductor substrate (silicon substrate) having substantially the same n-type impurity concentration as the drift region 28. First, the trench 40 is formed on the upper surface of the semiconductor substrate by etching. Next, a gate oxide film 42 is formed on the inner surface of the trench 40 by oxidation or CVD, as shown in FIG. The gate oxide film 42 is also formed on the upper surface of the semiconductor substrate. Next, as shown in FIG. 9, an electrode layer 52 made of polysilicon is formed on the upper surface of the semiconductor substrate and inside the trench 40 by oxidation or CVD. Next, the upper surface of the electrode layer 52 is planarized by grinding, polishing, etching, CMP, or the like.

  Next, the unnecessary electrode layer 52 is etched. At this time, the electrode layer 52 is left in the trench 40 as shown in FIG. The electrode layer 52 remaining in the trench 40 becomes the gate electrode 44. The etching is performed so that the electrode layer 52 in the trench 40 is partially etched. Therefore, a recess 48 is formed on the gate electrode 44. Since the etching amount varies, the dimension of the recess 48 in the depth direction varies.

  Next, the upper surface of the gate electrode 44 is oxidized by heat-treating the semiconductor substrate 12 in an oxidizing atmosphere. As a result, a cap oxide film 46 is formed as shown in FIG.

  When the cap oxide film 46 is formed, the oxidizing gas passes through the gate oxide film 42 on the side surface of the recess 48 and reaches the semiconductor layer. As a result, the semiconductor layer on this side surface is oxidized, and the thickness of the gate oxide film 42 covering the side surface of the recess 48 increases. For this reason, as shown in FIG. 12, the thick film part 42a is formed.

  Further, when the cap oxide film 46 is formed, the oxidizing gas reaches the side surface of the gate electrode 44 near the upper end of the gate electrode 44. As a result, the side surface is oxidized, and the thickness of the gate oxide film 42 near the upper end of the gate electrode 44 increases. The position closer to the upper end of the gate electrode 44 is more likely to be oxidized. Therefore, in the vicinity of the upper end of the gate electrode 44, the thickness of the gate oxide film 42 increases as the position is closer to the upper end. As a result, a reduced portion 42b whose thickness decreases from the upper end of the gate electrode 44 toward the lower side is formed. Further, since the gate oxide film 42 below the reduced portion 42b is not oxidized, the original thickness is maintained. For this reason, the gate oxide film 42 below the reduced portion 42b becomes a thin film portion 42c.

  Next, impurity ions are implanted into the semiconductor substrate from the upper surface side of the semiconductor substrate. Here, n-type impurity implantation into the emitter region 20, p-type impurity implantation into the body contact region 21, p-type impurity implantation into the first body region 22, n-type impurity implantation into the carrier storage region 24, and The p-type impurity is implanted into the two body regions 26, respectively.

  Reference numbers 20a, 22a1, 22a2, 24a, and 26a in FIG. 13 indicate positions where impurities are implanted. Reference number 20a indicates a position where n-type impurities are implanted by ion implantation into the emitter region 20, and reference numbers 22a1 and 22a2 indicate positions where p-type impurities are implanted by ion implantation into the first body region 22. The reference number 24a indicates the position where n-type impurities are implanted by ion implantation into the carrier accumulation region 24, and the reference number 26a indicates that p-type impurities are implanted by ion implantation into the second body region 26. The position is shown. Although not shown, p-type impurity implantation into the body contact region 21 is also performed. Here, at least two ion implantations of the ion implantation for the position 22a1 and the ion implantation for the position 22a2 are performed on the first body region 22. The position 22a2 is located below the position 22a1. For the position 22a2, the p-type impurity is implanted at a higher concentration than the position 22a1. Thereafter, by heat-treating the semiconductor substrate, an emitter region 20, a body contact region 21, a first body region 22, a carrier accumulation region 24, and a second body region 26 are formed as shown in FIG. Since the first body region 22 is ion-implanted twice, two maximum values PH1 and PH2 are formed in the first body region 22 at different depths. Further, since the p-type impurity concentration is implanted at a deeper position 22a2, the maximum value PH2 is formed on the lower surface side than the depth 101 of the maximum value PH1, as described with reference to FIG.

  As described above, the variation in the dimension of the recess 48 in the depth direction is large. However, in this manufacturing method, since the depth 102 of the maximum value (that is, the maximum value PH2) of the p-type impurity concentration in the first body region 22 is located closer to the lower surface, the thick film portion 42a is formed at the depth 102. In addition, the reduced portion 42b can be prevented from being formed. For this reason, variations in the thickness of the gate oxide film 42 at the depth 102 hardly occur. Therefore, according to this manufacturing method, the gate threshold value of the IGBT to be manufactured is less likely to vary.

  Thereafter, other necessary regions are formed in the semiconductor substrate, and necessary electrodes, insulating films and the like are formed on the surface of the semiconductor substrate, whereby the IGBT 10 is formed.

  As described above, by adopting the structure and manufacturing method of the IGBT 10 according to the present embodiment, even when there is a variation in the dimension of the recess 48 in the depth direction, the variation in the threshold voltage of the IGBT is suppressed. It is possible.

  In addition, each component of IGBT10 of said embodiment has the following relationship with respect to each component of a claim. The emitter region 20 of the embodiment is an example of a first semiconductor layer in the claims. The first body region 22 of the embodiment is an example of a second semiconductor layer in the claims. The carrier accumulation region 24 of the embodiment is an example of a third semiconductor layer in the claims. The second body region 26 of the embodiment is an example of a fifth semiconductor layer in the claims. The drift region 28 and the buffer region 30 in the embodiment are an example of a sixth semiconductor layer in the claims. The collector region 32 of the embodiment is an example of a fourth semiconductor layer in the claims.

  In the above embodiment, the IGBT having the carrier accumulation region 24 has been described. However, the technique of the above embodiment may be applied to an IGBT that does not have the carrier accumulation region 24. For example, as shown in FIG. 15, an IGBT having only one body region 22 without the carrier accumulation region 24 may be used. In the IGBT of FIG. 15, a maximum value PH1 is formed at the depth 101 in the body region 22, and a maximum value PH2 is formed at the depth 102 below the depth 101. The maximum value PH2 is larger than the maximum value PH1. Even in the structure of FIG. 15, variations in the gate threshold can be suppressed.

  Moreover, although said embodiment demonstrated the case where it had the recess part 48, the recess part 48 does not necessarily need to be formed. For example, when the etching amount is small in the step of etching the electrode layer 52 described above, or when the electrode layer 52 is planarized by CMP or the like, the upper surface of the cap insulating film 46 and the semiconductor substrate 12 are formed as shown in FIG. In some cases, the upper surfaces of the two surfaces are coplanar. That is, in this case, the recess 48 is not formed.

  In the IGBT of FIG. 15, the emitter region 20 is an example of the first semiconductor layer of the claims, the body region 22 is an example of the second semiconductor layer of the claims, and the drift region 28 and the buffer region 30 are claimed. It is an example of the 3rd semiconductor layer of a term. Further, the collector region 32 of FIG. 15 is an example of a fourth semiconductor layer in the claims.

  The semiconductor device shown in FIGS. 2 and 15 may be a MOSFET in which the collector region 32 is omitted and the bottom electrode 62 is connected to the n-type region 30.

  The semiconductor device of the above-described embodiment can be expressed as follows. The semiconductor substrate may further include a fourth semiconductor layer of the second conductivity type separated from the second semiconductor layer by the third semiconductor layer. Note that the fourth semiconductor layer may be in contact with the third semiconductor layer, or another layer may be interposed between the fourth semiconductor layer and the third semiconductor layer.

  A semiconductor substrate disposed below the third semiconductor layer, in contact with the third semiconductor layer, and separated from the second semiconductor layer by the third semiconductor layer; The semiconductor device further includes a sixth semiconductor layer of a first conductivity type disposed below the fifth semiconductor layer, in contact with the fifth semiconductor layer, and separated from the third semiconductor layer by the fifth semiconductor layer. It may be. The trench may penetrate the third semiconductor layer and the fifth semiconductor layer and reach the sixth semiconductor layer.

  As described above, even when the fifth semiconductor layer and the sixth semiconductor layer are present below the third semiconductor layer, it is possible to suppress variations in threshold voltage due to variations in the position of the upper surface of the gate electrode.

  The gate oxide film may have a reduced portion whose thickness decreases as it goes downward from the depth of the cap oxide film, and a lower portion positioned below the reduced portion. The second maximum value may be located at the depth of the lower portion.

  By adopting such a configuration, it is possible to suppress variations in threshold voltage even if the position and range of the reduced portion vary due to changes in the conditions for forming the cap oxide film.

  A method for manufacturing a semiconductor device includes a first step of implanting a second conductivity type impurity in a depth range of a second semiconductor layer, and a depth lower than an implantation depth of a first step in the depth range of the second semiconductor layer. You may have the 2nd process of inject | pouring more 2nd conductivity type impurities into the depth of the side than a 1st process.

  By adopting such a manufacturing method, it is possible to suppress variations in threshold voltage of the semiconductor device.

The embodiments have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings achieves a plurality of objects at the same time, and has technical usefulness by achieving one of them.

10: IGBT
12: Semiconductor substrate 20: Emitter region 21: Body contact region 22: First body region 22a: Upper layer 22b: Lower layer 24: Carrier accumulation region 26: Second body region 28: Drift region 30: Buffer region 32: Collector region 40: Trench 42: Gate oxide film 42a: Thick film portion 42b: Decreasing portion 42c: Thin film portion 44: Gate electrode 46: Cap oxide film 47: Interlayer insulating film 48: Recessed portion 60: Emitter electrode 62: Collector electrode

Claims (5)

A semiconductor device having a semiconductor substrate,
The semiconductor substrate is
A first semiconductor layer of a first conductivity type exposed on an upper surface of the semiconductor substrate;
A second semiconductor layer of a second conductivity type disposed below the first semiconductor layer and in contact with the first semiconductor layer;
A third semiconductor layer of a first conductivity type, disposed below the second semiconductor layer, in contact with the second semiconductor layer and separated from the first semiconductor layer by the second semiconductor layer;
With
The semiconductor device is
A trench formed on the upper surface of the semiconductor substrate, penetrating the first semiconductor layer and the second semiconductor layer and reaching the third semiconductor layer;
A gate oxide film covering the inner surface of the trench;
A gate electrode disposed inside the trench and insulated from the semiconductor substrate by the gate oxide film;
A cap oxide film covering the upper surface of the gate electrode;
With
In the second conductivity type impurity concentration distribution in the depth direction of the semiconductor substrate in the second semiconductor layer, a first maximum value and a second maximum value larger than the first maximum value exist,
The second maximum value is formed on the lower surface side than the first maximum value.
A semiconductor device.   2. The semiconductor device according to claim 1, wherein the semiconductor substrate further includes a fourth semiconductor layer of a second conductivity type separated from the second semiconductor layer by the third semiconductor layer. The semiconductor substrate is
A fifth semiconductor layer of a second conductivity type disposed below the third semiconductor layer, in contact with the third semiconductor layer, and separated from the second semiconductor layer by the third semiconductor layer; ,
A sixth semiconductor layer of a first conductivity type, disposed below the fifth semiconductor layer, in contact with the fifth semiconductor layer and separated from the third semiconductor layer by the fifth semiconductor layer;
In addition,
The trench penetrates the third semiconductor layer and the fifth semiconductor layer to reach the sixth semiconductor layer;
The semiconductor device according to claim 1, wherein: The gate oxide film has a reduced portion whose thickness decreases as it goes downward from the depth of the cap oxide film, and a lower portion located below the reduced portion;
The second maximum is located at a depth of the lower portion;
The semiconductor device according to claim 1, wherein: A method for manufacturing a semiconductor device according to any one of claims 1 to 4,
A first step of implanting a second conductivity type impurity within a depth range of the second semiconductor layer;
A second step of implanting more second conductivity type impurities than the first step to a depth below the implantation depth of the first step within the depth range of the second semiconductor layer;
A manufacturing method comprising:

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