JP2016009825A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To proximally position a transistor and a protection diode of the transistor while inhibiting leakage current from the transistor to the protection diode.SOLUTION: A semiconductor device manufacturing method comprises the steps of: forming an element isolation insulation film 2 on a silicon substrate 1 to partition the silicon substrate 1 into a plurality of element formation regions 3 and forming a transistor T1 and a protection diode 20; and forming a gate insulation film 14 in the region 12 where the protection diode 20 is to be formed on the transistor T1 side beyond the protection diode 20 side and forming a protection electrode 16 on the gate insulation film 14. A width of each of the gate insulation film 14 and the protection electrode 16 is made larger than a gate length. The protection electrode 16 is connected to potential where a channel of a gate electrode 15 is turned off, or the same potential with the gate electrode 15.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  Some semiconductor devices include, for example, a MOS (metal-oxide-semiconductor) transistor on a silicon substrate and a multilayer wiring electrically connected to the MOS transistor formed thereon. Here, in the semiconductor device, a protection diode that protects the MOS transistor is formed in order to prevent charges caused by static electricity from damaging the gate insulating film of the MOS transistor through the wiring. The protection diode is formed in the same well as the transistor to be protected. For example, in the case of an N-type MOS transistor formed in a P-type well, a protective diode that protects the N-type MOS transistor is also formed in the same P-type well. In this case, in order to reduce a leakage current from the N-type MOS transistor to the protection diode, an element isolation insulating film is formed between the N-type MOS transistor and the protection diode. Further, when forming the source / drain regions by implanting ions on both sides of the gate electrode in the formation process of the N-type MOS transistor, ions are implanted into the formation region of the protection diode under the same conditions to form the protection diode. . The gate electrode of the N-type MOS transistor thus formed and the protection diode are electrically connected via a wiring formed in the upper layer.

JP-A-10-242401 Special Table 2001-526003

  Here, when a transistor is formed on a P-type substrate without using a P-type well, a leak current along the element isolation insulating film is easily generated between the N-type transistor and the protection diode. Therefore, in order to reduce the leakage current, the protection diode is formed after the well is formed by ion implantation in advance in the formation region of the protection diode. On the other hand, no well is formed in the transistor formation region. Thereby, the leakage current of the N-type transistor can be reduced.

However, when ions are implanted into the protective diode formation region, the ions in the ion implantation layer diffuse into the P-type substrate due to the heat treatment during the manufacturing process, and the ion concentration in the N-type transistor formation region changes. It is conceivable that the threshold voltage varies. For this reason, in the conventional semiconductor device, the transistor and the protection diode, which are protected elements, are arranged at a distance that is not affected by ion diffusion. However, when the arrangement interval between the transistor and the protection diode is increased, it is difficult to increase the degree of integration of the semiconductor device.
The present invention has been made in view of such circumstances, and an object of the present invention is to allow a transistor and its protection diode to be arranged close to each other while suppressing leakage current from the transistor to the protection diode.

  According to one aspect of the embodiment, the transistor disposed in the first element formation region on the silicon substrate and the second element formation region on the silicon substrate are electrically connected to the gate electrode of the transistor. A protection diode connected thereto, an element isolation insulating film disposed between the first element formation region and the second element formation region, and the second element formation between the protection diode and the transistor A semiconductor device comprising: a protective insulating film disposed in a region; and a protective electrode disposed on the protective insulating film and connected to a potential at which a channel of the gate electrode is turned off or the same potential as the gate electrode Is provided.

  According to another aspect of the embodiment, an element isolation insulating film is formed on a silicon substrate to define a first element formation region and a second element formation region. In the first element formation region, After forming a transistor, forming a protection diode in the second element formation region, forming a protection insulating film in a region closer to the transistor than the protection diode in the second element formation region, and then on the protection insulating film Forming a protective electrode, electrically connecting the protective diode and the gate electrode of the transistor, and connecting the protective electrode to a potential at which the channel of the gate electrode is turned off, or to the same potential as the gate electrode. A method for manufacturing a semiconductor device is provided.

  The leakage current from the transistor to the protection diode can be suppressed, and the semiconductor circuit can be highly integrated.

FIG. 1A is a cross-sectional view (part 1) illustrating an example of the manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 1B is a cross-sectional view (part 2) illustrating the example of the manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 1C is a sectional view (part 3) showing an example of the manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 1D is a cross-sectional view (No. 4) showing an example of the manufacturing process of the semiconductor device according to the first embodiment of the invention. FIG. 1E is a sectional view (No. 5) showing an example of the manufacturing process of the semiconductor device according to the first embodiment of the invention. FIG. 1F is a cross-sectional view (No. 6) showing an example of the manufacturing process of the semiconductor device according to the first embodiment of the invention. FIG. 1G is a sectional view (No. 7) showing an example of the manufacturing process of the semiconductor device according to the first embodiment of the invention. FIG. 2 is a plan view schematically showing an example of the layout of the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a plan view schematically showing an example of the layout of the semiconductor device according to the modification of the first embodiment of the present invention. FIG. 4 is a cross-sectional view schematically showing an example of the layout of the semiconductor device according to the modification of the first embodiment of the present invention. FIG. 5 is a plan view schematically showing an example of the layout of the semiconductor device according to another modification of the first embodiment of the present invention. FIG. 6 is a cross-sectional view schematically showing an example of a layout of a semiconductor device according to another modification of the first embodiment of the present invention. FIG. 7A is a sectional view (No. 1) showing an example of a manufacturing process of a semiconductor device according to the second embodiment of the present invention. FIG. 7B is a sectional view (No. 2) showing an example of the manufacturing process of the semiconductor device according to the second embodiment of the present invention. FIG. 7C is a sectional view (part 3) showing an example of the manufacturing process of the semiconductor device according to the second embodiment of the present invention. FIG. 8 is a cross-sectional view schematically showing an example of the layout of the semiconductor device according to the modification of the second embodiment of the present invention.

The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
The foregoing general description and the following detailed description are exemplary and explanatory only and are not intended to limit the invention.

First, steps required until a sectional structure shown in FIG. 1A is obtained will be described.
As shown in FIG. 1A, a plurality of element isolation insulating films 2 are formed on a P-type silicon substrate 1. For the element isolation insulating film 2, for example, shallow trench isolation (STI) is used. The STI is formed by forming a trench in the element isolation region of the silicon substrate 1 and embedding an insulating film such as silicon oxide therein. Thereby, a plurality of element formation regions 3 partitioned by the element isolation insulating film 2 are formed on the surface of the silicon substrate 1.

Next, impurities are ion-implanted into a part of the surface of the silicon substrate 1 to form the well 10. For example, when an n-type impurity such as phosphorus is implanted as a dopant impurity in the element formation region, an N well is formed. Further, when a p-type impurity such as boron is implanted as a dopant impurity in the element formation region, a P well is formed. The well 10 is implanted so that the impurity has a concentration of, for example, 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ .

Next, steps required until a sectional structure shown in FIG. 1B is obtained will be described.
First, a region which is one of the element formation regions 3 on the silicon substrate 1 and in which the well 10 is not formed is defined as a transistor formation region 11 (first element formation region). Further, a region where the well 10 is not formed and adjacent to the transistor formation region 11 is defined as a protection diode formation region 12 (second element formation region). These element formation regions 11 and 12 have the same impurity concentration and are equal to the impurity concentration of the silicon substrate 1.

  First, a gate insulating film 13 is formed in the transistor formation region 11. As a method for forming the gate insulating film 13, for example, there is a method in which the surface of the transistor formation region or a part of the protection diode formation region is thermally oxidized. Here, the gate insulating film 13 is a silicon oxide film formed by thermal oxidation, and the thickness thereof is, for example, 1 nm to 10 nm. Note that the gate insulating film 13 may be formed of a material having a high dielectric constant by a CVD method or the like. At the same time, a gate insulating film 14 as a protective insulating film is formed in the transistor formation region 11. The thickness of the gate complete film 14 is the same as that of the gate insulating film 13 in the adjacent transistor formation region 11.

  Thereafter, an amorphous or polycrystalline silicon film is formed on the entire surface of the silicon substrate 1. The film thickness of the silicon film is about 50 nm, for example. By patterning the silicon film, the gate electrode 15 is formed in the transistor formation region 11. The gate electrode 15 is also formed in another transistor formation region 11 (not shown). At the same time, the protective electrode 16 is formed in the protective diode formation region 12. The protective electrode 16 is formed so as to cover a part of the element isolation insulating film 2 that partitions the protective diode formation region 12 and also to cover a part of the exposed silicon substrate 1 between the element isolation insulating films 2. As one example, the protective electrode 16 has an opening that exposes the silicon substrate 1 in a square shape, and is formed in a ring shape that extends on the element isolation insulating film 2. Here, the gate electrode 15 and the protective electrode 16 may be formed of a metal material.

Next, steps required until a sectional structure shown in FIG. FIG. 1C is a diagram illustrating a manufacturing process in a cross section taken along line AA in FIG. 1B.
Impurity source / drain regions 17 are formed by implanting impurities into regions on both sides of the gate electrode 15 by ion implantation using the gate electrode 15 as a mask. Impurities are implanted into the extension source / drain region 17 so as to have a concentration of 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ , for example.

  Thereafter, an insulating film is formed on the entire upper surface of the silicon substrate 1 including the gate electrode 15. As the insulating film, for example, a silicon oxide film formed by a CVD method is used. Then, the insulating film is etched back to leave only the both side portions of the gate electrode 15 to form the insulating sidewalls 18.

Here, impurities are ion-implanted again on both sides of the gate electrode 15 using the insulating sidewalls 18 and the gate electrode 15 as a mask, and the extension source / drain region 17 is deep in the silicon substrate 1 on the side of each gate electrode 15. A source / drain diffusion layer constituting the region is formed. As a result, source / drain regions 19 are formed in the silicon substrate 1 so as to sandwich the gate electrode 15 therebetween. Impurities are implanted into the source / drain region 19 so as to have a concentration of, for example, 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ .

At this time, as shown in FIG. 1D, the protection diode 20 is formed by ion implantation. Further, impurities are implanted into the protective diode 20 so as to have a concentration of, for example, 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ . After the impurity implantation, heat treatment is performed. By this heat treatment, each source / drain region 19 and the protection diode 20 are activated to reduce the resistance.

  Further, a mask (not shown) is formed on the entire upper surface of the silicon substrate 1 including the gate electrode 15. The mask is provided with an opening in the transistor formation region and the upper surface of the protection diode. Subsequently, a metal film is formed by sputtering using a mask. The metal film is preferably a refractory metal such as a cobalt film or a nickel film, but may be a metal having a relatively low melting point. Thereafter, the metal film is heated to react with silicon. Thus, as shown in FIGS. 1C and 1D, a cobalt silicide layer and a nickel silicide layer are formed on the upper surface of the gate electrode 15, the source / drain regions 19, the protective electrode 16, and the protective diode 20, respectively. Thus, the metal silicide layers 21A and 21B are formed. Through the steps up to here, a transistor (semiconductor element) T1 including the gate insulating film 13, the gate electrode 15, and the source / drain region 19 is formed for each active region of the silicon substrate 1. Note that a transistor or a protective diode may be formed in an element formation region in which the well 10 shown in FIG. 1A is formed or in another element formation region. The method for forming the transistor and the protection diode is the same as described above. In addition, two or more transistors or protective diodes may be formed in one element formation region 3.

Next, steps required until a sectional structure shown in FIGS. 1E and 1F is obtained will be described.
First, a first interlayer insulating film 21 is formed on the entire surface of the silicon substrate 1 including transistors. For the first interlayer insulating film 21, for example, a stacked structure of a silicon nitride film and a silicon oxide (SiO ₂ ) film can be employed. The silicon nitride film is formed by plasma CVD, for example. The silicon oxide film is formed to a thickness of, for example, 450 nm to 550 nm, for example, by plasma CVD using TEOS (tetra ethoxy silane) gas. The surface of the first interlayer insulating film 21 is polished using a chemical mechanical polishing (CMP) method, and the film thickness from the surface of the silicon substrate 1 to the surface of the first interlayer insulating film 21 is a predetermined value. For example, it is adjusted to about 150 nm to 250 nm.

  Further, after applying a resist film (not shown) on the first interlayer insulating film 21, an opening is formed in the resist film by a photolithography technique. A plurality of openings are formed above the gate electrode 15 of the transistor, above the source / drain region 19, above the protective electrode 16, and above the protective diode 20. Subsequently, the first interlayer insulating film 21 is processed by dry etching using the resist film as a mask to form a plurality of contact holes 22, 23, and 24. The etching depth is set to reach the metal silicide layers 21A and 21B or the protection diode 20. As a result, contact holes 22 are formed on the gate electrode 15 and the protection electrode 16, respectively. A contact hole 23 is formed on the protection diode 20. Further, a contact hole 24 is formed on the source / drain region 19. Further, thereafter, a resist film (not shown) is removed by ashing or the like.

  Subsequently, conductive plugs 27A, 27B, 28, and 29 are formed in the contact holes 22, 23, and 24, respectively. Specifically, first, an adhesion layer is formed on the inner surfaces of the contact holes 22, 23, and 24 by sputtering. The adhesion layer is formed by stacking a titanium film with a thickness of 3 nm to 7 nm and a titanium nitride film with a thickness of 3 nm to 7 nm. Further, a tungsten film is grown on the adhesion film by a CVD method. The tungsten film is embedded in each contact hole 22, 23, 24 and grown to a thickness of, for example, 150 nm to 250 nm above the first interlayer insulating film 21. Thereafter, the excess tungsten film and the adhesion film grown on the first interlayer insulating film 21 are removed by polishing using a CMP (Chemical Mechanical Polishing) method. As a result, a conductive plug 27A electrically connected to the gate electrode 15 and a conductive plug 27B electrically connected to the protective electrode 16 are formed in the contact hole 22. Further, a conductive plug 28 that is electrically connected to the protection diode 20 is formed in the contact hole 23. Further, a conductive plug 29 that is electrically connected to the source / drain region 19 is formed in the contact hole 24.

Next, steps required until a sectional structure shown in FIG.
First, a second interlayer insulating film 31 such as a silicon oxide film is formed on the first interlayer insulating film 21. Subsequently, the second interlayer insulating film 31 is dry-etched using a resist film (not shown) as a mask to form wiring grooves 32 and 33. Further, a TaN film is formed to a thickness of about 8 nm by sputtering, for example, on the entire surface of the second interlayer insulating film 31 including the wiring trench 32. Thereafter, a Cu film as a conductive material is formed on the TaN film by a plating method. The thickness of the Cu film is set to 350 nm to 400 nm, for example. The excess Cu film and TaN film on the surface are sequentially removed by polishing by the CMP method. By this polishing, first-layer wirings 35 and 36 are formed. The wiring 35 is electrically connected to the conductive plugs 27A and 28. As a result, the transistor T1 and the protection diode 20 are electrically connected to have the same potential. Further, the wiring 36 is electrically connected to the conductive plug 27B. Thereafter, the semiconductor device 51 is manufactured by forming the required number of wiring structures. Also, other elements are formed in the multilayer wiring structure as necessary.

  Here, as shown in an example of a planar shape in FIG. 2, the gate electrode 15 of the transistor T <b> 1 and the protection diode 20 are electrically connected via a wiring 35. In addition, the protective electrode 16 around the protective diode 20 is connected to a potential at which the transistor T1 is turned off by the wiring 36. The protective electrode 16 is connected to a potential at which the channel of the gate electrode 15 is turned off or the same potential as the gate electrode 15. As one example, when the transistor T1 is N-type, the protective electrode 16 is connected to a GND power supply (P-type well) (not shown) or the like.

  Here, as shown in FIGS. 1G and 2, the length of the gate insulating film 14 and the protective electrode 16 on the protective diode forming region 12 between the transistor T1 to be protected and the protective diode 20, that is, the protective diode forming region. The covering amount (width) of the protective electrode 16 with respect to 12 is W1. The covering amount W1 is in a relationship of W2 ≦ W1 with respect to the gate electrode width W2 in the source / gate / drain arrangement direction of the transistor T1. By making the covering amount W1 larger than the gate electrode width W2, it is possible to prevent leakage current from flowing to the protective diode 20. The covering amount W1 is preferably adjusted so that the leakage current between the protection diode 20 and the transistor T1 is smaller than the leakage current in the subthreshold region of the transistor T1.

  The length of the protective electrode 16 on the element isolation insulating film 2, that is, the covering width W3 of the protective electrode 16 to the element isolation insulating film 2 is W3> in consideration of the width variation in manufacturing, alignment accuracy, and the like. 0. Thereby, it is possible to prevent the occurrence of a leak current along the element isolation insulating film 3 between the transistor T1 and the protection diode 20.

  In the structure without the protective electrode 16, for example, a leakage current flows from the source / drain region 19 of the transistor T1 to the protective diode 20. For this reason, when the threshold voltage of the transistor T1 is increased, when the transistor T1 is turned off, a leakage current greater than or equal to the off current flows from the source / drain region 19 of the transistor T1 to the protection diode 20. On the other hand, in the semiconductor device 51 of the embodiment, since the leakage electrode along the side wall of the element isolation insulating film 2 is suppressed by having the protective electrode 16, even if a leakage current in the subthreshold region is generated, the protection device 16 is protected. It is prevented from flowing to the diode 20, and the transistor T1 can be turned off.

  As described above, the semiconductor device 51 includes a stacked structure of the gate insulating film 14 and the protective electrode 16 between the transistor T1 and the protective diode 20 in a configuration in which no well is used. The channel was turned off or connected to the same potential as the gate electrode 15. As a result, generation of leakage current along the element isolation insulating film 2 is suppressed, subthreshold leakage can be reduced, and power consumption can be achieved. In addition, since it is not necessary to form an impurity implantation region around the protective diode 20, high integration of the semiconductor circuit can be achieved. Further, the manufacturing process of the gate insulating film 14 and the manufacturing process of the protective electrode 16 can be performed simultaneously with the manufacturing process of the gate insulating film 13 and the manufacturing process of the gate electrode 15 of the transistor T1, respectively, under the same conditions. Leakage current can be suppressed and semiconductor circuits can be highly integrated without increasing the number of steps.

Here, a modification of the embodiment will be described.
In the modification shown in FIGS. 3 and 4, the conductive plug 27 </ b> B electrically connected to the protective electrode 16 is connected to the wiring 35. As a result, the protective electrode 16 is electrically connected to the gate electrode 15 and the protective diode 20 via the wiring 35. In this modified example, the protective electrode 16 has the same potential as that of the gate electrode 15 and the protective diode 20, thereby preventing leakage current.

In the modification shown in FIGS. 5 and 6, one conductive plug 27 </ b> C is connected to the protection diode 20 and the protection electrode 16. In this modified example, the protective electrode 16 has the same potential as that of the gate electrode 15 and the protective diode 20, thereby preventing leakage current.
The semiconductor device 51 according to these modified examples can be manufactured by the same method as described above.

(Second Embodiment)
A second embodiment will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same component as 1st Embodiment. Moreover, the description which overlaps with 1st Embodiment is abbreviate | omitted.

First, steps required until a sectional structure shown in FIG.
First, an element isolation insulating film 2 is formed on a P-type silicon substrate 1. In at least one transistor formation region 11, for example, an N-type impurity is implanted to form an N-type well 10. Further, impurities are not implanted into the at least one transistor formation region 11 and the well 10 is not formed. Further, a protection diode formation region 12 is adjacent to the transistor formation region 11 where the well 10 is not formed. No well is formed in the protective diode formation region 12. That is, these element formation regions 11 and 12 have the same impurity concentration and are equal to the impurity concentration of the silicon substrate 1.

  Subsequently, a first gate insulating film 13 is formed with a first thickness h1 in the transistor formation region 11 where the well 10 is not formed. Further, a second gate insulating film 61, which is a protective insulating film, is formed to a second thickness h2 in the transistor forming region 11 in which the well 10 is formed and the protective diode forming region 12. The second thickness h2 of the second gate insulating film 61 is thicker than the first thickness h1 of the first gate insulating film 13.

Next, steps required until a sectional structure shown in FIG.
A gate electrode 15 is formed on each gate insulating film 13, 61 in the transistor formation region 11. Further, the protective electrode 16 is formed on the second gate insulating film 61 in the protective diode formation region 12. The protective electrode 16 is also formed on part of the element isolation insulating film 2 that partitions the protective diode formation region 12. Thereafter, the same process as in the first embodiment is performed, and the transistor T1 is formed in the transistor formation region 11 that does not have the well 10. Further, the transistor T2 is formed in the transistor formation region 11 on the well 10. Further, the protection diode 20 is formed in the protection diode formation region 12. The protection target of the protection diode 20 is the transistor T1 disposed with the element isolation insulating film 2 interposed therebetween.

Further, steps required until a sectional structure shown in FIG.
First, a first interlayer insulating film 21 is formed on the entire surface of the silicon substrate 1 including transistors. In the first interlayer insulating film 21, conductive plugs 27A, 27B, 27C, 28, and 29 are embedded. A conductive plug 27C is electrically connected to the gate electrode 15 of the transistor T2. Further, a second interlayer insulating film 31 is formed on the first interlayer insulating film 21, and wirings 35, 36, and 37 are formed. The arrangement of the wirings 35 to 37, the transistor T1, the protective electrode 16, and the protective diode 20 in plan view is the same as that in FIG. Thereafter, the semiconductor device 71 is manufactured by forming the required number of wiring structures. Also, other elements are formed in the multilayer wiring structure as necessary.

  In this semiconductor device 71, the thickness h2 of the second gate insulating film 61 under the protective electrode 16 around the protective diode 20 is thicker than the thickness h1 of the first gate insulating film 13 of the transistor T1 to be protected. Therefore, the leakage current flowing through the protective diode 20 can be further reduced as compared with the case where the film thickness is the same, and the transistor T1 having a higher threshold voltage than that in the first embodiment can be formed.

  Here, in the semiconductor device 71, the lengths of the gate insulating film 14 and the protective electrode 16 in the protective diode formation region 12 between the transistor T 1 to be protected and the protective diode 20, that is, the protective electrode on the protective diode formation region 12. The covering amount (width) of 16 is W4. The covering amount W4 has a relationship of W2 ≦ W4 with respect to the gate electrode width W2 in the arrangement direction of the source / gate / drain of the transistor T1. As a result, leakage current can be prevented from flowing through the protection diode 20. Since the thickness h2 of the second gate insulating film 61 is thicker than the thickness h1 of the gate insulating film 13 of the transistor T1 to be protected, the covering amount W4 of the protective electrode 16 on the protective diode formation region 12 is The covering amount W1 of the first embodiment can be made smaller.

  In this semiconductor device 71, operations and effects similar to those of the first embodiment can be obtained. Here, the manufacturing process of the second gate insulating film 61 in the protection diode forming region 12 can be formed simultaneously with the manufacturing process of the second gate insulating film 61 in the transistor T2 and under the same conditions, so that the manufacturing process increases. There is nothing.

Here, a modified example of the embodiment will be described.
In the semiconductor device 81 shown in FIG. 8, the protective electrode 16 is formed in a region inside the element isolation insulating film 3. That is, the covering amount W4 of the protective electrode 16 and the element isolation insulating film 3 becomes zero. For this purpose, a metal silicide layer 21B is formed in the protective diode forming region 12 exposed between the element isolation insulating film 3 and the protective electrode 16. In this semiconductor device 81, even if the covering amount W4 is zero, the leakage of the transistor T1 can be suppressed to an increase in junction leakage when the covering amount W4 is zero, and the transistor T1 having a high threshold voltage can be manufactured. This also applies to the semiconductor device 51.

  All examples and conditional expressions given here are intended to help the reader understand the inventions and concepts that have contributed to the promotion of technology, and such examples and It is to be construed without being limited to the conditions, and the organization of such examples in the specification is not related to showing the superiority or inferiority of the present invention. While embodiments of the present invention have been described in detail, various changes, substitutions and variations can be made thereto without departing from the spirit and scope of the present invention.

The features of the above embodiment will be added below.
(Appendix 1)
A transistor disposed in a first element formation region on a silicon substrate;
A protective diode disposed in a second element formation region on the silicon substrate and electrically connected to a gate electrode of the transistor;
An element isolation insulating film disposed between the first element formation region and the second element formation region;
A protective insulating film disposed in the second element formation region between the protective diode and the transistor;
A protective electrode disposed on the protective insulating film and connected to the potential at which the channel of the gate electrode is turned off or the same potential as the gate electrode;
A semiconductor device including:
(Appendix 2)
The semiconductor device according to appendix 1, wherein an impurity concentration of the first element formation region is equal to an impurity concentration of the second element formation region.
(Appendix 3)
The semiconductor device according to appendix 2, wherein the impurity concentration of the first element formation region and the second element formation region is equal to the impurity concentration of the silicon substrate.
(Appendix 4)
Additional widths of the protective insulating film and the protective electrode arranged between the protective diode and the transistor on the second element formation region are larger than a gate length of the transistor. The semiconductor device according to any one of the above.
(Appendix 5)
5. The semiconductor device according to claim 1, wherein the protective electrode extends above an element isolation insulating film between the transistor and the protective diode.
(Appendix 6)
The semiconductor device according to any one of appendix 1 to appendix 5, wherein the protective insulating film is thicker than the gate insulating film of the transistor.
(Appendix 7)
The semiconductor device according to any one of appendices 1 to 6, wherein the protective electrode is electrically connected to the gate electrode and the protective diode.
(Appendix 8)
Forming an element isolation insulating film on the silicon substrate to define a first element formation region and a second element formation region;
Forming a transistor in the first element formation region;
Forming a protective diode in the second element formation region;
After forming a protective insulating film in a region closer to the transistor than the protective diode in the second element formation region, a protective electrode is formed on the protective insulating film,
Electrically connecting the protection diode and the gate electrode of the transistor;
A method for manufacturing a semiconductor device, comprising: connecting the protective electrode to a potential at which a channel of the gate electrode is turned off or to the same potential as the gate electrode.
(Appendix 9)
The semiconductor device according to appendix 8, wherein an impurity concentration of the first element formation region is equal to an impurity concentration of the second element formation region.
(Appendix 10)
The method for manufacturing a semiconductor device according to appendix 9, wherein the impurity concentration of the first element formation region and the second element formation region is equal to the impurity concentration of the silicon substrate.
(Appendix 11)
11. The semiconductor device according to any one of appendices 8 to 10, wherein the gate insulating film and the protective insulating film of the transistor are formed simultaneously, and the gate electrode and the protective electrode of the transistor are formed simultaneously. Production method.
(Appendix 12)
The widths of the protective insulating film and the protective electrode disposed between the protective diode and the transistor on the second element formation region are formed larger than the gate length of the transistor. 11. The semiconductor device according to claim 11.
(Appendix 13)
13. The semiconductor device according to any one of appendices 8 to 12, wherein the protective insulating film is formed thicker than a thickness of a gate insulating film of the transistor.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Element isolation insulating film 11 Transistor formation area (1st element formation area)
12 Protection diode formation region (second element formation region)
13 Gate insulating film 14 Gate insulating film (protective insulating film)
15 Gate electrode 16 Protective electrode 20 Protective diode 61 Second gate insulating film (protective insulating film)
T1, T2 Transistors W1, W4 Covering amount (width)

Claims (7)

A transistor disposed in a first element formation region on a silicon substrate;
A protective diode disposed in a second element formation region on the silicon substrate and electrically connected to a gate electrode of the transistor;
An element isolation insulating film disposed between the first element formation region and the second element formation region;
A protective insulating film disposed in the second element formation region between the protective diode and the transistor;
A protective electrode disposed on the protective insulating film and connected to the potential at which the channel of the gate electrode is turned off or the same potential as the gate electrode;
A semiconductor device including:   2. The semiconductor device according to claim 1, wherein the impurity concentration of the first element formation region is equal to the impurity concentration of the second element formation region.   The width of the protective insulating film and the protective electrode disposed between the protective diode and the transistor on the second element formation region is larger than a gate length of the transistor. Item 3. The semiconductor device according to Item 2.   4. The semiconductor device according to claim 1, wherein the protective insulating film is thicker than the gate insulating film of the transistor. Forming an element isolation insulating film on the silicon substrate to define a first element formation region and a second element formation region;
Forming a transistor in the first element formation region;
Forming a protective diode in the second element formation region;
After forming a protective insulating film in a region closer to the transistor than the protective diode in the second element formation region, a protective electrode is formed on the protective insulating film,
Electrically connecting the protection diode and the gate electrode of the transistor;
A method for manufacturing a semiconductor device, comprising: connecting the protective electrode to a potential at which a channel of the gate electrode is turned off or to the same potential as the gate electrode.   6. The semiconductor device according to claim 5, wherein the impurity concentration of the first element formation region is equal to the impurity concentration of the second element formation region.   7. The method for manufacturing a semiconductor device according to claim 5, wherein the gate insulating film and the protective insulating film of the transistor are formed simultaneously, and the gate electrode and the protective electrode of the transistor are formed simultaneously.

Images