JP2009231585A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which alleviates the plasma charging to a gate insulating film using a plasma process, and to provide a manufacturing method thereof. <P>SOLUTION: The method for manufacturing the semiconductor device forms a gate insulating film 4 and a gate electrode 5 in such an order on a substrate, and forms a first interlayer insulating film 8 followed by formation of contact holes 11a, 11b, and 11c as well as a groove 11, into which W plugs 9a, 9b, 9c and 9 are embedded. Thereafter, the method forms Al wires 10a, 10b and 10c, an Al shielding wire 10 to surround the gate electrode and a protection diode, a second interlayer insulating film 12, and via holes 15 and 15a, into which W plugs 13 and 13a are embedded. The method includes a step of forming an Al wire 14, and the W plugs 13 and 13a are electrically connected with each other using a third wire 14. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device and a manufacturing method thereof that can alleviate plasma charge to a gate insulating film by a plasma process.

FIG. 3 is a plan view showing a conventional semiconductor device, which is a high voltage transistor.
As shown in FIG. 3, a low concentration impurity region 3a is formed in the silicon substrate. Thereafter, a LOCOS oxide film (not shown) that functions as an element isolation film is formed on the silicon substrate. Next, the silicon substrate is thermally oxidized to form a gate insulating film (not shown) on the silicon substrate, and the gate electrode 5 is formed on the gate insulating film. Further, by introducing impurities into the silicon substrate using the LOCOS oxide film and the gate electrode 5 as a mask, an impurity region 7c serving as a source / drain is formed. In this way, a high breakdown voltage transistor is formed.

  Thereafter, a first interlayer insulating film (not shown) is formed on the gate insulating film and the gate electrode. Next, in the first interlayer insulating film and the gate insulating film, a contact hole 11a located on the impurity region 7c, a contact hole (not shown) located on the gate electrode 5, and a silicon substrate around the high breakdown voltage transistor An upper contact hole (not shown) is formed. Thereafter, a first W plug (not shown) is buried in the contact hole, and a first Al wiring 10 is formed on the first interlayer insulating film and the first W plug. Thereby, the first Al wiring 10 formed so as to surround the high breakdown voltage transistor is electrically connected to the silicon substrate via the first W plug. The first Al wiring 10 forms an Al shield for fixing the substrate potential surrounding the high voltage transistor. Next, a second interlayer insulating film (not shown) is formed on the first interlayer insulating film and the first Al wiring 10, and a via hole (not shown) is formed in the second interlayer insulating film. . After that, a second W plug (not shown) is embedded in the via hole, and the second Al wiring 14 electrically connected to the gate electrode 5 on the second interlayer insulating film and the second W plug. Is formed. (For example, see Patent Document 1)

JP2007-165766 (paragraphs 0023-0025)

  In recent semiconductor device manufacturing processes, there are many processing processes using plasma. Further, with the use of the plasma process, destruction or damage of the gate insulating film under the gate electrode due to a charge-up phenomenon in the plasma process has become a serious problem. Further, the gate insulating film is damaged by the plasma process, which may affect the transistor characteristic shift.

  Further, as shown in FIG. 3, the gate electrode 5 is not connected to the protective diode. Therefore, it does not have a structure for releasing plasma charge, and the gate insulating film under the gate electrode is easily damaged by plasma.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device capable of alleviating plasma damage to a gate insulating film due to a charge-up phenomenon that occurs when a plasma process is used. And a manufacturing method thereof.

In order to solve the above problems, a method for manufacturing a semiconductor device according to the present invention includes a first conductivity type semiconductor substrate,
A gate insulating film formed on the semiconductor substrate;
A gate electrode formed on the gate insulating film;
A second conductivity type source / drain diffusion layer formed on the semiconductor substrate;
A first shielding diffusion layer of a first conductivity type formed on the semiconductor substrate and disposed so as to surround the gate electrode and the source / drain diffusion layer;
A diffusion layer for a protective diode of a second conductivity type formed on the semiconductor substrate and disposed outside the diffusion layer for the first shield;
A second shielding diffusion layer of a first conductivity type formed on the semiconductor substrate and disposed so as to surround the diffusion layer for the protective diode;
A first interlayer insulating film formed on the gate electrode and the semiconductor substrate;
A first contact hole formed in the first interlayer insulating film and located on the gate electrode;
A second contact hole formed in the first interlayer insulating film and located on the diffusion layer for the protective diode;
A first groove formed in the first interlayer insulating film, located on the first shielding diffusion layer and disposed so as to surround the gate electrode;
A second groove formed in the first interlayer insulating film, located on the second shield diffusion layer and disposed so as to surround the second contact hole;
A first conductive film embedded in the first contact hole;
A second conductive film embedded in the second contact hole;
A third conductive film embedded in the first groove;
A fourth conductive film embedded in the second groove;
A first wiring formed on the first conductive film and the first interlayer insulating film;
A second wiring formed on the second conductive film and the first interlayer insulating film;
A first shield wiring formed on the third conductive film and the first interlayer insulating film and disposed so as to surround the first wiring;
A second shield wiring formed on the fourth conductive film and the first interlayer insulating film and disposed so as to surround the second wiring;
The first and second wirings, the first and second shield wirings, a second interlayer insulating film formed on the first interlayer insulating film;
A first via hole formed in the second interlayer insulating film and positioned on the first wiring;
A second via hole formed in the second interlayer insulating film and positioned on the second wiring;
A fifth conductive film embedded in the first via hole;
A sixth conductive film embedded in the second via hole;
A third wiring formed on each of the second interlayer insulating film and the fifth and sixth conductive films;
Comprising
The fifth conductive film and the sixth conductive film are electrically connected by the third wiring,
The gate electrode, the gate insulating film, and the source / drain diffusion layer constitute a high breakdown voltage transistor.

  In the method for manufacturing a semiconductor device according to the present invention, each of the first to sixth conductive films is preferably a W film.

  In the method for manufacturing a semiconductor device according to the present invention, the high breakdown voltage transistor is preferably a transistor that operates with a voltage of 7 V or more.

In the method for manufacturing a semiconductor device according to the present invention, a step of forming a gate insulating film on the first conductivity type semiconductor substrate;
Forming a gate electrode on the gate insulating film;
Forming a source / drain diffusion layer and a protective diode diffusion layer in the semiconductor substrate by introducing impurity ions of a second conductivity type into the semiconductor substrate;
By introducing impurity ions of the first conductivity type into the semiconductor substrate, the first shield diffusion layer and the protection diode diffusion layer shaped to surround the gate electrode and the source / drain diffusion layer are surrounded. Forming a second shielding diffusion layer having a shape on the semiconductor substrate;
Forming a first interlayer insulating film on the gate electrode and the semiconductor substrate;
A first contact hole located on the gate electrode; a second contact hole located on the protective diode diffusion layer; a first shield diffusion layer; and Forming a first groove shaped to surround the gate electrode and a second groove located on the second shield diffusion layer and shaped to surround the second contact hole;
First to fourth conductive films are embedded in the first contact hole, the second contact hole, the first groove, and the second groove, respectively. And a first wiring is formed on the first interlayer insulating film, a second wiring is formed on the second conductive film and the first interlayer insulating film, and the third wiring is formed. Forming a first shield wiring having a shape surrounding the first wiring on the conductive film and the first interlayer insulating film; and forming the fourth conductive film and the first interlayer insulating film. Forming a second shield wiring having a shape surrounding the second wiring;
Forming a second interlayer insulating film on the first and second wirings, the first and second shielding wirings, and the first interlayer insulating film;
Forming a first via hole located on the first wiring and a second via hole located on the second wiring in the second interlayer insulating film;
Fifth and sixth conductive films are embedded in the first and second via holes, respectively, and third wirings are formed on the second interlayer insulating film and the fifth and sixth conductive films, respectively. And the process of
Comprising
The fifth conductive film and the sixth conductive film are electrically connected by the third wiring,
The gate electrode, the gate insulating film, and the source / drain diffusion layer constitute a high breakdown voltage transistor.

  According to the semiconductor device manufacturing method of the present invention, the gate electrode surrounded by the first shield wiring includes the first conductive film, the first wiring, and the first wiring buried in the first contact hole. The fifth conductive film embedded in the via hole, the third wiring, the sixth conductive film embedded in the second via hole, the second wiring, and the second conductive film embedded in the second contact hole. A protective diode surrounded by the second shield wiring is connected via a conductive film. As a result, it is possible to suppress the breakdown or damage of the gate insulating film due to the plasma charge in the process of forming the third wiring and the charge-up phenomenon by the process using plasma after the process of forming the third wiring.

  In the method for manufacturing a semiconductor device according to the present invention, it is possible to further include a step using plasma after the step of forming the third wiring.

  According to the semiconductor device manufacturing method of the present invention, the gate electrode and the protection diode are electrically connected by forming the third wiring. Therefore, in the process using plasma after the process of forming the third wiring, plasma charge can be discharged from the protection diode to the substrate, and plasma damage to the gate insulating film under the gate electrode can be suppressed. it can.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 2 is a plan view for explaining the semiconductor device according to the embodiment of the present invention. FIGS. 1A to 1C are cross-sectional views for explaining a method of manufacturing the semiconductor device shown in FIG. 2, and FIG. 1C is a cross-sectional view taken along line AA ′ shown in FIG.

  First, as shown in FIG. 1A, a LOCOS oxide film 6 located in an element isolation region is formed on a silicon substrate 1 by a LOCOS method using a silicon nitride film (not shown) of the silicon substrate 1 as a selective oxidation mask. Next, a P-type well region 2 is formed on the silicon substrate 1.

  Next, a resist pattern (not shown) is formed on the silicon substrate 1. N-type impurity ions are implanted into the silicon substrate 1 using this resist pattern as a mask. As a result, the N-type low concentration impurity region 3 a of the N-type transistor and the N-type low concentration impurity region 3 b of the protection diode are formed in the P-type well region 2. Thereafter, the resist pattern is removed.

  Next, a gate oxide film to be the gate insulating film 4 is formed on the silicon substrate 1 by a thermal oxidation method. Next, a Poly-Si film is formed on the gate insulating film 4 and the LOCOS oxide film 6 by a CVD method, and this Poly-Si film is processed using a photolithography and a dry etching method to obtain a gate insulating film. A gate electrode 5 is formed on 4.

  Thereafter, a resist pattern (not shown) is formed on the gate electrode 5, the gate insulating film 4 and the LOCOS oxide film 6, and N-type impurity ions are formed on the silicon substrate 1 using the resist pattern, the gate electrode 5 and the LOCOS oxide film 6 as a mask. Inject. As a result, an N-type impurity region 7c serving as a source / drain region of the N-type transistor is formed in the N-type low-concentration impurity region 3a, and a protection diode N-type impurity region 7b is formed in the N-type low-concentration impurity region 3b. Is done.

  Next, a resist pattern (not shown) is formed on the gate electrode 5, the gate insulating film 4, and the LOCOS oxide film 6, and P-type impurity ions are formed on the silicon substrate 1 using the resist pattern, the gate electrode 5 and the LOCOS oxide film 6 as a mask. Inject. As a result, a P-type shielding impurity region 7 a is formed in the silicon substrate 1. The P-type shield impurity region 7a is disposed so as to surround the gate electrode 5 and the source / drain regions, and to surround the N-type impurity region 7b and the N-type low concentration impurity region 3b of the protective diode. It becomes a diffusion layer for use.

  Thereafter, as shown in FIG. 1B, a first interlayer insulating film 8 is formed on the entire surface including the gate electrode 5 and the gate insulating film 4 by a CVD method. Next, a resist pattern (not shown) is formed on the first interlayer insulating film 8. Next, by using this resist pattern as a mask, the first interlayer insulating film 8 and the gate insulating film 4 are etched, whereby a trench 11 located on the P-type shield impurity region 7a and a position contact hole on the source / drain region 7c. 11a, contact hole 11b located on the gate electrode and contact hole 11c located on N-type impurity region 7b are formed. The trench 11 is disposed so as to surround the gate electrode 5 and the contact holes 11a and 11b and to surround the contact hole 11c.

  Thereafter, a W film is formed in the trench 11, the contact holes 11a, 11b and 11c and on the first interlayer insulating film 8 by a CVD method, and the W film located on the first interlayer insulating film 8 is removed by a CMP method. To do. As a result, the first W plugs 9, 9a, 9b and 9c are embedded in the groove 11 and the contact holes 11a, 11b and 11c.

  Next, an Al alloy film is formed on the first interlayer insulating film 8 and the first W plugs 9, 9a, 9b and 9c by sputtering. Thereafter, a resist pattern (not shown) is formed on the Al alloy film, and the Al alloy film is etched using the resist pattern as a mask, so that the first Al wirings 10, 10a, 10b and 10c are formed. Further, the first Al wiring 10 positioned on the first W plug 9 forms two ring-shaped Al shields surrounding the first Al wirings 10a and 10b and surrounding the first Al wiring 10c. is doing.

  Thereafter, as shown in FIG. 1C, a second interlayer insulating film 12 is formed on the first interlayer insulating film 8 and the first Al wirings 10, 10a, 10b and 10c by the CVD method. Next, a resist pattern (not shown) is formed on the second interlayer insulating film 12. Next, by etching the second interlayer insulating film 12 using this resist pattern as a mask, the second interlayer insulating film 12 is positioned above the gate electrode 5 and above the first Al wiring 10b. A via hole 15 is formed which is located above the via hole 15a and the N-type impurity region 7b of the protective diode and on the first Al wiring 10c.

  Thereafter, a W film is formed in the via holes 15 and 15a and on the second interlayer insulating film 12 by the CVD method, and the W film located on the second interlayer insulating film 12 is removed by the CMP method. As a result, the second W plugs 13 and 13a are embedded in the via holes 15 and 15a.

  Next, an Al alloy film is formed on the second interlayer insulating film 12 and the second W plugs 13 and 13a by sputtering. Thereafter, a resist pattern (not shown) is formed on the Al alloy film, and the Al alloy film is dry-etched using the resist pattern as a mask, whereby a second Al wiring 14 is formed on the second interlayer insulating film 12. Is done. The second Al wiring 14 is electrically connected to the second W plugs 13a and 13 respectively. Thereafter, an Al wiring higher than the second Al wiring 14 is formed by a known plasma process.

  As shown in FIG. 2, the semiconductor device thus fabricated includes a high breakdown voltage transistor having a gate electrode 5 and source / drain regions 3a, a ring-shaped Al shield surrounding the transistor, and an N-type impurity region. 7b, and a ring-shaped Al shield surrounding the protection diode. The gate electrode 5 in the transistor is electrically connected to the second Al wiring 14 via the first W plug 9b in the contact hole 11b, the first Al wiring 10b, and the second W plug 13 in the via hole 15a. It is connected to the. The second Al wiring 14 straddles the Al shield by the first Al wiring 10, and the first W plug 9 c in the contact hole 11 c, the first Al wiring 10 c and the second W in the via hole 15. The plug 13a is electrically connected to the N-type impurity region 7b of the protective diode having the same structure as the source / drain structure of the transistor. Note that the high breakdown voltage transistor in this embodiment refers to a transistor having an operating voltage of 7V or more, and a preferable operating voltage is about 30V.

  As described above, according to the embodiment of the present invention, the first Al wiring 10 has the Al shield structure surrounding the transistor in order to fix the substrate potential and prevent the field inversion. The Al wiring 14 is connected to the protection diode. Therefore, it is possible to discharge the plasma charge in the process of forming the second Al wiring 14 and the plasma charge in the process using the plasma after the process of forming the second Al wiring 14 from the protective diode to the substrate. Plasma damage to the gate insulating film 4 under the gate electrode 5 can be suppressed.

  The structure of the protection diode is the same as that of the source / drain of the high voltage transistor. Therefore, the number of process steps is not increased by installing the protective diode. Further, the protective diode also has a shield structure by the first Al wiring 10 like the transistor. For this reason, it can suppress affecting other elements at the time of operation | movement of a high voltage | pressure-resistant transistor.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, in the above embodiment, the protective diode that discharges plasma charge generated during the plasma process can be shared with a plurality of transistors having gate electrodes used at the same potential. In other words, instead of providing protective diodes for a plurality of high voltage transistors having gate electrodes used at the same potential, the gate electrodes of the plurality of high voltage transistors are electrically connected to one protective diode. It is also possible to adopt a configuration in which

(A)-(c) is sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment. FIG. 2 is a plan view of the semiconductor device shown in FIG. The top view for demonstrating the structure of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... P well area | region, 3a, 3b ... N-type low concentration impurity area | region, 4 ... Gate insulating film, 5 ... Gate electrode, 6 ... LOCOS oxide film , 7a... P-type impurity region for shielding, 7b... N-type impurity region, 7c... Source / drain region (N-type impurity region), 8. , 9b, 9c ... first W plug, 10 ... Al shield, 10a, 10b, 10c ... first Al wiring, 11, 11a, 11b, 11c ... contact hole, 12 ... Second interlayer insulating film, 13, 13a ... second W plug, 14 ... second Al wiring, 15, 15a ... via hole

Claims (5)

A first conductivity type semiconductor substrate;
A gate insulating film formed on the semiconductor substrate;
A gate electrode formed on the gate insulating film;
A second conductivity type source / drain diffusion layer formed on the semiconductor substrate;
A first shielding diffusion layer of a first conductivity type formed on the semiconductor substrate and disposed so as to surround the gate electrode and the source / drain diffusion layer;
A diffusion layer for a protective diode of a second conductivity type formed on the semiconductor substrate and disposed outside the diffusion layer for the first shield;
A second shielding diffusion layer of a first conductivity type formed on the semiconductor substrate and disposed so as to surround the diffusion layer for the protective diode;
A first interlayer insulating film formed on the gate electrode and the semiconductor substrate;
A first contact hole formed in the first interlayer insulating film and located on the gate electrode;
A second contact hole formed in the first interlayer insulating film and located on the diffusion layer for the protective diode;
A first groove formed in the first interlayer insulating film, located on the first shielding diffusion layer and disposed so as to surround the gate electrode;
A second groove formed in the first interlayer insulating film, located on the second shield diffusion layer and disposed so as to surround the second contact hole;
A first conductive film embedded in the first contact hole;
A second conductive film embedded in the second contact hole;
A third conductive film embedded in the first groove;
A fourth conductive film embedded in the second groove;
A first wiring formed on the first conductive film and the first interlayer insulating film;
A second wiring formed on the second conductive film and the first interlayer insulating film;
A first shield wiring formed on the third conductive film and the first interlayer insulating film and disposed so as to surround the first wiring;
A second shield wiring formed on the fourth conductive film and the first interlayer insulating film and disposed so as to surround the second wiring;
The first and second wirings, the first and second shield wirings, a second interlayer insulating film formed on the first interlayer insulating film;
A first via hole formed in the second interlayer insulating film and positioned on the first wiring;
A second via hole formed in the second interlayer insulating film and positioned on the second wiring;
A fifth conductive film embedded in the first via hole;
A sixth conductive film embedded in the second via hole;
A third wiring formed on each of the second interlayer insulating film and the fifth and sixth conductive films;
Comprising
The fifth conductive film and the sixth conductive film are electrically connected by the third wiring,
2. A semiconductor device according to claim 1, wherein a high breakdown voltage transistor is constituted by the gate electrode, the gate insulating film, and the source / drain diffusion layer.   2. The semiconductor device according to claim 1, wherein each of the first to sixth conductive films is a W film.   3. The semiconductor device according to claim 1, wherein the high breakdown voltage transistor is a transistor that operates with a voltage of 7 V or more. Forming a gate insulating film on a first conductivity type semiconductor substrate;
Forming a gate electrode on the gate insulating film;
Forming a source / drain diffusion layer and a protective diode diffusion layer in the semiconductor substrate by introducing impurity ions of a second conductivity type into the semiconductor substrate;
By introducing impurity ions of the first conductivity type into the semiconductor substrate, the first shield diffusion layer and the protection diode diffusion layer shaped to surround the gate electrode and the source / drain diffusion layer are surrounded. Forming a second shielding diffusion layer having a shape on the semiconductor substrate;
Forming a first interlayer insulating film on the gate electrode and the semiconductor substrate;
A first contact hole located on the gate electrode; a second contact hole located on the protective diode diffusion layer; a first shield diffusion layer; and Forming a first groove shaped to surround the gate electrode and a second groove located on the second shield diffusion layer and shaped to surround the second contact hole;
First to fourth conductive films are embedded in the first contact hole, the second contact hole, the first groove, and the second groove, respectively. And a first wiring is formed on the first interlayer insulating film, a second wiring is formed on the second conductive film and the first interlayer insulating film, and the third wiring is formed. Forming a first shield wiring having a shape surrounding the first wiring on the conductive film and the first interlayer insulating film; and forming the fourth conductive film and the first interlayer insulating film. Forming a second shield wiring having a shape surrounding the second wiring;
Forming a second interlayer insulating film on the first and second wirings, the first and second shielding wirings, and the first interlayer insulating film;
Forming a first via hole located on the first wiring and a second via hole located on the second wiring in the second interlayer insulating film;
Fifth and sixth conductive films are embedded in the first and second via holes, respectively, and third wirings are formed on the second interlayer insulating film and the fifth and sixth conductive films, respectively. And the process of
Comprising
The fifth conductive film and the sixth conductive film are electrically connected by the third wiring,
A method of manufacturing a semiconductor device, wherein a high breakdown voltage transistor is constituted by the gate electrode, the gate insulating film and the source / drain diffusion layer.   5. The method for manufacturing a semiconductor device according to claim 4, further comprising a step of using plasma after the step of forming the third wiring.

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