JP2015192011A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate overetching of an insulation film on a side part of a fuse to prevent residual of a resist film.SOLUTION: A semiconductor device manufacturing method comprises the steps of: forming a first insulation film 85 so as to cover an electrode pad 81 and a fuse 82 which are formed on an interlayer insulation film 61 above a substrate to make a film thickness on the electrode pad 81 thinner than a film thickness on the interlayer insulation film; subsequently forming a resist film 88 above the first insulation film 85; and simultaneously forming a first opening 90A for exposing the electrode pad 81 by using the resist film 88 as a mask and a second opening 90B by removing at least a part of the first insulation film 85 on the fuse 82.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  A semiconductor device in which a semiconductor circuit is formed on a substrate such as silicon includes an electrode pad for inputting and outputting an electric signal and a fuse used for adjusting a resistance value. For example, the electrode pad is formed in the uppermost layer of a multilayer structure in which a conductor film or an insulating film is laminated, and is formed by forming an opening in a passivation film formed on the conductor film and exposing the conductor film. The fuse is formed below the uppermost layer on which the electrode pad is formed, and the fuse is exposed to form an opening by etching from the uppermost layer. Further, in order to prevent corrosion of the fuse, after forming the opening, a resist film is embedded in the opening and the surface of the fuse is covered with the resist film. When trimming the fuse, laser irradiation is performed through the opening, and the fuse is blown out while removing the resist film above the fuse.

  However, when the fuse is formed in the lower layer, it takes time to etch the opening for the fuse. Therefore, in recent semiconductor devices, it has been studied to form a fuse in the same uppermost layer as the electrode pad and to simultaneously form the use opening and the electrode pad opening. At this time, an insulating film is formed to cover the fuse and the electrode pad, and the width of the opening of the mask for etching the insulating film is made smaller than the width above the electrode pad. The width of the opening above the fuse is sized so that the etching rate of the insulating film above the fuse is sufficiently lower than the etching rate of the insulating film above the electrode pad. As a result, the opening above the fuse becomes shallower than the depth of the opening of the electrode pad, and the electrode pad is exposed, while the insulating film remains above the fuse to prevent corrosion of the fuse. Become.

JP 2007-123615 A JP-A-8-213469

  However, if the opening on the fuse is reduced, the degree of freedom in designing the size and shape of the fuse is reduced. Therefore, it has been desired to develop a process for removing the insulating film covering the fuse and exposing the fuse. Here, an example of a process for exposing the fuse will be described below.

  For example, as illustrated in FIG. 3A, after patterning the electrode pad 202 and the fuse 203 on the insulating film 201, the insulating film 204 and the passivation film 205 are sequentially stacked so as to cover the electrode pad 202 and the fuse 203. Thereafter, as shown in FIG. 3B, the passivation film 205 and the insulating film 204 are patterned using the resist film 206 as a mask to expose the electrode pad 202 and the fuse 203. At this time, the etching process for exposing the electrode pad 202 is performed under the condition that the insulating film 204 covering the electrode pad 202 is over-etched. For this purpose, the insulating film 201 around the fuse 203 is over-etched, and a groove 207 is formed in the insulating film 201 around the fuse 203. Subsequently, as illustrated in FIG. 3C, the insulating film 208 and the passivation film 209 are stacked to protect the fuse 203. At this time, since the electrode pad 202 is covered with the insulating film 208 and the passivation film 209, a resist pattern 210 that covers the fuse 203 is formed, the insulating film 208 and the passivation film 209 on the electrode pad 202 are removed by etching, and the electrode pad is formed. An opening 211 that exposes 202 is formed. By adopting such a process, it is not necessary to reduce the opening of the fuse, and the degree of freedom in designing the fuse is improved.

However, when the resist pattern 210 is peeled after the opening 211 is formed in the electrode pad 202 with the resist pattern 210 covering the fuse 203, the groove 207 of the insulating film 201 around the fuse 203 is formed as shown in FIG. Part of the resist material 210A that has entered may remain. If the resist material 210A remains in the groove 207, when the fuse 203 is trimmed with a laser, the resist material 210A is scattered by the laser and easily contaminates the surface of the semiconductor device.
The present invention has been made in view of such circumstances, and an object thereof is to eliminate over-etching of an insulating film on a side portion of a fuse and prevent a resist film from remaining.

  According to one aspect of the embodiment, an electrode pad and a fuse are formed on the uppermost interlayer insulating film in the multilayer wiring structure formed above the substrate, and the interlayer insulating film, the electrode pad, and the fuse are above the interlayer insulating film. Forming an insulating film having a film thickness on the side of the fuse above the interlayer insulating film larger than that on the electrode pad, and etching the insulating film to expose the electrode pad And a method of manufacturing a semiconductor device including an opening step of simultaneously forming a second opening from which at least a part of the insulating film above the fuse is removed.

  According to another aspect of the embodiment, the substrate, electrode pads and fuses disposed on the uppermost interlayer insulating film in the multilayer wiring structure formed above the substrate, and the interlayer insulating film An insulating film formed above, a first opening formed in the insulating film and exposing the electrode pad, and a second opening formed in the insulating film and having a bottom height higher than a bottom surface of the fuse. And a semiconductor device including the opening.

  When the first opening that exposes the electrode pad is formed, the second opening is prevented from becoming too deep to form a deep groove in the side of the fuse. The surface contamination of the semiconductor device due to the resist film remaining can be prevented.

FIG. 1A is a cross-sectional view (part 1) illustrating an example of the manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 1B is a cross-sectional view (part 2) illustrating the example of the manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 1C is a sectional view (part 3) showing an example of the manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 1D is a cross-sectional view (No. 4) showing an example of the manufacturing process of the semiconductor device according to the first embodiment of the invention. FIG. 1E is a sectional view (No. 5) showing an example of the manufacturing process of the semiconductor device according to the first embodiment of the invention. FIG. 1F is a cross-sectional view (No. 6) showing an example of the manufacturing process of the semiconductor device according to the first embodiment of the invention. FIG. 1G is a sectional view (No. 7) showing an example of the manufacturing process of the semiconductor device according to the first embodiment of the invention. FIG. 1H is a sectional view (No. 8) showing an example of the manufacturing process of the semiconductor device according to the first embodiment of the invention. FIG. 1I is a sectional view (No. 9) showing an example of the manufacturing process of the semiconductor device according to the first embodiment of the invention. FIG. 2A is a cross-sectional view (part 1) illustrating an example of the manufacturing process of the semiconductor device according to the second exemplary embodiment of the present invention. FIG. 2B is a cross-sectional view (part 2) illustrating the example of the manufacturing process of the semiconductor device according to the second embodiment of the present invention. FIG. 2C is a cross-sectional view (part 3) illustrating the example of the manufacturing process of the semiconductor device according to the second embodiment of the present invention. FIG. 2D is a sectional view (No. 4) showing an example of the manufacturing process of the semiconductor device according to the second embodiment of the present invention. FIG. 2E is a sectional view (No. 5) showing an example of the manufacturing process of the semiconductor device according to the second embodiment of the present invention. FIG. 3A is a cross-sectional view (part 1) illustrating an example of a manufacturing process of a semiconductor device according to a conventional example. FIG. 3B is a sectional view (No. 2) showing an example of the manufacturing process of the semiconductor device according to the conventional example. FIG. 3C is a cross-sectional view (part 3) illustrating the example of the manufacturing process of the semiconductor device according to the conventional example. FIG. 3D is a sectional view (No. 4) showing an example of the manufacturing process of the semiconductor device according to the conventional example. FIG. 3E is a sectional view (No. 5) showing an example of the manufacturing process of the semiconductor device according to the conventional example.

The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
The foregoing general description and the following detailed description are exemplary and explanatory only and are not intended to limit the invention.

(First embodiment)
A first embodiment will be described in detail with reference to the drawings.
First, steps required until a sectional structure shown in FIG. 1A is obtained will be described.
As shown in FIG. 1A, a plurality of element isolation regions 2 are formed on a wafer (semiconductor substrate) 1 such as silicon. For the element isolation region 2, for example, shallow trench isolation (STI) is used. The STI is formed by forming a groove in the element isolation region of the substrate 1 and embedding an insulating film such as silicon oxide therein. The element isolation region 2 is not limited to STI, and an insulating film formed by a LOCOS (Local Oxidation of Silicon) method may be used.

  Next, impurities are ion-implanted into the surface of the substrate 1 to form the wells 11 and 12. For example, when an n-type impurity such as phosphorus is introduced as a dopant impurity in the element region, the n-well 11 is formed. In addition, when a p-type impurity such as boron is introduced, a p-well 12 is formed.

  Thereafter, the surface of the transistor active region on the substrate 1 is thermally oxidized to form the gate insulating film 13. The gate insulating film 13 is a silicon oxide film formed by thermal oxidation and has a thickness of 1 to 10 nm, for example. The gate insulating film 13 may be formed of a material having a high dielectric constant.

  Thereafter, an amorphous or polycrystalline silicon film is formed on the entire surface of the substrate 1. The film thickness of the silicon film is about 100 nm, for example. The gate electrode 14 is formed by patterning the silicon film. Here, the gate electrode 14 may be formed of a metal material.

  Subsequently, by ion implantation using the gate electrode 14 as a mask, a p-type impurity such as boron is introduced on both sides of the gate electrode 14 to form a source / drain extension 15 constituting a shallow region of the extension source / drain region. . Thereafter, an insulating film is formed on the entire upper surface of the substrate 1 including the gate electrode 14. As the insulating film, for example, a silicon oxide film formed by a CVD method is used. Then, the insulating film is etched back to leave only the both side portions of the gate electrode 14 to form the insulating sidewalls 17.

  Subsequently, impurities are ion-implanted again on both sides of the gate electrode 14 using the insulating sidewall 17 and the gate electrode 14 as a mask. As a result, source / drain diffusion layers 18 that form deep regions of extension source / drain regions are formed in the substrate 1 on the side of each gate electrode 14.

  Further, a metal film is formed on the entire upper surface of the substrate 1 including the gate electrode 14 by sputtering. The metal film is preferably a refractory metal such as a cobalt film or a nickel film, but may be a metal having a relatively low melting point. Thereafter, the metal film is heated to react with silicon. As a result, a metal silicide layer 19A such as a cobalt silicide layer or a nickel silicide layer is formed on the upper surface of the gate electrode 14 and on the source / drain diffusion layer 18, respectively. By this heat treatment, each source / drain diffusion layer 18 is activated to reduce its resistance. A metal silicide layer 19B is formed on the gate electrode.

  Thereafter, the unreacted metal film on the element isolation region 2 or the like is removed by wet etching. Through the steps so far, the transistor T1 (semiconductor element) constituted by the gate insulating film 13, the gate electrode 14, the source / drain diffusion layer 18 and the like is formed for each active region of the substrate 1.

Next, a silicon nitride film 21 is formed to a thickness of, for example, 80 nm on the entire surface of the substrate 1 including the transistor T1. Each of the silicon nitride films 21 is formed by a plasma CVD method. Subsequently, as the first interlayer insulating film 22, for example, a silicon oxide (SiO ₂ ) film is formed to a thickness of 1300 nm on the silicon nitride film 21 by a plasma CVD method using TEOS (tetraethoxysilane) gas. . The surface of the first interlayer insulating film 22 is polished using a chemical mechanical polishing (CMP) method, and the film thickness from the surface of the substrate 1 to the surface of the first interlayer insulating film 22 is set to a predetermined value, for example, Adjust to about 950 nm.

  Further, after applying a resist film 23 on the first interlayer insulating film 22, an opening 23A is formed in the resist film 23 by photolithography. A plurality of openings 23A are formed above the source / drain diffusion layer 18 of the transistor T1.

Next, steps required until a sectional structure shown in FIG. 1B is obtained will be described.
The first interlayer insulating film 22 and the silicon nitride film 21 are sequentially processed by dry etching using the resist film 23 as a mask. The etching depth is set to reach the refractory metal silicide layer 19 of the source / drain diffusion layer 18. As a result, a contact hole 25 is formed on the source / drain diffusion layer 18. Thereafter, the resist film 23 is removed by ashing or the like.

  Subsequently, a conductive plug 26 electrically connected to the source / drain region 17 is formed in the contact hole 25. Specifically, first, the adhesion layer 27 is formed on the inner surface of the contact hole 25 by sputtering. The adhesion layer is formed by laminating a 30 nm titanium film and a 20 nm titanium nitride film. Further, a tungsten film 28 is grown on the adhesion film 27 by a CVD method. The tungsten film 28 is buried in each hole 25 and grown to a thickness of, for example, 300 nm above the first interlayer insulating film 22. Thereafter, excess tungsten film 28 and adhesion film 27 grown on first interlayer insulating film 22 are removed by polishing using a CMP (Chemical Mechanical Polishing) method. As a result, the conductive plug 26 is embedded in the contact hole 25.

Next, steps required until a sectional structure shown in FIG.
First, a second interlayer insulating film 31 such as a silicon oxide film is formed on the first interlayer insulating film 22. Subsequently, the second interlayer insulating film 31 is dry-etched using a resist film (not shown) as a mask to form a wiring groove 32. Further, a TaN film 33 is formed on the entire surface of the second interlayer insulating film 31 including the wiring trench 32 to a thickness of about 8 nm by sputtering, for example. Further, a Cu film 34 is formed as a conductive material on the TaN film 33 by a plating method. The thickness of the Cu film 34 is, for example, 800 nm. The Cu film 34 on the surface and the TaN film 33 are sequentially removed by polishing by the CMP method. By this polishing, a first-layer wiring 35 is formed. The wiring 35 is electrically connected to the conductive plug 26. Thereafter, as many wiring structures as necessary in the same process are formed. Also, other elements are formed in the multilayer wiring structure as necessary.

Next, steps required until a sectional structure shown in FIG. Note that FIG. 1D illustrates an example of a process of forming the uppermost layer wiring of a semiconductor device having a four-layer wiring structure, but the total number of wirings is not limited to this.
As a fourth interlayer insulating film 61, for example, a silicon oxide film is formed on the entire surface of the third interlayer insulating film to a thickness of 800 nm to 1 μm by plasma TEOSCVD. Thereafter, the surface of the fourth interlayer insulating film 61 is planarized by, eg, CMP. Next, the fourth interlayer insulating film 61 is etched using a photolithography technique. Thereby, a contact hole 62 reaching the lower wiring is formed. Further, a conductive plug 63 is formed in the contact hole 62. The method for forming the conductive plug 63 is the same as the method for forming the conductive plug 26.

  Subsequently, for example, a Ti film 71, a TiN film 72, an AlCu alloy film 73, and a TiN film 74 are sequentially stacked on the fourth interlayer insulating film 61 and the conductive plug 63 by, for example, a sputtering method. The total film thickness of these films 71 to 74 is, for example, 1.14 μm. Thereafter, a resist film (not shown) is formed on these films 71 to 74, and the films 71 to 74 are patterned using the resist film as a mask to form electrode pads 81 and fuses 82.

Next, steps required until a sectional structure shown in FIG. FIG. 1E is an enlarged cross-sectional view of the electrode pad 81 and the fuse 82 of FIG. 1D and a region in the vicinity thereof.
A first insulating film 85 is formed so as to cover the entire surface of the fourth interlayer insulating film 61, the electrode pad 81 and the fuse 82. As the first insulating film 85, an oxide film, for example, a SiO ₂ film is formed by a plasma CVD method or the like. The first insulating film 85 is formed to be thicker than the electrode pad 81 and the fuse 82, for example, 1.5 μm. Since the first insulating film 85 is also formed on the electrode pad 81 and the fuse 82, the height of the first insulating film 85 in the region where the electrode pad 81 and the fuse 82 are present is higher than in other regions. It is high. Therefore, as shown in FIG. 1F, the first insulating film 85 is etched back using, for example, plasma, or polished by a CMP method to flatten the surface. As a result, the first insulating film 85 is a little thicker than the electrode pad 81 and the fuse 82 and has a flat surface.

Next, steps required until a sectional structure shown in FIG.
On the first insulating film 85, as the second insulating film 86, for example, an SiO ₂ film that is an oxide film is formed to 600 nm by a plasma CVD method or the like. Further, a nitride film 87 is formed as a passivation film on the second insulating film 86 to a thickness of 300 nm by, for example, a plasma CVD method. Further, a resist film 88 is formed on the entire surface of the nitride film 87. Since the resist film 88 is formed by applying a resist on the flat nitride film 87, the film height is lower than the conventional one. That is, the thickness of the films 85 to 87 disposed on the electrode pad 81 is thinner than the thickness of the films 85 to 87 on the fourth interlayer insulating film 61 around the other region, for example, the fuse 82. Further, unlike the conventional example shown in FIG. 3B, since there is no deep groove 207 between the electrode pad 202 and the fuse 203, a region where the resist is accumulated is not formed.

  Subsequently, the resist film 88 is patterned to form openings 89A and 89B. The opening 89A is formed above the electrode pad 81. The opening 89B is formed above the fuse 82.

Next, steps required until a sectional structure shown in FIG.
Using the patterned resist film 88 as a mask, the nitride film 87, the second insulating film 86, and the first insulating film 85 are etched in order so that the first opening 90A and the second opening 90B are simultaneously formed. Form. The first opening 90A is formed below the opening 89A of the resist film 88 and exposes the electrode pad 81. The second opening 90B is formed below the opening 89B of the resist film 88, and exposes the fuse 82. The etching here is performed under conditions such that the insulating films 85 and 86 are over-etched in order to completely expose the electrode pad 81. Therefore, around the fuse 82, the first insulating film 85 is etched deeper than the upper surface of the fuse 82, and a groove 92 is formed. However, the depth of the groove 92 of the first insulating film 85 is shallower than the film thickness of the first insulating film 85. That is, the height of the upper surface 85A of the first insulating film 85 on the side of the fuse 82 forming the bottom of the second opening 90B is higher than the bottom surface 82A of the fuse 82.

  Thereafter, the resist film 88 remaining on the nitride film 87 is removed by ashing or the like. Since there is no deep groove between the electrode pad 81 and the fuse 82 as in the prior art, the resist film 88 does not remain around the fuse 82. As a result, as shown in FIG. 1I, the semiconductor device 100 having the electrode pad 81 and the fuse 82 in the uppermost layer and the other region covered with the oxide film and the nitride film is formed. Here, the electrode pad 81 is exposed to the outside through the first opening 90A. The fuse 82 is exposed to the outside through the second opening 90B.

  As described above, in the method of manufacturing the semiconductor device 100, the surfaces of the insulating films 86 and 86 are flattened in the process of simultaneously forming the electrode pad 81 formed in the uppermost layer and the openings 90A and 90B of the fuse 82. As a result, the film thickness of the insulating film above the interlayer insulating film 61 on the side of the fuse 82 was made larger than the film thickness of the insulating film above the electrode pad 81. That is, the film thickness of the insulating films 85 and 86 and the nitride film 87 on the electrode pad 81 is smaller than the film thickness of the insulating films 85 and 86 and the nitride film 87 in a region where no circuit is formed. Thus, the depths of the insulating films 85 and 86 and the nitride film 87 to be removed by etching become shallower than other regions. As a result, even if the insulating films 85 and 86 and the nitride film 87 are etched so that the electrode pad 81 is completely exposed, the insulating films 85 and 86 around the fuse 82 are not dug. More specifically, according to this manufacturing method, the semiconductor device 100 in which the upper surface 85A of the first insulating film 85 is higher than the bottom surface 82A of the fuse 82 is manufactured. This makes it difficult for the resist film to remain on the upper surface 85A of the first insulating film 85, which is the bottom of the second opening 90B. Further, in the method for manufacturing the semiconductor device 100, as illustrated in FIG. 3D, the resist film 210 is not applied after the groove 207 is formed on the side of the fuse 203. This also contributes to preventing the resist film from remaining around the fuse 82. For these reasons, the surface contamination of the semiconductor device 100 due to the residual resist film can be prevented.

(Second Embodiment)
The second embodiment will be described in detail with reference to the drawings. The same components as those in the first embodiment are denoted by the same reference numerals. Moreover, the description which overlaps with 1st Embodiment is abbreviate | omitted.
First, steps required until a sectional structure shown in FIG. The steps until the electrode pad 81 and the fuse 82 are formed are the same as those in the first embodiment described with reference to FIGS. 1A to 1D. First, the first insulating film 101 is formed so as to cover the entire surface of the electrode pad 81 and the fuse 82. As the first insulating film 101, an SiO ₂ film is formed to a thickness of 700 μm, for example, using an oxide film, a plasma CVD method or the like. On the first insulating film 101, a first nitride film 102 is formed as a first passivation film to a thickness of 500 nm by using, for example, a plasma CVD method. Subsequently, a resist film 103 is formed on the entire surface of the first nitride film 102, and the resist film 103 is patterned. As a result, a resist pattern having an opening 103A only above the electrode pad 81 is formed.

Next, steps required until a sectional structure shown in FIG.
Using the patterned resist film 103 as a mask, the first nitride film 102 and the first insulating film 101 are etched in order to form an opening 105 on the electrode pad 81. The opening 105 exposes the electrode pad 81.

Next, steps required until a sectional structure shown in FIG.
An oxide film, for example, a SiO ₂ film is formed as the second insulating film 106 on the first nitride film 102 having the opening 105. The second insulating film 106 is formed to a thickness of 600 nm, for example, by a plasma CVD method or the like. The second insulating film 106 is also formed on the electrode pad 81 exposed from the opening 105. Subsequently, a second nitride film 107 is formed as a second passivation film on the second insulating film 106 by using a plasma CVD method or the like. The second nitride film 107 is formed, for example, to be thinner than the first nitride film 102, for example, to a thickness of 300 nm. At this time, the thicknesses of the films 106 and 107 disposed on the electrode pad 81 are set such that the thickness of the films 106 and 107 disposed above other regions, for example, the first insulating film 101 or the fourth interlayer insulating film 61 around the fuse 82 is increased. It becomes thinner than the thickness of 102,106,107.

Further, steps required until a sectional structure shown in FIG.
A resist film 110 is formed on the entire surface of the second nitride film 107, and the resist film 110 is patterned. As a result, resist patterns having openings 110A and 110B are formed above the electrode pad 81 and the fuse 82, respectively. Then, using the patterned resist film 110 as a mask, the second nitride film 107 and the second insulating film 106 are sequentially etched to form the first opening 111A and the second opening 111B at the same time. Etching is performed while the steps of the second nitride film 107 and the second insulating film 106 are divided and the selection ratio with the base is maintained. At this time, since the first nitride film 102 functions as an etching stopper, the uniformity of the in-plane film thickness can be ensured. In addition, since the first nitride film 102 serves as an etching stopper, the lower first insulating film 101 is not etched. Therefore, the upper surface 101A of the first insulating film 101 in the second opening 111B is disposed above the bottom surface 82A of the fuse 82. Similarly, the upper surface 102A of the first nitride film 102 corresponding to the bottom of the second opening 111B is disposed above the bottom surface 82A of the fuse 82.

  As a result, as shown in FIG. 2E, the semiconductor device 120 having the electrode pad 81 and the fuse 82 in the uppermost layer and the other region covered with the laminated structure of the insulating films 101 and 106 and the nitride films 102 and 107 is formed. Is done. Here, the electrode pad 81 is exposed to the outside through the opening 111A. The fuse 82 is exposed to the outside through the opening 111 </ b> B while being covered with the first insulating film 101 and the first nitride film 102. Since the periphery of the fuse 82 is not over-etched, a deep groove is not formed in the side portion of the fuse as in the prior art. Further, by stacking the insulating films 101 and 106 and the nitride films 102 and 107, the waterproofness and moistureproofness of the circuit structure below the semiconductor device 10 are improved.

  As described above, in the method of manufacturing the semiconductor device 120, in the process of simultaneously forming the electrode pad 81 formed in the uppermost layer and the openings 90A and 90B of the fuse 82, the first insulating film on the electrode pad 81 is formed. 101 and the first nitride film 102 were removed. As a result, the film thickness of the insulating film above the interlayer insulating film 61 on the side of the fuse 82 becomes thicker than the film thickness of the insulating film above the electrode pad 81, and the second insulating film to be removed by etching on the electrode pad 81. The depths of 106 and the second nitride film 107 are smaller than those in other regions. As a result, even if the second insulating film 106 and the second nitride film 107 are etched so that the electrode pad 81 is completely exposed, the first insulating film 101 and the first nitride film 102 around the fuse 82 are used. Will not be dug too much. This becomes more prominent by forming the first nitride film 102 to be thicker than the thickness of the second nitride film 107 to be etched, so that the first nitride film 102 functions as a stopper. As a result, the semiconductor device 120 in which the upper surface 101A of the first insulating film 101 and the upper surface 102A of the first nitride film 102 are higher than the bottom surface 82A of the fuse 82 is manufactured. This makes it difficult for the resist film to remain on the bottom (the upper surface 101A or the upper surface 102A) of the second opening 111B. Further, in the method for manufacturing the semiconductor device 120, as illustrated in FIG. 3D, the resist film 210 is not applied after the groove 207 is formed on the side of the fuse 203. This also contributes to preventing the resist film from remaining around the fuse 82. For these reasons, the surface contamination of the semiconductor device 120 due to the residual resist film can be prevented.

  All examples and conditional expressions given here are intended to help the reader understand the inventions and concepts that have contributed to the promotion of technology, and such examples and It is to be construed without being limited to the conditions, and the organization of such examples in the specification is not related to showing the superiority or inferiority of the present invention. While embodiments of the present invention have been described in detail, various changes, substitutions and variations can be made thereto without departing from the spirit and scope of the present invention.

The features of the above embodiment will be added below.
(Appendix 1) An electrode pad and a fuse are formed on the uppermost interlayer insulating film in the multilayer wiring structure formed above the substrate, and the fuse side is located above the interlayer insulating film, the electrode pad and the fuse. A first opening that exposes the electrode pad by etching the insulating film and forming an insulating film having a thickness above the interlayer insulating film at a thickness greater than that above the electrode pad; and above the fuse A method for manufacturing a semiconductor device, comprising the step of simultaneously forming a second opening from which at least a part of the insulating film is removed.
(Additional remark 2) The said opening process does not expose the said interlayer insulation film in a said 2nd opening part, The manufacturing method of the semiconductor device of Additional remark 1 characterized by the above-mentioned.
(Appendix 3)
The step of forming the insulating film includes the step of forming the insulating film in which the film thickness of the side portion of the fuse above the interlayer insulating film is larger than the film thickness of the electrode pad, and etching or polishing the surface of the insulating film The method for manufacturing a semiconductor device according to appendix 1 or appendix 2, wherein the opening step exposes the fuse in a second opening.
(Supplementary Note 4) The insulating film includes a first insulating film, a first passivation film, a second insulating film, and a second passivation film, and the step of forming the insulating film includes the interlayer insulating film and Forming the first insulating film covering the electrode pad and the fuse, forming the first passivation film on the first insulating film, the first passivation film and the first Etching the insulating film to expose the electrode pad, forming the second insulating film so as to cover the exposed electrode pad and the first passivation film, and the second insulating film Forming the second passivation film on the film, wherein the opening step etches the second passivation film and the second insulating film to form the electrode passivation. The semiconductor device according to appendix 1 or appendix 2, wherein the first opening that exposes the gate and the second opening that exposes the first passivation film above the fuse are formed simultaneously. Device manufacturing method.
(Supplementary note 5) The method for manufacturing a semiconductor device according to supplementary note 4, wherein the second passivation film is formed to be thinner than the first passivation film.
(Appendix 6) An electrode pad and a fuse are formed on the uppermost interlayer insulating film in the multilayer wiring structure formed above the substrate, and the insulating film covering the interlayer insulating film, the electrode pad, and the fuse is formed as the electrode pad. And the surface of the insulating film is flattened by etching or polishing, a passivation film is formed above the flattened insulating film, and the passivation film and the insulating film are etched. A method of manufacturing a semiconductor device, comprising simultaneously forming a first opening for exposing the electrode pad and a second opening for exposing the fuse.
(Supplementary Note 7) An electrode pad and a fuse are formed on the uppermost interlayer insulating film in the multilayer wiring structure formed above the substrate, and the first insulating film covering the interlayer insulating film, the electrode pad, and the fuse is formed. Forming a first passivation film on the first insulating film, etching the first passivation film and the first insulating film to expose the electrode pad, and exposing the electrode A second insulating film is formed to cover the pad and the first passivation film, a second passivation film is formed on the second insulating film, and the second passivation film and the second insulating film are formed. The film is etched to simultaneously form a first opening for exposing the electrode pad and a second opening for exposing the first passivation film above the fuse. A method for manufacturing a semiconductor device.
(Supplementary Note 8) A substrate, electrode pads and fuses disposed on the uppermost interlayer insulating film in the multilayer wiring structure formed above the substrate, and an insulating film formed above the interlayer insulating film; A first opening formed in the insulating film and exposing the electrode pad; and a second opening formed in the insulating film and having a bottom height higher than a bottom surface of the fuse. A featured semiconductor device.
(Supplementary Note 9) The insulating film includes a first insulating film disposed on the interlayer insulating film, a first passivation film formed on the first insulating film, and on the first passivation film. A second insulating film formed on the second insulating film, and a second passivation film formed on the second insulating film, wherein the first opening and the second opening are the second opening 9. The semiconductor device according to appendix 8, wherein the semiconductor device is formed by removing the insulating film and the second passivation film.

1 substrate 61 interlayer insulating film 81 electrode pad 82 fuse 82A bottom surface 85, 101 first insulating film 85A, 101A, 102A top surface (bottom surface)
87 Nitride film (passivation film)
88,110 Resist film (mask)
90A, 111A First opening 90B, 111B Second opening 100, 120 Semiconductor device 102 First nitride film (first passivation film)
103 Mask 106 Second insulating film 107 Second nitride film (second passivation film)

Claims (5)

Forming electrode pads and fuses on the uppermost interlayer insulating film in the multilayer wiring structure formed above the substrate;
Forming an insulating film above the interlayer insulating film, the electrode pad and the fuse, the film thickness of the side portion of the fuse above the interlayer insulating film being larger than the film thickness above the electrode pad;
A semiconductor including an opening step in which the insulating film is etched to simultaneously form a first opening exposing the electrode pad and a second opening from which at least a part of the insulating film above the fuse is removed. Device manufacturing method.   The manufacturing method of a semiconductor device according to appendix 1, wherein the opening step does not expose the interlayer insulating film in the second opening. The step of forming the insulating film includes
Forming the insulating film whose film thickness above the interlayer insulating film on the side of the fuse is larger than the film thickness of the electrode pad;
Flattening the surface of the insulating film by etching or polishing;
Including
The manufacturing method of the semiconductor device according to appendix 1 or appendix 2, wherein the opening step exposes the fuse in a second opening. The insulating film includes a first insulating film, a first passivation film, a second insulating film, and a second passivation film,
The step of forming the insulating film includes
Forming the first insulating film covering the interlayer insulating film, the electrode pad, and the fuse;
Forming the first passivation film on the first insulating film;
Etching the first passivation film and the first insulating film to expose the electrode pads;
Forming the second insulating film so as to cover the exposed electrode pad and the first passivation film;
Forming the second passivation film on the second insulating film;
Including
The opening step etches the second passivation film and the second insulating film to expose the first opening for exposing the electrode pad and the first passivation film above the fuse. The method for manufacturing a semiconductor device according to appendix 1 or appendix 2, wherein the second opening is formed simultaneously. A substrate,
Electrode pads and fuses disposed on the uppermost interlayer insulating film in the multilayer wiring structure formed above the substrate;
An insulating film formed above the interlayer insulating film;

A first opening formed in the insulating film and exposing the electrode pad;
A second opening formed in the insulating film and having a bottom height higher than a bottom surface of the fuse;
A semiconductor device comprising:

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