JP2015228473A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a through electrode capable of enhancing the reliability while easing limitations in layout.SOLUTION: The semiconductor device includes: a semiconductor substrate; an element separation region formed in an upper part of one major plane of the semiconductor substrate; an interlayer insulation film formed on the one major plane of the semiconductor substrate; a first contact plug that penetrates the interlayer insulation film and reaches the inside of the element separation region; and a through electrode penetrating the semiconductor substrate. The first contact plug and the through electrode are connected to each other inside or on the bottom of the element separation region.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a through electrode and a manufacturing method thereof.

  With the recent enhancement of functionality and performance of electronic devices, various developments have been promoted to improve the performance and integration of semiconductor devices used, and as part of this, the development of 3D packaging technology with through electrodes has been developed. Is being actively conducted. Among them, a through electrode penetrating a semiconductor substrate is frequently used in place of conventional wire bonding mainly due to a demand for package miniaturization.

  A cross-sectional view of a conventional semiconductor device having a through electrode is shown in FIG. 2 (see, for example, Patent Document 1).

  In this semiconductor device, an element such as a transistor and a wiring layer are formed on one main surface of a semiconductor substrate 101. Here, the gate electrode 102 is formed in a region surrounded by the element isolation region 103, and the contact plug 105 is connected to a predetermined region of the semiconductor substrate 101 through the contact plug etching stop film 104. The contact plug 105 is formed in the interlayer insulating film 107 so as to be connected to the lowermost wiring layer 106. An insulating film 108 is formed so as to cover the wiring layer 106. Although not shown, a gate insulating film is formed below the gate electrode, and a plurality of upper wiring layers and a plurality of insulating film layers including the insulating film 108 are formed above the lowermost wiring layer 106. A pad electrode is disposed on the uppermost wiring layer 106, and a protective film is formed so as to open the pad electrode.

  A through hole 112 reaching the desired lowermost wiring layer 106 on which the passivation film 111 is formed is formed on the back surface side of the semiconductor substrate 101. Further, an insulating film 113 made of a silicon oxide film is formed so as to cover the inner wall surface of the through hole 112, a barrier metal layer 114 and a Cu seed layer 115 are formed, and a through electrode 116 and a rewiring layer 117 are formed. Yes. A protective layer 118 is formed on the back side of the semiconductor substrate 101, and solder terminals 119 are formed.

  In such a conventional technique, when the through electrode 116 is formed, the through hole 112 is formed up to the surface of the semiconductor substrate 101 on which the element is formed, and the through electrode 116 itself applies stress to the periphery, thereby penetrating. In the region occupied by the electrode 116 and its peripheral region, a region where elements and wiring cannot be formed occurs. Further, since the through electrode having a large opening diameter of about 100 μm is received by the thin wiring layer 106 of about 100 nm, damage to the wiring layer is large, and the Cu film is excessively shaved or resputtered Cu diffuses in terms of reliability. There is a problem.

  In order to deal with the above problems, for example, an invention described in Patent Document 2 is known for a conventional semiconductor device having a through electrode and a method for forming the same. In Patent Document 2, a proposal is made that the through electrode is configured to connect two types of through electrodes including a small diameter plug and a large diameter plug. Here, a small-diameter plug that reaches the middle of the semiconductor substrate from the front surface side of the semiconductor substrate is formed, while a large-diameter plug is formed from the back surface side of the semiconductor substrate at a position corresponding to the small-diameter plug and connected to the small-diameter plug. In this way, a through electrode is formed.

JP 2006-128352 A JP 2005-294577 A

  However, the etching of the Si substrate of the large-diameter plug has a large etching rate of about 10 μm / min, and it is difficult to control the bottom surface of the large-diameter plug at a fixed position by etching that is normally performed for a fixed time. Therefore, the large-diameter plug becomes shallow or penetrates the Si substrate due to variations in the in-plane thickness of the Si substrate, rate variations, and the like.

  Therefore, in the manufacturing method disclosed in Patent Document 2 shown above, due to variations in the amount of silicon etching, the small diameter plug and the large diameter plug are not connected due to insufficient etching, or the large diameter plug reaches the element formation surface due to excessive etching. Such problems occur. Here, when the large-diameter plug reaches the interlayer insulating film (or immediately before), which is the element formation surface, the influence of the stress due to the back electrode on the element becomes large, causing a problem that the characteristics of the transistor fluctuate.

  In addition, from the viewpoint of productivity, an additional step of forming a small-diameter plug that requires a large number of man-hours in the manufacturing process is required, and productivity is greatly reduced.

  In view of the above-described problems in the prior art, the present invention reduces the influence on the element formation surface due to the through electrode, relaxes the layout restriction, and has high productivity, high controllability, and high reliability. An object of the present invention is to provide a semiconductor device including a through electrode and a method for manufacturing the semiconductor device.

  In order to solve the above-described problems, a semiconductor device of the present invention includes a semiconductor substrate, an element isolation region formed on an upper portion of one main surface of the semiconductor substrate, and an interlayer insulating film formed on the one main surface. A first contact plug that penetrates the interlayer insulating film and reaches the element isolation region, and a back electrode provided from the back surface side opposite to the one main surface to the one main surface side in the semiconductor substrate. The first contact plug and the back electrode are connected in the element isolation region to form a through electrode.

  In the semiconductor device of the present invention, the element formation region formed on the upper side of the one main surface of the semiconductor substrate and the element formation region on the one main surface between the interlayer insulating film and the element formation region. An etching stopper film formed on the semiconductor substrate, and a second contact plug that penetrates the interlayer insulating film and the etching stopper film and reaches an element formation region of the semiconductor substrate. The interlayer insulating film and the element on the semiconductor substrate It is preferable that an etching stop film is not formed between the separation regions.

  In the semiconductor device of the present invention, it is preferable that there are a plurality of first contact plugs, and each of the plurality of first contact plugs is connected to one back electrode.

  In the semiconductor device of the present invention, it is preferable that the bottom portion of the first contact plug protrudes into the back electrode and is connected.

  In the semiconductor device of the present invention, the first contact plug and the second contact plug are preferably made of the same conductive material.

  In the semiconductor device of the present invention, the conductive material is preferably mainly composed of tungsten or copper.

  In the semiconductor device of the present invention, the opening diameter of the first contact plug is preferably equal to or larger than the opening diameter of the second contact plug.

  In the semiconductor device of the present invention, it is preferable that the first contact plug and the second contact plug have a hole shape or a groove shape.

  In addition, the method for manufacturing a semiconductor device of the present invention includes a step (a) of forming an element isolation region and an element formation region on one main surface of a semiconductor substrate, and an etching stop film on the element isolation region and the element formation region. Forming a step (b), removing the etching stop film on the element isolation region (c), after the step (c), forming an interlayer insulating film on the semiconductor substrate (d), A step (e) of forming a first contact hole penetrating the insulating film and reaching the element isolation region, and a second contact hole penetrating the interlayer insulating film and reaching the contact etching stop film; A step (f) of penetrating the etching stopper film exposed on the bottom surface of the second contact hole to reach the second contact hole to the element formation region, and a conductive material in the first contact hole and the second contact hole. Embedded, After the step (g) of forming the first contact plug and the second contact plug, and after the step (g), an opening reaching the element isolation region from the back side of the semiconductor substrate is formed, and the opening A step (i) of exposing the first contact plug on the bottom surface of the portion, and a step (j) of forming a back electrode by embedding a conductive material in the opening and connecting the back electrode and the first contact plug. I have.

  Further, in the method for manufacturing a semiconductor device of the present invention, in step (e), it is preferable that the opening diameter of the first contact hole is formed to be equal to or larger than the opening diameter of the second contact hole.

  In the method for manufacturing a semiconductor device of the present invention, the etching stop film is preferably made of a silicon nitride film.

  In the method for manufacturing a semiconductor device of the present invention, both the element isolation region and the interlayer insulating film are preferably made of a silicon oxide film.

  In the method for manufacturing a semiconductor device of the present invention, it is preferable that the first contact plug and the second contact plug are made of a conductive material containing tungsten or copper as a main component.

  Further, in the method for manufacturing a semiconductor device of the present invention, a step (h) of thinning the semiconductor substrate by removing a back surface opposite to one main surface of the semiconductor substrate between the steps (g) and (i). ).

  According to the semiconductor device and the method for manufacturing the same of the present invention, the contact plug formed from the front surface side of the semiconductor substrate and the through electrode formed from the back surface side of the semiconductor substrate are formed in the region near the surface of the semiconductor substrate. By connecting in the isolation region or at the bottom of the isolation region, the effect on the element formation surface due to the through electrode is reduced, layout restrictions are relaxed, and productivity and controllability are highly reliable. A semiconductor device including an electrode and a method for manufacturing the semiconductor device can be provided.

It is process sectional drawing which shows the semiconductor device which concerns on embodiment of this invention, and its manufacturing method. It is process sectional drawing which shows the semiconductor device which concerns on embodiment of this invention, and its manufacturing method. It is process sectional drawing which shows the semiconductor device which concerns on embodiment of this invention, and its manufacturing method. It is process sectional drawing which shows the semiconductor device which concerns on embodiment of this invention, and its manufacturing method. It is process sectional drawing which shows the semiconductor device which concerns on embodiment of this invention, and its manufacturing method. It is process sectional drawing which shows the semiconductor device which concerns on embodiment of this invention, and its manufacturing method. It is process sectional drawing which shows the semiconductor device which concerns on embodiment of this invention, and its manufacturing method. It is process sectional drawing which shows the semiconductor device which concerns on embodiment of this invention, and its manufacturing method. It is process sectional drawing which shows the semiconductor device which concerns on embodiment of this invention, and its manufacturing method. It is process sectional drawing which shows the semiconductor device which concerns on embodiment of this invention, and its manufacturing method. It is sectional drawing of the semiconductor device which has the conventional penetration electrode.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  1a to 1j are process cross-sectional views illustrating a semiconductor device and a manufacturing method thereof according to the present embodiment.

  First, as shown in FIG. 1A, an etching stop film 14 for a contact hole for forming a gate electrode 12, an element isolation region 13, and a contact plug is formed on one main surface of a semiconductor substrate 11. Although not shown, a gate insulating film is formed under the gate electrode, and a diffusion layer constituting, for example, a source / drain is formed above the semiconductor substrate 11 on both sides of the gate electrode 12. . Here, the element isolation region 13 is made of, for example, a silicon oxide film, and is formed to surround the gate electrode 12 and the diffusion layer at a depth of 300 nm. The etching stop film 14 is formed of, for example, a silicon nitride film with a thickness of 30 nm.

  Next, as shown in FIG. 1b, the etching stop film 14 in the region where the through electrode is formed is removed using the lithography technique and the etching technique, while the etching stop film 14 is formed in the area where an element such as a transistor is formed. Try to leave. Thereafter, an interlayer insulating film 15 is formed on the semiconductor substrate 11. Here, the interlayer insulating film 15 is a silicon oxide film, for example, and may be formed to a thickness of 400 nm, for example.

  Next, as shown in FIG. 1c, a contact hole in which a first contact plug 16a and a second contact plug 16b are to be formed later is patterned in the interlayer insulating film 15 by using a lithography technique and a dry etching technique. Form. For example, tungsten is buried in these contact holes to form a first contact plug 16a and a second contact plug 16b. Here, the first contact plug 16a is a contact plug formed in the back electrode formation region, and the second contact plug 16b is a contact plug formed in the element formation region. Note that the back electrode forming region exists inside the element isolation region 13 in plan view.

Etching of the contact hole in the interlayer insulating film 15 uses, for example, a mixed gas of C ₅ F ₈ , oxygen, and argon, and a silicon oxide film that is the interlayer insulating film 15 is applied to the silicon nitride film that is the etching stop film 14. Selectively etch. For example, the selection ratio of the silicon oxide film etching rate to the silicon nitride film etching rate may be set to 30.

  Here, the etching amount of the interlayer insulating film 15 is usually over-etched in consideration of variations in film thickness and variations in etching rate. In the present embodiment, for example, 50% overetching is performed with respect to the thickness of the interlayer insulating film 15 in which the etching amount is set to be larger than that corresponding to the variation. That is, the total etching amount of the interlayer insulating film 15 is 600 nm as a film thickness. Therefore, the contact hole, which is the opening for the second contact plug 16b in the region for forming an element such as a transistor, is temporarily stopped on the etching stop film 14, and the remaining film amount of the etching stop film 14 is, for example, 10 nm. On the other hand, the contact hole, which is the opening for the first contact plug 16a in the back electrode formation region, does not have the etching stop film 14, and the interlayer insulating film 15 and the element isolation region 13 are both silicon oxide films. Etching reaches the depth of, for example, 200 nm inside the element isolation region 13 without stopping in the middle. However, since the element isolation region 13 is formed to a depth of 300 nm, a contact hole that is an opening for the first contact plug 16a does not penetrate the element isolation region 13.

  Next, as shown in FIG. 1d, the entire surface is etched back by dry etching to reach the bottom surface of the contact hole, which is the opening for the second contact plug 16b, to the semiconductor substrate 11, and then, for example, Ti and TiN After forming a barrier metal made of tungsten and a metal film made of tungsten on the inside of the contact hole and on the surface of the interlayer insulating film 15, the metal film on the surface of the interlayer insulating film 15 is removed using CMP technology, One contact plug 16a and a second contact plug 16b are formed.

  Next, the lowermost wiring layer 17 and the insulating film 18 on the wiring layer 17, and further, although not shown, an insulating film including a plurality of upper wiring layers and the insulating film 18 above the lowermost wiring layer 17. A pad electrode connected to the uppermost wiring layer and a protective film are sequentially formed.

  Next, as shown in FIG. 1e, after the support substrate 19 is bonded to the front surface side of the semiconductor substrate 11 using an adhesive 20, a predetermined thickness, for example, 200 μm, is formed from the back surface side of the semiconductor substrate 11 by a grinder or the like. The semiconductor substrate 11 is thinned by polishing. Note that. The support substrate 19 and the adhesive 20 are not shown in the drawings after FIG.

Next, as shown in FIG. 1f, after forming a passivation film 21 made of, for example, a silicon nitride film on the back side of the semiconductor substrate 11, an opening 22 reaching the bottom of the element isolation region 13 by lithography and dry etching techniques. Are formed with an opening diameter of 100 μm in diameter, for example. At this time, dry etching is performed by first opening the passivation film 21 with a mixed gas of, for example, CHF ₃ , Ar, and oxygen, and then selectively etching the silicon substrate with respect to the silicon oxide film, for example, C ₄ F ₈ gas. The semiconductor substrate 11 is etched from the back side by using a Bosch process in which protective film deposition by etching and etching by SF ₆ gas are alternately performed. Thus, the opening reaches the bottom surface of the element isolation region 13 made of a silicon oxide film.

  Etching conditions for silicon as a substrate may be, for example, a selection ratio of silicon etching rate to silicon oxide film etching rate of about 200. Considering thickness variation TTV (Total Thickness Variation) of the semiconductor substrate 11, for example, equivalent to 2 μm Even when overetching is performed, the amount of silicon oxide film scraped at the bottom surface of the element isolation region 13 is almost 10 nm, and the etching can be stopped at the bottom surface of the element isolation region 13 with high accuracy.

  Next, as shown in FIG. 1g, the etching conditions are switched, and the silicon oxide film is etched from the bottom surface of the element isolation region 13 to reach the bottom surface of the first contact plug 16a.

Here, the etching condition of the silicon oxide film is, for example, a mixed gas of C ₅ F ₈ , oxygen, and argon, and the etching rate is several tens of nm / min, which is sufficiently low compared with the high etching rate of several μm / min during silicon etching. Since it can be set, the connection between the bottom surface of the opening 22 and the bottom surface of the second contact plug 16b can be processed with high accuracy.

  Next, as shown in FIG. 1h, an insulating film 23 made of a silicon oxide film is formed on the back side of the semiconductor substrate 11 to cover the inner wall surface of the opening 22, and the opening 22 is etched back by dry etching. The insulating film 23 formed on the bottom surface is removed.

  Next, as shown in FIG. 1i, a barrier metal layer 24 and a seed layer 25 of Cu as a filling material are formed inside the opening 22 by sputtering, and then the back electrode and the rewiring region are exposed by lithography. After resist patterning (not shown), a through electrode 26 made of Cu and a rewiring layer 27 are formed using a plating technique. Thereafter, the barrier metal layer 24 and the seed layer 25 remaining in the region where the plating is not formed are removed by wet etching. Finally, the Cu seed layer 25, the through electrode 26 made of Cu, and the rewiring layer 27 are integrated into a Cu layer.

  Next, as shown in FIG. 1j, a protective layer 28 is formed on the back surface side of the semiconductor substrate 11, and after patterning so as to have an opening in a region where the solder terminal 29 is formed by lithography, a support substrate (not shown) 19 is peeled off. Thereafter, solder terminals 29 are formed in the openings of the protective layer 28 to complete the semiconductor device of this embodiment.

  In the present embodiment, for example, overetching of 50% with respect to the thickness of the interlayer insulating film 15 is performed, and the first contact plug 16a reaching a depth of, for example, 200 nm is formed inside the element isolation region 13. The depth of the first contact plug 16a can be set by adjusting the amount of overetching of the interlayer insulating film 15 from the bottom of the element isolation region 13 to a desired depth inside.

  Therefore, if the condition setting is optimized, the first contact plug 16 a is formed so as to reach the bottom surface of the element isolation region 13, and the bottom surface of the through electrode 26 just reaches the bottom surface of the element isolation region 13. It is also possible to form.

  Further, the first contact plug 16a and the through electrode 26 may be connected inside or on the bottom surface of the element isolation region 13. For example, the first contact plug 16a protrudes from the bottom surface of the through electrode 26 into the through electrode. It does not matter.

  According to this embodiment, the contact plug formed from the front surface side of the semiconductor substrate and the through electrode formed from the back surface side of the semiconductor substrate are within the element isolation region or the element isolation region formed in the region near the surface of the semiconductor substrate. By connecting at the bottom surface, the stress on the semiconductor substrate caused by the through electrode can be relieved, and the characteristic variation of the transistor adjacent to the through electrode can be suppressed. Further, since the contact plug connected to the through electrode is formed at the same time as the contact plug of the transistor portion, it is possible to provide a manufacturing method that does not impair productivity.

  The semiconductor device and the manufacturing method thereof according to the present invention reduce the influence on the element formation surface caused by the through electrode, relax the layout restriction, and provide a highly reliable semiconductor device with high productivity and controllability and the manufacturing thereof. The present invention can provide a method, and is particularly useful in a three-dimensional stacked semiconductor device having a through electrode that requires high integration, high performance, improved yield, and the like, and a method for manufacturing the same.

DESCRIPTION OF SYMBOLS 11 Semiconductor substrate 12 Gate electrode 13 Element isolation region 14 Etching stop film 15 Interlayer insulating film 16a 1st contact plug 16b 2nd contact plug 17 Wiring layer 18, 23 Insulating film 19 Support substrate 20 Adhesive 21 Passivation film 22 Opening part 24 Barrier metal layer 25 Seed layer 26 Through electrode 27 Redistribution layer 28 Protective layer 29 Solder terminal 101 Semiconductor substrate 102 Gate electrode 103 Element isolation region 104 Etching stop film 105 Contact plug 106 Wiring layer 107 Interlayer insulating film 108, 113 Insulating film 109 Support substrate 110 Adhesive 111 Passivation film 112 Through hole 114 Barrier metal layer 115 Seed layer 116 Through electrode 117 Rewiring layer 118 Protective layer 119 Solder terminal

Claims (14)

A semiconductor substrate;
An element isolation region formed in an upper portion on one main surface side of the semiconductor substrate;
An interlayer insulating film formed on the one main surface;
A first contact plug that penetrates the interlayer insulating film and reaches the element isolation region;
In the semiconductor substrate, comprising a back electrode provided toward the one main surface side from the back surface side opposite to the one main surface,
The first contact plug and the back electrode are connected in the element isolation region to form a through electrode. An element formation region formed in an upper part on one main surface side of the semiconductor substrate;
An etching stop film formed between the interlayer insulating film and the element formation region on the element formation region on the one main surface;
A second contact plug that penetrates the interlayer insulating film and the etching stopper film and reaches an element formation region of the semiconductor substrate,
The semiconductor device according to claim 1, wherein the etching stop film is not formed between the interlayer insulating film and the element isolation region on the semiconductor substrate. There are a plurality of the first contact plugs,
The semiconductor device according to claim 1, wherein each of the plurality of first contact plugs is connected to the back electrode.   The semiconductor device according to claim 1, wherein a bottom portion of the first contact plug protrudes and is connected to the inside of the back electrode.   The semiconductor device according to claim 1, wherein the first contact plug and the second contact plug are made of the same conductive material.   6. The semiconductor device according to claim 5, wherein the conductive material contains tungsten or copper as a main component.   The semiconductor device according to claim 1, wherein an opening diameter of the first contact plug is equal to or larger than an opening diameter of the second contact plug.   The semiconductor device according to claim 1, wherein the first contact plug and the second contact plug have a hole shape or a groove shape. A step (a) of forming an element isolation region and an element formation region on an upper portion of one main surface of a semiconductor substrate;
A step (b) of forming an etching stop film on the element isolation region and on the element formation region;
Removing the etching stopper film on the element isolation region (c);
After the step (c), a step (d) of forming an interlayer insulating film on the semiconductor substrate;
Forming a first contact hole penetrating the interlayer insulating film and reaching the element isolation region; and a second contact hole penetrating the interlayer insulating film and reaching the etching stop film (e )When,
Passing through the etching stopper film exposed on the bottom surface of the second contact hole, and allowing the second contact hole to reach the element formation region;
A step (g) of embedding a conductive material in the first contact hole and the second contact hole to form a first contact plug and a second contact plug, respectively;
After the step (g), forming an opening reaching the element isolation region from the back surface side of the semiconductor substrate, and exposing the first contact plug on the bottom surface of the opening;
A method of manufacturing a semiconductor device, comprising: forming a back electrode by embedding a conductive material in the opening and connecting the back electrode and the first contact plug (j).   The method of manufacturing a semiconductor device according to claim 9, wherein in the step (e), an opening diameter of the first contact hole is formed to be equal to or larger than an opening diameter of the second contact hole.   The method of manufacturing a semiconductor device according to claim 9, wherein the etching stop film is made of a silicon nitride film.   The method for manufacturing a semiconductor device according to claim 9, wherein both the element isolation region and the interlayer insulating film are made of a silicon oxide film.   The method of manufacturing a semiconductor device according to claim 9, wherein the first contact plug and the second contact plug are made of a conductive material mainly composed of tungsten or copper.   Between the step (g) and the step (i), there is a step (h) in which the back surface opposite to one main surface of the semiconductor substrate is scraped to thin the semiconductor substrate. A method for manufacturing a semiconductor device according to claim 9.

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