JPH08125030A - Semicondutor device having input protective circuit and its manufacture - Google Patents

Abstract

PURPOSE: To uniformize the crystalline property of a part where a PN junction of a protecting semiconductor element is formed, to prevent the local breakdown of the PN junction by a crystal defect, and to evade the lowering of an electrostatic breakdown resisting property as a protective element by making the region for the formation of the PN junction amorphous. CONSTITUTION: The titile semiconductor device has semiconductor circuits 14a and 14b composed of semiconductor elements to be operated according to input signals, and input protective circuits 12 and 13 having a semiconductor element 13 for protecting the semiconductor circuits 14a and 14b. The protecting semiconductor element 13 has a PN junction, and at least the PN junction is amorphous. Accordingly, it becomes possible to prevent the local breakdown of the PN junction caused by a crystal defect, and evade the lowering of the electrostatic breakdown resistance as a protective element, since any crystal defects do not exist practically in the amorphous part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an input protection circuit.

[0002]

2. Description of the Related Art Generally, in a semiconductor integrated circuit device,
In order to prevent the internal elements from being destroyed by excessive static electricity from the outside, an input protection circuit consisting of a semiconductor element for electrostatic breakdown protection is placed between the internal circuit such as a semiconductor integrated circuit and the external connection terminal. The diode characteristics of the PN junction formed in the electrostatic breakdown resistant semiconductor element are used to prevent an excessive current from being applied to the internal element.

On the other hand, a MOSFET formed on an SOI (Silicon On Insulator) type substrate is capable of high speed and low power consumption operation of a semiconductor integrated circuit because of its parasitic capacitance being reduced. As an input protection circuit in the semiconductor integrated circuit device having the SOI structure, Japanese Patent Application Laid-Open No. 26045/1990.
In Japanese Patent Publication No. 9, there is proposed one including an input resistor 12 and an N-channel MOSFET 13 as a protection transistor as shown in FIG.

In the structure shown in FIG. 2, a protection transistor 13 is arranged between the input pad 11 and the ground terminal 16 via a protection resistor 12, and when a negative overvoltage is applied to the input pad 11, When the protection transistor 13 is turned on and a current flows, the overvoltage is dissipated and the internal circuits (14a, 14b) are protected. On the other hand, when the positive overvoltage is applied, the current flows due to the avalanche breakdown of the PN junction in the protection transistor 13 to dissipate the overvoltage.

[0005]

However, in the protection transistor for electrostatic breakdown having a PN junction of this kind, especially SIMOX (Separation-by-IM plant ratio) is used.
In a case where a protection transistor is formed on an (n-of-OXygen) -SOI substrate, the PN junction may be locally destroyed due to many crystal defects in the single crystal semiconductor layer in which the PN junction is formed. In many cases, there is a problem that sufficient electrostatic breakdown resistance cannot be obtained.

The present invention has been made in view of the above problems, and amorphizes a portion of a protective semiconductor element where a PN junction is formed to make the crystallinity of the region uniform and substantially eliminates crystal defects. P due to crystal defects
It is an object of the present invention to prevent local destruction of the N-junction and prevent a decrease in electrostatic breakdown resistance as a protective element.

[0007]

In order to achieve the above-mentioned object, in the invention described in claim 1, a semiconductor circuit (14a, 1a comprising semiconductor elements which operate in response to an input signal is used.
4b) and a protection semiconductor element (13, 17) for protecting the semiconductor circuit (14a, 14b) when the input signal is in an overvoltage state.
3, 17), the protective semiconductor element (13, 17) is configured to have a PN junction, and at least a portion where the PN junction is formed is amorphous. It is characterized by being.

According to a second aspect of the present invention, a plurality of island-shaped semiconductor layers formed on the semiconductor substrate (1) with the insulating layer (2a) interposed therebetween and the periphery being separated by the insulator (2b). (3a, 3b), a semiconductor circuit (14a, 14b) including a semiconductor element formed in a predetermined semiconductor layer (3a) of the plurality of semiconductor layers, and another predetermined one of the plurality of semiconductor layers. A protection semiconductor element (13, 17) which is formed on the semiconductor layer (3b) and protects the semiconductor circuit (14a, 14b) when the input signal to the semiconductor circuit (14a, 14b) is in an overvoltage state. In the semiconductor device including the input protection circuit (12, 13, 17), the protection semiconductor element (13, 17) has a PN junction, and at least the PN junction is formed. The Moiety is characterized in that amorphous.

The protective semiconductor elements (13, 1)
7) is MOSFET or P in the embodiment described later.
It is composed of N diodes. In the invention according to claim 3, a plurality of island-shaped semiconductor layers (3a) are formed on the semiconductor substrate (1) with the insulating layer (2a) interposed therebetween and the periphery of which is separated by the insulator (2b). And the semiconductor circuits (14a, 1) on the plurality of island-shaped semiconductor layers (3a).
4b) and the semiconductor element and the semiconductor circuit (1
4a, 14b) input protection circuit (12,
In the method for manufacturing a semiconductor device having an input protection circuit, the method including the step of forming the protective semiconductor element (13) constituting the protective element (13) with a MOS transistor, the semiconductor layer of the protective semiconductor element (13). It is characterized by having a step of making (3a) amorphous.

According to a fourth aspect of the invention, in the invention of the third aspect, the step of forming the protective semiconductor element (13) includes forming the gate (5) and then removing the gate (5). A step of forming a source / drain as a mask, wherein the step of making the semiconductor layer (3a) amorphous is performed before forming the source / drain by using the gate (5) as a mask, It is characterized by the step of making the semiconductor layer (3a) of the protective semiconductor element (13) amorphous.

The reference numerals in parentheses of the above-mentioned means indicate the correspondence with the concrete means described in the embodiments described later.

[0012]

According to the invention described in claims 1 to 4, the portion in which the PN junction is formed in the protective semiconductor element is made amorphous. Therefore, since the crystal defects are substantially absent in the amorphous portion, it is possible to prevent the local destruction of the PN junction due to the crystal defects and prevent the deterioration of the electrostatic breakdown resistance as the protection element.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a main sectional view of a semiconductor integrated circuit device (shown in FIG. 2) constructed according to the first embodiment. Note that, in FIG. 1, the cross-sectional structure of the input pad (bonding pad) 11, the protective resistor 12, and the like of FIG. 2 is omitted.

The internal circuit of the semiconductor integrated circuit device includes an N-channel MOSFET (hereinafter referred to as NMOS).
An inverter composed of 14b and a P-channel MOSFET (hereinafter referred to as PMOS) 14a is used. The power supply terminal 15 is connected to the source electrode of the PMOS 14a, and the ground terminal 16 is connected to the source electrode of the NMOS 14b.
Is connected. This inverter has an input pad 11
It operates according to the input signal input from.

An input protection circuit is arranged between the input terminal of the inverter and the input pad 11 which is an external connection terminal. The input protection circuit includes a protection resistor 12 and a protection NMOS 13.
It consists of and. That is, the protective resistor 12 is provided in the middle of the connecting line connecting the input pad 11 and the input terminal of the inverter.
Is provided, and a protective N is provided between the connecting wire and the ground terminal 16.
The MOS 13 is arranged. The gate terminal of the protection NMOS 13 is connected to the ground terminal 16.

The semiconductor layer 3b on which the source / drain of the protection NMOS 13 is formed is a PMOS which constitutes an inverter.
Unlike the semiconductor layer 3a in which the source / drain of the NMOS transistor 14a and the NMOS 14b are formed, the semiconductor layer 3a is made of an amorphous material. That is, in the protection NMOS 13, P in the semiconductor layer 3b where the source / drain is formed
The portion where the N junction is formed is amorphous.

An example of a method of manufacturing the semiconductor integrated circuit device configured as described above will be described with reference to FIG. First, as shown in FIG. 3A, S in which the single crystal semiconductor layer 3a is formed on the semiconductor substrate 1 with the insulating layer 2a interposed therebetween.
The IMOX-SOI type substrate is set to L by the normal LOCOS method.
The OCOS oxide film 2b is formed to separate the single crystal semiconductor layer 3a of the SIMOX-SOI type substrate into islands, thereby limiting the active region.

Next, as shown in FIGS. 3 (B) and 3 (C),
A gate oxide film 4 is formed, a photoresist 8 is used, and M
A P-type impurity (boron) is added to the single crystal semiconductor layer 3a in the NMOS formation region to control the threshold voltage of the OSFET.
N-type impurities are sequentially implanted into the PMOS formation region.
Then, as shown in FIG. 3D, the gate electrode 5 is formed of polycrystalline silicon to which impurities are added, and the gate electrode 5 is protected by a silicon oxide film as shown in FIG. The regions other than the NMOS formation region are protected by a photoresist 8, and, for example, silicon is ion-implanted to break the silicon bond of the single crystal semiconductor layer in the protection NMOS formation region to make the amorphous state 3b.

Subsequently, as shown in FIGS. 3F and 3G, arsenic and boron are implanted into the NMOS formation region and the PMOS formation region to form source / drain diffusion layers. After that, the interlayer insulating film 6 and the Al wiring 7 are formed to configure the semiconductor integrated circuit device shown in FIG. Although the input protection circuit is arranged between the input pad 11 and the ground terminal 16 in the above-mentioned embodiment, as shown in FIG.
An input protection circuit may be arranged between the power supply terminal 15 and the power supply terminal 15. Further, as shown in FIG. 5, the input pad 11 and the ground terminal 1
An input protection circuit may be arranged between each of 6 and the power supply terminal 15.

Further, the input protection circuit can be configured in various combinations of protection resistance, protection NMOS and protection PMOS. (Second Embodiment) This second embodiment, as shown in FIG.
The input protection circuit is composed of a protection resistor 12 and a protection diode 17. The protection diode 17 used here is a gated diode formed of a semiconductor layer similarly to the protection NMOS 13 described in the first embodiment.

A protection resistor 12 is arranged in the middle of a connection line connecting the input pad 11 and the input terminal of the inverter, and a protection diode 17 is arranged between the connection line and the ground terminal 16. The gate terminal of the protection diode 17 is connected to the ground terminal. The portion of the semiconductor layer 3b where the protection diode 17 is formed where the PN junction is formed is in an amorphous state as shown in FIG.

Therefore, as in the first embodiment, since the semiconductor layer 3b in which the PN junction is formed is amorphous, crystal defects are substantially absent, and local destruction of the PN junction due to crystal defects is suppressed. be able to. In the second embodiment,
Although the input protection circuit is arranged between the input pad 11 and the ground terminal 16, the input protection circuit may be arranged between the input pad 11 and the power supply terminal 15 as in the first embodiment. Further, regarding the configuration of the input protection circuit, various combinations of protection resistors, protection diodes, protection NMOSs and protection PMOSs are possible.

Although the present invention is applied to the SIMOX-SOI structure in the various embodiments described above, the present invention is also applied to a semiconductor device having an SOI structure by bonding substrates or a bulk structure. The invention can be applied.

[Brief description of drawings]

FIG. 1 is a sectional view showing a sectional structure of a semiconductor integrated circuit device having an input protection circuit according to a first embodiment of the present invention.

FIG. 2 is an electrical connection diagram showing an electrical configuration of a semiconductor integrated circuit device having an input protection circuit.

FIG. 3 is a process drawing showing a manufacturing method for obtaining the structure shown in FIG.

FIG. 4 is an electrical connection diagram showing another electrical connection of the input protection circuit.

FIG. 5 is an electrical connection diagram showing still another electrical connection of the input protection circuit.

FIG. 6 is an electrical connection diagram showing an electrical configuration of a semiconductor integrated circuit device having an input protection circuit showing a second embodiment of the present invention.

7 is a cross-sectional view showing a cross-sectional structure of the semiconductor integrated circuit device shown in FIG.

[Explanation of symbols]

1 ... Semiconductor substrate, 2a ... Insulating layer, 2b ... LOCO
S oxide film, 4 ... Gate oxide film, 5 ... Gate, 11 ...
… Input pad, 12 …… Protection resistance, 13 …… Protection NMO
S, 14a ... PMOS, 14b ... NMOS, 17 ...
... PN diode.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 21/822 27/08 331 E 29/78 29/786 H01L 29/78 301 K 9056-4M 623 Z

Claims (4)

[Claims] 1. A semiconductor comprising a semiconductor circuit including a semiconductor element that operates in response to an input signal, and an input protection circuit having a protection semiconductor element that protects the semiconductor circuit when the input signal is in an overvoltage state. In the device, the protection semiconductor element is configured to have a PN junction, and at least a portion where the PN junction is formed is amorphous, and a semiconductor device having an input protection circuit. . 2. A plurality of island-shaped semiconductor layers formed on a semiconductor substrate with an insulating layer interposed therebetween and having a periphery separated by an insulator, and a predetermined semiconductor layer among the plurality of semiconductor layers. A semiconductor circuit including a semiconductor element, and a protective semiconductor formed on another predetermined semiconductor layer of the plurality of semiconductor layers and protecting the semiconductor circuit when an input signal to the semiconductor circuit is in an overvoltage state In a semiconductor device including an input protection circuit having an element, the protection semiconductor element has a PN junction, and at least a portion where the PN junction is formed is amorphous. A semiconductor device having an input protection circuit. 3. A step of forming a plurality of island-shaped semiconductor layers on a semiconductor substrate with an insulating layer interposed therebetween and the periphery of which is separated by an insulator, and a semiconductor circuit is formed on the plurality of island-shaped semiconductor layers. And a semiconductor element for protection which constitutes an input protection circuit for protecting the input of the semiconductor circuit, respectively.
A method of manufacturing a semiconductor device having an input protection circuit, comprising the step of forming a transistor, wherein the semiconductor layer of the protection semiconductor element is made amorphous. Manufacturing method of semiconductor device. 4. The step of forming the protective semiconductor element includes the step of forming a source / drain by using the gate as a mask after forming the gate, and making the semiconductor layer amorphous. A step of forming the source / drain using the gate as a mask,
The method of manufacturing a semiconductor device having an input protection circuit according to claim 3, wherein the step of making the semiconductor layer of the protective semiconductor element amorphous.