JP2015532488A5 - - Google Patents

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Publication number
JP2015532488A5
JP2015532488A5 JP2015535792A JP2015535792A JP2015532488A5 JP 2015532488 A5 JP2015532488 A5 JP 2015532488A5 JP 2015535792 A JP2015535792 A JP 2015535792A JP 2015535792 A JP2015535792 A JP 2015535792A JP 2015532488 A5 JP2015532488 A5 JP 2015532488A5
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JP
Japan
Prior art keywords
memory card
tuning
host device
command
exceeds
Prior art date
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Pending
Application number
JP2015535792A
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English (en)
Japanese (ja)
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JP2015532488A (ja
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Publication date
Priority claimed from US13/672,693 external-priority patent/US8972818B2/en
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Publication of JP2015532488A publication Critical patent/JP2015532488A/ja
Publication of JP2015532488A5 publication Critical patent/JP2015532488A5/ja
Pending legal-status Critical Current

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JP2015535792A 2012-10-05 2013-10-03 外部メモリチューニングシーケンスの最適使用のためのアルゴリズム Pending JP2015532488A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201261710639P 2012-10-05 2012-10-05
US61/710,639 2012-10-05
US13/672,693 US8972818B2 (en) 2012-10-05 2012-11-08 Algorithm for optimal usage of external memory tuning sequence
US13/672,693 2012-11-08
PCT/US2013/063319 WO2014055794A1 (en) 2012-10-05 2013-10-03 Algorithm for optimal usage of external memory tuning sequence

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2018089246A Division JP2018125040A (ja) 2012-10-05 2018-05-07 外部メモリチューニングシーケンスの最適使用のためのアルゴリズム

Publications (2)

Publication Number Publication Date
JP2015532488A JP2015532488A (ja) 2015-11-09
JP2015532488A5 true JP2015532488A5 (enExample) 2016-11-10

Family

ID=50433743

Family Applications (2)

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JP2015535792A Pending JP2015532488A (ja) 2012-10-05 2013-10-03 外部メモリチューニングシーケンスの最適使用のためのアルゴリズム
JP2018089246A Pending JP2018125040A (ja) 2012-10-05 2018-05-07 外部メモリチューニングシーケンスの最適使用のためのアルゴリズム

Family Applications After (1)

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JP2018089246A Pending JP2018125040A (ja) 2012-10-05 2018-05-07 外部メモリチューニングシーケンスの最適使用のためのアルゴリズム

Country Status (6)

Country Link
US (1) US8972818B2 (enExample)
EP (1) EP2904502A1 (enExample)
JP (2) JP2015532488A (enExample)
KR (1) KR20150067214A (enExample)
CN (1) CN104704477B (enExample)
WO (1) WO2014055794A1 (enExample)

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US12032848B2 (en) 2021-06-21 2024-07-09 Pure Storage, Inc. Intelligent block allocation in a heterogeneous storage system
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US12001684B2 (en) 2019-12-12 2024-06-04 Pure Storage, Inc. Optimizing dynamic power loss protection adjustment in a storage system
US11507297B2 (en) 2020-04-15 2022-11-22 Pure Storage, Inc. Efficient management of optimal read levels for flash storage systems
US11416338B2 (en) 2020-04-24 2022-08-16 Pure Storage, Inc. Resiliency scheme to enhance storage performance
US11474986B2 (en) 2020-04-24 2022-10-18 Pure Storage, Inc. Utilizing machine learning to streamline telemetry processing of storage media
US11768763B2 (en) 2020-07-08 2023-09-26 Pure Storage, Inc. Flash secure erase
US11513974B2 (en) 2020-09-08 2022-11-29 Pure Storage, Inc. Using nonce to control erasure of data blocks of a multi-controller storage system
US11681448B2 (en) 2020-09-08 2023-06-20 Pure Storage, Inc. Multiple device IDs in a multi-fabric module storage system
US12153818B2 (en) 2020-09-24 2024-11-26 Pure Storage, Inc. Bucket versioning snapshots
US12387133B2 (en) * 2020-10-29 2025-08-12 Qualcomm Incorporated Reinforcement learning based scheme for tuning memory interfaces
US11487455B2 (en) 2020-12-17 2022-11-01 Pure Storage, Inc. Dynamic block allocation to optimize storage system performance
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US12099742B2 (en) 2021-03-15 2024-09-24 Pure Storage, Inc. Utilizing programming page size granularity to optimize data segment storage in a storage system
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US8972818B2 (en) * 2012-10-05 2015-03-03 Qualcomm Incorporated Algorithm for optimal usage of external memory tuning sequence

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