JP2015501046A5 - - Google Patents

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Publication number
JP2015501046A5
JP2015501046A5 JP2014544989A JP2014544989A JP2015501046A5 JP 2015501046 A5 JP2015501046 A5 JP 2015501046A5 JP 2014544989 A JP2014544989 A JP 2014544989A JP 2014544989 A JP2014544989 A JP 2014544989A JP 2015501046 A5 JP2015501046 A5 JP 2015501046A5
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JP
Japan
Prior art keywords
processor
reset
storage element
information
history
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
JP2014544989A
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English (en)
Japanese (ja)
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JP2015501046A (ja
JP5788611B2 (ja
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Priority claimed from US13/309,623 external-priority patent/US8880860B2/en
Application filed filed Critical
Publication of JP2015501046A publication Critical patent/JP2015501046A/ja
Publication of JP2015501046A5 publication Critical patent/JP2015501046A5/ja
Application granted granted Critical
Publication of JP5788611B2 publication Critical patent/JP5788611B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2014544989A 2011-12-02 2012-12-03 リセット後の評価のためにリセットより前の状態を保存するための方法および装置 Expired - Fee Related JP5788611B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/309,623 2011-12-02
US13/309,623 US8880860B2 (en) 2011-12-02 2011-12-02 Methods and apparatus for saving conditions prior to a reset for post reset evaluation
PCT/US2012/067652 WO2013082625A1 (en) 2011-12-02 2012-12-03 Method and apparatus for saving processor information prior to a reset for post reset evaluation

Publications (3)

Publication Number Publication Date
JP2015501046A JP2015501046A (ja) 2015-01-08
JP2015501046A5 true JP2015501046A5 (enExample) 2015-02-26
JP5788611B2 JP5788611B2 (ja) 2015-10-07

Family

ID=47470158

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014544989A Expired - Fee Related JP5788611B2 (ja) 2011-12-02 2012-12-03 リセット後の評価のためにリセットより前の状態を保存するための方法および装置

Country Status (6)

Country Link
US (1) US8880860B2 (enExample)
EP (1) EP2776930A1 (enExample)
JP (1) JP5788611B2 (enExample)
CN (1) CN103975310A (enExample)
IN (1) IN2014CN03839A (enExample)
WO (1) WO2013082625A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014010739A (ja) * 2012-07-02 2014-01-20 Fujitsu Ltd システムの状態の復元についての情報処理方法、情報処理プログラム及び情報処理装置
US10848483B2 (en) * 2016-12-08 2020-11-24 Ricoh Company, Ltd. Shared terminal, communication system, and display control method, and recording medium
US11474698B2 (en) * 2019-12-04 2022-10-18 Micron Technology, Inc. Reset verification in a memory system by using a mode register
US12009966B2 (en) * 2020-08-13 2024-06-11 Arris Enterprises Llc Modem reset package with self-healing
US20240320078A1 (en) * 2021-07-13 2024-09-26 SiFive, Inc. Processor Crash Analysis Using Register Sampling
CN117453439A (zh) * 2022-07-19 2024-01-26 华为技术有限公司 处理器、获取信息的方法、单板及网络设备
US12164348B2 (en) * 2022-10-04 2024-12-10 Nxp Usa, Inc. Capturing of on-chip resets in an integrated circuit

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0665941U (ja) * 1993-02-22 1994-09-16 株式会社三協精機製作所 プログラム動作装置
GB2281986B (en) 1993-09-15 1997-08-06 Advanced Risc Mach Ltd Data processing reset
AUPM348794A0 (en) * 1994-01-20 1994-02-17 Alcatel Australia Limited Microprocessor fault log
JPH09114707A (ja) * 1995-10-13 1997-05-02 Mitsubishi Electric Corp マイクロプロセッサ及びデバッグ情報記憶方法
JP3202700B2 (ja) * 1998-10-20 2001-08-27 松下電器産業株式会社 信号処理装置
JP3376306B2 (ja) * 1998-12-25 2003-02-10 エヌイーシーマイクロシステム株式会社 データ処理装置、そのデータ処理方法
US6968469B1 (en) 2000-06-16 2005-11-22 Transmeta Corporation System and method for preserving internal processor context when the processor is powered down and restoring the internal processor context when processor is restored
US6775609B2 (en) * 2001-09-27 2004-08-10 Denso Corporation Electronic control unit for vehicle having operation monitoring function and fail-safe function
KR100505638B1 (ko) 2002-08-28 2005-08-03 삼성전자주식회사 워킹 콘텍스트 저장 및 복구 장치 및 방법
US7698544B2 (en) 2005-05-13 2010-04-13 Texas Instruments Incorporated Automatic halting of a processor in debug mode due to reset
US7574591B2 (en) 2006-01-12 2009-08-11 Microsoft Corporation Capturing and restoring application state after unexpected application shutdown
CN100517244C (zh) * 2006-02-21 2009-07-22 中兴通讯股份有限公司 一种对异常复位进行系统保护的方法及装置
US7725769B1 (en) * 2006-06-07 2010-05-25 Zilog, Inc. Latent VBO reset circuit
US7971104B2 (en) 2006-10-24 2011-06-28 Shlomi Dolev Apparatus and methods for stabilization of processors, operating systems and other hardware and/or software configurations
GB2455744B (en) 2007-12-19 2012-03-14 Advanced Risc Mach Ltd Hardware driven processor state storage prior to entering a low power mode
TWI369608B (en) * 2008-02-15 2012-08-01 Mstar Semiconductor Inc Multi-microprocessor system and control method therefor
US8825912B2 (en) 2008-11-12 2014-09-02 Microchip Technology Incorporated Dynamic state configuration restore
DE102009000874A1 (de) 2009-02-16 2010-08-19 Robert Bosch Gmbh Verfahren zur Verbesserung der Analysierbarkeit von Softwarefehlern in einem Mikrocontroller
JP2011076295A (ja) * 2009-09-30 2011-04-14 Hitachi Ltd 組込系コントローラ
JP4911372B2 (ja) * 2009-10-06 2012-04-04 日本電気株式会社 Ｃｐｕ再リセットを伴うｃｐｕ再初期化時におけるタイムアウト防止方法、その装置及びそのプログラム
JP5533097B2 (ja) * 2010-03-18 2014-06-25 株式会社リコー 情報処理装置、画像形成装置及び情報処理プログラム

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