JP2015185076A5 - - Google Patents

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Publication number
JP2015185076A5
JP2015185076A5 JP2014063125A JP2014063125A JP2015185076A5 JP 2015185076 A5 JP2015185076 A5 JP 2015185076A5 JP 2014063125 A JP2014063125 A JP 2014063125A JP 2014063125 A JP2014063125 A JP 2014063125A JP 2015185076 A5 JP2015185076 A5 JP 2015185076A5
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JP
Japan
Prior art keywords
data
slot
output
unit
bit
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JP2014063125A
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English (en)
Japanese (ja)
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JP2015185076A (ja
JP6378515B2 (ja
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Priority to JP2014063125A priority Critical patent/JP6378515B2/ja
Priority claimed from JP2014063125A external-priority patent/JP6378515B2/ja
Priority to CN201510010671.0A priority patent/CN104951280B/zh
Priority to US14/660,057 priority patent/US9798547B2/en
Publication of JP2015185076A publication Critical patent/JP2015185076A/ja
Publication of JP2015185076A5 publication Critical patent/JP2015185076A5/ja
Application granted granted Critical
Publication of JP6378515B2 publication Critical patent/JP6378515B2/ja
Expired - Fee Related legal-status Critical Current
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JP2014063125A 2014-03-26 2014-03-26 Ｖｌｉｗプロセッサ Expired - Fee Related JP6378515B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2014063125A JP6378515B2 (ja) 2014-03-26 2014-03-26 Ｖｌｉｗプロセッサ
CN201510010671.0A CN104951280B (zh) 2014-03-26 2015-01-09 Vliw处理器
US14/660,057 US9798547B2 (en) 2014-03-26 2015-03-17 VLIW processor including a state register for inter-slot data transfer and extended bits operations

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014063125A JP6378515B2 (ja) 2014-03-26 2014-03-26 Ｖｌｉｗプロセッサ

Publications (3)

Publication Number Publication Date
JP2015185076A JP2015185076A (ja) 2015-10-22
JP2015185076A5 true JP2015185076A5 (enExample) 2017-03-30
JP6378515B2 JP6378515B2 (ja) 2018-08-22

Family

ID=54165955

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014063125A Expired - Fee Related JP6378515B2 (ja) 2014-03-26 2014-03-26 Ｖｌｉｗプロセッサ

Country Status (3)

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US (1) US9798547B2 (enExample)
JP (1) JP6378515B2 (enExample)
CN (1) CN104951280B (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7159696B2 (ja) * 2018-08-28 2022-10-25 富士通株式会社 情報処理装置，並列計算機システムおよび制御方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4238833A (en) * 1979-03-28 1980-12-09 Monolithic Memories, Inc. High-speed digital bus-organized multiplier/divider system
JP2806171B2 (ja) * 1992-08-31 1998-09-30 日本電気株式会社 データ演算装置
JP3658072B2 (ja) * 1996-02-07 2005-06-08 株式会社ルネサステクノロジ データ処理装置およびデータ処理方法
JP2003216943A (ja) 2002-01-22 2003-07-31 Toshiba Corp 画像処理装置、この装置に用いられるコンパイラおよび画像処理方法
US20060224652A1 (en) * 2005-04-05 2006-10-05 Nokia Corporation Instruction set processor enhancement for computing a fast fourier transform
JP2006338684A (ja) * 2006-08-01 2006-12-14 Matsushita Electric Ind Co Ltd プロセッサ
US20080071851A1 (en) * 2006-09-20 2008-03-20 Ronen Zohar Instruction and logic for performing a dot-product operation
JP2008310693A (ja) * 2007-06-15 2008-12-25 Panasonic Corp 情報処理装置
KR101645001B1 (ko) * 2009-02-18 2016-08-02 삼성전자주식회사 Ｖｌｉｗ 명령어 생성 장치 및 그 방법과 ｖｌｉｗ 명령어를 처리하는 ｖｌｉｗ 프로세서 및 그 방법
US10095516B2 (en) * 2012-06-29 2018-10-09 Intel Corporation Vector multiplication with accumulation in large register space
US9600235B2 (en) * 2013-09-13 2017-03-21 Nvidia Corporation Technique for performing arbitrary width integer arithmetic operations using fixed width elements

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