JP2017515228A5 - - Google Patents

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Publication number
JP2017515228A5
JP2017515228A5 JP2016563817A JP2016563817A JP2017515228A5 JP 2017515228 A5 JP2017515228 A5 JP 2017515228A5 JP 2016563817 A JP2016563817 A JP 2016563817A JP 2016563817 A JP2016563817 A JP 2016563817A JP 2017515228 A5 JP2017515228 A5 JP 2017515228A5
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JP
Japan
Prior art keywords
threads
simd processor
simd
processor
active
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2016563817A
Other languages
English (en)
Japanese (ja)
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JP2017515228A (ja
Filing date
Publication date
Priority claimed from US14/268,215 external-priority patent/US10133572B2/en
Application filed filed Critical
Publication of JP2017515228A publication Critical patent/JP2017515228A/ja
Publication of JP2017515228A5 publication Critical patent/JP2017515228A5/ja
Pending legal-status Critical Current

Links

JP2016563817A 2014-05-02 2015-04-10 Simd処理システムにおける直列実行のための技法 Pending JP2017515228A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/268,215 2014-05-02
US14/268,215 US10133572B2 (en) 2014-05-02 2014-05-02 Techniques for serialized execution in a SIMD processing system
PCT/US2015/025362 WO2015167777A1 (en) 2014-05-02 2015-04-10 Techniques for serialized execution in a simd processing system

Publications (2)

Publication Number Publication Date
JP2017515228A JP2017515228A (ja) 2017-06-08
JP2017515228A5 true JP2017515228A5 (enExample) 2018-05-10

Family

ID=53039617

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016563817A Pending JP2017515228A (ja) 2014-05-02 2015-04-10 Simd処理システムにおける直列実行のための技法

Country Status (8)

Country Link
US (1) US10133572B2 (enExample)
EP (1) EP3137988B1 (enExample)
JP (1) JP2017515228A (enExample)
KR (1) KR20160148673A (enExample)
CN (1) CN106233248B (enExample)
BR (1) BR112016025511A2 (enExample)
ES (1) ES2834573T3 (enExample)
WO (1) WO2015167777A1 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9898348B2 (en) * 2014-10-22 2018-02-20 International Business Machines Corporation Resource mapping in multi-threaded central processor units
US9921838B2 (en) * 2015-10-02 2018-03-20 Mediatek Inc. System and method for managing static divergence in a SIMD computing architecture
CN107534445B (zh) * 2016-04-19 2020-03-10 华为技术有限公司 用于分割哈希值计算的向量处理
US10091904B2 (en) 2016-07-22 2018-10-02 Intel Corporation Storage sled for data center
US10565017B2 (en) * 2016-09-23 2020-02-18 Samsung Electronics Co., Ltd. Multi-thread processor and controlling method thereof
US10990409B2 (en) * 2017-04-21 2021-04-27 Intel Corporation Control flow mechanism for execution of graphics processor instructions using active channel packing
CN108549583B (zh) * 2018-04-17 2021-05-07 致云科技有限公司 大数据处理方法、装置、服务器及可读存储介质
US12004257B2 (en) * 2018-10-08 2024-06-04 Interdigital Patent Holdings, Inc. Device discovery and connectivity in a cellular network
US12314760B2 (en) * 2021-09-27 2025-05-27 Advanced Micro Devices, Inc. Garbage collecting wavefront

Family Cites Families (19)

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US6947047B1 (en) 2001-09-20 2005-09-20 Nvidia Corporation Method and system for programmable pipelined graphics processing with branching instructions
US7895328B2 (en) 2002-12-13 2011-02-22 International Business Machines Corporation System and method for context-based serialization of messages in a parallel execution environment
WO2005072307A2 (en) 2004-01-22 2005-08-11 University Of Washington Wavescalar architecture having a wave order memory
US7590830B2 (en) * 2004-05-28 2009-09-15 Sun Microsystems, Inc. Method and structure for concurrent branch prediction in a processor
GB2437837A (en) 2005-02-25 2007-11-07 Clearspeed Technology Plc Microprocessor architecture
US7761697B1 (en) * 2005-07-13 2010-07-20 Nvidia Corporation Processing an indirect branch instruction in a SIMD architecture
US7634637B1 (en) 2005-12-16 2009-12-15 Nvidia Corporation Execution of parallel groups of threads with per-instruction serialization
US8176265B2 (en) 2006-10-30 2012-05-08 Nvidia Corporation Shared single-access memory with management of multiple parallel requests
US8312254B2 (en) * 2008-03-24 2012-11-13 Nvidia Corporation Indirect function call instructions in a synchronous parallel thread processor
US8850436B2 (en) 2009-09-28 2014-09-30 Nvidia Corporation Opcode-specified predicatable warp post-synchronization
US8782645B2 (en) * 2011-05-11 2014-07-15 Advanced Micro Devices, Inc. Automatic load balancing for heterogeneous cores
US8683468B2 (en) * 2011-05-16 2014-03-25 Advanced Micro Devices, Inc. Automatic kernel migration for heterogeneous cores
US10152329B2 (en) 2012-02-09 2018-12-11 Nvidia Corporation Pre-scheduled replays of divergent operations
US9256429B2 (en) * 2012-08-08 2016-02-09 Qualcomm Incorporated Selectively activating a resume check operation in a multi-threaded processing system
US9229721B2 (en) * 2012-09-10 2016-01-05 Qualcomm Incorporated Executing subroutines in a multi-threaded processing system
US10013290B2 (en) 2012-09-10 2018-07-03 Nvidia Corporation System and method for synchronizing threads in a divergent region of code
KR101603752B1 (ko) * 2013-01-28 2016-03-28 삼성전자주식회사 멀티 모드 지원 프로세서 및 그 프로세서에서 멀티 모드를 지원하는 방법
KR20150019349A (ko) * 2013-08-13 2015-02-25 삼성전자주식회사 다중 쓰레드 실행 프로세서 및 이의 동작 방법
US9652284B2 (en) * 2013-10-01 2017-05-16 Qualcomm Incorporated GPU divergence barrier

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