JP2017515228A - Ｓｉｍｄ処理システムにおける直列実行のための技法 - Google Patents

Ｓｉｍｄ処理システムにおける直列実行のための技法 Download PDF

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JP2017515228A
JP2017515228A JP2016563817A JP2016563817A JP2017515228A JP 2017515228 A JP2017515228 A JP 2017515228A JP 2016563817 A JP2016563817 A JP 2016563817A JP 2016563817 A JP2016563817 A JP 2016563817A JP 2017515228 A JP2017515228 A JP 2017515228A
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instruction
thread
threads
active
processor
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Japanese (ja)
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JP2017515228A5 (enExample
Inventor
アンドリュー・エヴァン・グルーバー
リン・チェン
ユン・ドゥ
アレクセイ・ヴラディミロヴィチ・ボード
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クアルコム，インコーポレイテッド
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Publication of JP2017515228A publication Critical patent/JP2017515228A/ja
Publication of JP2017515228A5 publication Critical patent/JP2017515228A5/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/3009—Thread control instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3888—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple threads [SIMT] in parallel

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Hardware Redundancy (AREA)
  • Devices For Executing Special Programs (AREA)
JP2016563817A 2014-05-02 2015-04-10 Ｓｉｍｄ処理システムにおける直列実行のための技法 Pending JP2017515228A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/268,215 2014-05-02
US14/268,215 US10133572B2 (en) 2014-05-02 2014-05-02 Techniques for serialized execution in a SIMD processing system
PCT/US2015/025362 WO2015167777A1 (en) 2014-05-02 2015-04-10 Techniques for serialized execution in a simd processing system

Publications (2)

Publication Number Publication Date
JP2017515228A true JP2017515228A (ja) 2017-06-08
JP2017515228A5 JP2017515228A5 (enExample) 2018-05-10

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JP2016563817A Pending JP2017515228A (ja) 2014-05-02 2015-04-10 Ｓｉｍｄ処理システムにおける直列実行のための技法

Country Status (8)

Country Link
US (1) US10133572B2 (enExample)
EP (1) EP3137988B1 (enExample)
JP (1) JP2017515228A (enExample)
KR (1) KR20160148673A (enExample)
CN (1) CN106233248B (enExample)
BR (1) BR112016025511A2 (enExample)
ES (1) ES2834573T3 (enExample)
WO (1) WO2015167777A1 (enExample)

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US9898348B2 (en) * 2014-10-22 2018-02-20 International Business Machines Corporation Resource mapping in multi-threaded central processor units
US9921838B2 (en) * 2015-10-02 2018-03-20 Mediatek Inc. System and method for managing static divergence in a SIMD computing architecture
CN107534445B (zh) * 2016-04-19 2020-03-10 华为技术有限公司 用于分割哈希值计算的向量处理
US10091904B2 (en) 2016-07-22 2018-10-02 Intel Corporation Storage sled for data center
US10565017B2 (en) * 2016-09-23 2020-02-18 Samsung Electronics Co., Ltd. Multi-thread processor and controlling method thereof
US10990409B2 (en) * 2017-04-21 2021-04-27 Intel Corporation Control flow mechanism for execution of graphics processor instructions using active channel packing
CN108549583B (zh) * 2018-04-17 2021-05-07 致云科技有限公司 大数据处理方法、装置、服务器及可读存储介质
US12004257B2 (en) * 2018-10-08 2024-06-04 Interdigital Patent Holdings, Inc. Device discovery and connectivity in a cellular network
US12314760B2 (en) * 2021-09-27 2025-05-27 Advanced Micro Devices, Inc. Garbage collecting wavefront

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JP2009230756A (ja) * 2008-03-24 2009-10-08 Nvidia Corp 同期並列スレッドプロセッサにおける間接的な関数呼び出し命令
US7634637B1 (en) * 2005-12-16 2009-12-15 Nvidia Corporation Execution of parallel groups of threads with per-instruction serialization
US20110078690A1 (en) * 2009-09-28 2011-03-31 Brian Fahs Opcode-Specified Predicatable Warp Post-Synchronization
WO2012155010A1 (en) * 2011-05-11 2012-11-15 Advanced Micro Devices, Inc. Automatic load balancing for heterogeneous cores
WO2012158753A1 (en) * 2011-05-16 2012-11-22 Advanced Micro Devices, Inc. Automatic kernel migration for heterogeneous cores
WO2014025480A1 (en) * 2012-08-08 2014-02-13 Qualcomm Incorporated Selectively activating a resume check operation in a multi-threaded processing system
US20140075160A1 (en) * 2012-09-10 2014-03-13 Nvidia Corporation System and method for synchronizing threads in a divergent region of code
WO2014039206A1 (en) * 2012-09-10 2014-03-13 Qualcomm Incorporated Executing subroutines in a multi-threaded processing system
JP2014146335A (ja) * 2013-01-28 2014-08-14 Samsung Electronics Co Ltd マルチモード支援プロセッサ及びマルチモードを支援する処理方法
JP2015036983A (ja) * 2013-08-13 2015-02-23 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． 多重スレッド実行プロセッサ、及びその動作方法
JP2016532180A (ja) * 2013-10-01 2016-10-13 クゥアルコム・インコーポレイテッドＱｕａｌｃｏｍｍ Ｉｎｃｏｒｐｏｒａｔｅｄ Ｇｐｕ発散バリア

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US6947047B1 (en) 2001-09-20 2005-09-20 Nvidia Corporation Method and system for programmable pipelined graphics processing with branching instructions
US7895328B2 (en) 2002-12-13 2011-02-22 International Business Machines Corporation System and method for context-based serialization of messages in a parallel execution environment
WO2005072307A2 (en) 2004-01-22 2005-08-11 University Of Washington Wavescalar architecture having a wave order memory
US7590830B2 (en) * 2004-05-28 2009-09-15 Sun Microsystems, Inc. Method and structure for concurrent branch prediction in a processor
GB2437837A (en) 2005-02-25 2007-11-07 Clearspeed Technology Plc Microprocessor architecture
US7761697B1 (en) * 2005-07-13 2010-07-20 Nvidia Corporation Processing an indirect branch instruction in a SIMD architecture
US8176265B2 (en) 2006-10-30 2012-05-08 Nvidia Corporation Shared single-access memory with management of multiple parallel requests
US10152329B2 (en) 2012-02-09 2018-12-11 Nvidia Corporation Pre-scheduled replays of divergent operations

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7634637B1 (en) * 2005-12-16 2009-12-15 Nvidia Corporation Execution of parallel groups of threads with per-instruction serialization
JP2009230756A (ja) * 2008-03-24 2009-10-08 Nvidia Corp 同期並列スレッドプロセッサにおける間接的な関数呼び出し命令
US20110078690A1 (en) * 2009-09-28 2011-03-31 Brian Fahs Opcode-Specified Predicatable Warp Post-Synchronization
WO2012155010A1 (en) * 2011-05-11 2012-11-15 Advanced Micro Devices, Inc. Automatic load balancing for heterogeneous cores
WO2012158753A1 (en) * 2011-05-16 2012-11-22 Advanced Micro Devices, Inc. Automatic kernel migration for heterogeneous cores
WO2014025480A1 (en) * 2012-08-08 2014-02-13 Qualcomm Incorporated Selectively activating a resume check operation in a multi-threaded processing system
US20140075160A1 (en) * 2012-09-10 2014-03-13 Nvidia Corporation System and method for synchronizing threads in a divergent region of code
WO2014039206A1 (en) * 2012-09-10 2014-03-13 Qualcomm Incorporated Executing subroutines in a multi-threaded processing system
JP2014146335A (ja) * 2013-01-28 2014-08-14 Samsung Electronics Co Ltd マルチモード支援プロセッサ及びマルチモードを支援する処理方法
JP2015036983A (ja) * 2013-08-13 2015-02-23 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． 多重スレッド実行プロセッサ、及びその動作方法
JP2016532180A (ja) * 2013-10-01 2016-10-13 クゥアルコム・インコーポレイテッドＱｕａｌｃｏｍｍ Ｉｎｃｏｒｐｏｒａｔｅｄ Ｇｐｕ発散バリア

Also Published As

Publication number Publication date
US20150317157A1 (en) 2015-11-05
EP3137988A1 (en) 2017-03-08
KR20160148673A (ko) 2016-12-26
US10133572B2 (en) 2018-11-20
CN106233248A (zh) 2016-12-14
ES2834573T3 (es) 2021-06-17
CN106233248B (zh) 2018-11-13
EP3137988B1 (en) 2020-09-02
WO2015167777A1 (en) 2015-11-05
BR112016025511A2 (pt) 2017-08-15

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