JP6378515B2 - Ｖｌｉｗプロセッサ - Google Patents

Ｖｌｉｗプロセッサ Download PDF

Info

Publication number
JP6378515B2
JP6378515B2 JP2014063125A JP2014063125A JP6378515B2 JP 6378515 B2 JP6378515 B2 JP 6378515B2 JP 2014063125 A JP2014063125 A JP 2014063125A JP 2014063125 A JP2014063125 A JP 2014063125A JP 6378515 B2 JP6378515 B2 JP 6378515B2
Authority
JP
Japan
Prior art keywords
data
unit
slot
output
bit data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2014063125A
Other languages
English (en)
Japanese (ja)
Other versions
JP2015185076A5 (enExample
JP2015185076A (ja
Inventor
祥平 野本
祥平 野本
水野　雄介
雄介 水野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MegaChips Corp
Original Assignee
MegaChips Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MegaChips Corp filed Critical MegaChips Corp
Priority to JP2014063125A priority Critical patent/JP6378515B2/ja
Priority to CN201510010671.0A priority patent/CN104951280B/zh
Priority to US14/660,057 priority patent/US9798547B2/en
Publication of JP2015185076A publication Critical patent/JP2015185076A/ja
Publication of JP2015185076A5 publication Critical patent/JP2015185076A5/ja
Application granted granted Critical
Publication of JP6378515B2 publication Critical patent/JP6378515B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/82—Architectures of general purpose stored program computers data or demand driven
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
JP2014063125A 2014-03-26 2014-03-26 Ｖｌｉｗプロセッサ Expired - Fee Related JP6378515B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2014063125A JP6378515B2 (ja) 2014-03-26 2014-03-26 Ｖｌｉｗプロセッサ
CN201510010671.0A CN104951280B (zh) 2014-03-26 2015-01-09 Vliw处理器
US14/660,057 US9798547B2 (en) 2014-03-26 2015-03-17 VLIW processor including a state register for inter-slot data transfer and extended bits operations

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014063125A JP6378515B2 (ja) 2014-03-26 2014-03-26 Ｖｌｉｗプロセッサ

Publications (3)

Publication Number Publication Date
JP2015185076A JP2015185076A (ja) 2015-10-22
JP2015185076A5 JP2015185076A5 (enExample) 2017-03-30
JP6378515B2 true JP6378515B2 (ja) 2018-08-22

Family

ID=54165955

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014063125A Expired - Fee Related JP6378515B2 (ja) 2014-03-26 2014-03-26 Ｖｌｉｗプロセッサ

Country Status (3)

Country Link
US (1) US9798547B2 (enExample)
JP (1) JP6378515B2 (enExample)
CN (1) CN104951280B (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7159696B2 (ja) * 2018-08-28 2022-10-25 富士通株式会社 情報処理装置，並列計算機システムおよび制御方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4238833A (en) * 1979-03-28 1980-12-09 Monolithic Memories, Inc. High-speed digital bus-organized multiplier/divider system
JP2806171B2 (ja) * 1992-08-31 1998-09-30 日本電気株式会社 データ演算装置
JP3658072B2 (ja) * 1996-02-07 2005-06-08 株式会社ルネサステクノロジ データ処理装置およびデータ処理方法
JP2003216943A (ja) 2002-01-22 2003-07-31 Toshiba Corp 画像処理装置、この装置に用いられるコンパイラおよび画像処理方法
US20060224652A1 (en) * 2005-04-05 2006-10-05 Nokia Corporation Instruction set processor enhancement for computing a fast fourier transform
JP2006338684A (ja) * 2006-08-01 2006-12-14 Matsushita Electric Ind Co Ltd プロセッサ
US20080071851A1 (en) * 2006-09-20 2008-03-20 Ronen Zohar Instruction and logic for performing a dot-product operation
JP2008310693A (ja) * 2007-06-15 2008-12-25 Panasonic Corp 情報処理装置
KR101645001B1 (ko) * 2009-02-18 2016-08-02 삼성전자주식회사 Ｖｌｉｗ 명령어 생성 장치 및 그 방법과 ｖｌｉｗ 명령어를 처리하는 ｖｌｉｗ 프로세서 및 그 방법
US10095516B2 (en) * 2012-06-29 2018-10-09 Intel Corporation Vector multiplication with accumulation in large register space
US9600235B2 (en) * 2013-09-13 2017-03-21 Nvidia Corporation Technique for performing arbitrary width integer arithmetic operations using fixed width elements

Also Published As

Publication number Publication date
CN104951280B (zh) 2018-10-12
CN104951280A (zh) 2015-09-30
JP2015185076A (ja) 2015-10-22
US20150277909A1 (en) 2015-10-01
US9798547B2 (en) 2017-10-24

Similar Documents

Publication Publication Date Title
JP5491071B2 (ja) 命令融合演算装置および命令融合演算方法
US11907158B2 (en) Vector processor with vector first and multiple lane configuration
US9965275B2 (en) Element size increasing instruction
JP2008071130A (ja) Ｓｉｍｄ型マイクロプロセッサ
JP2015527642A5 (enExample)
JP4374363B2 (ja) ビットフィールド操作回路
JP5231949B2 (ja) 半導体装置、および、半導体装置によるデータ処理方法
JP6378515B2 (ja) Ｖｌｉｗプロセッサ
JP2018005369A (ja) 演算処理装置及び演算処理装置の制御方法
JP2000322235A (ja) 情報処理装置
JP4444305B2 (ja) 半導体装置
JP6130058B2 (ja) 条件付きのチャネルルーティングおよびインプレースの機能性を持つ再設定可能な命令セルのアレイ
KR100960148B1 (ko) 데이터 프로세싱 회로
JP5786719B2 (ja) ベクトルプロセッサ
CN101253480A (zh) 具有实时动态可变指令集的计算机
JP2014164659A (ja) プロセッサ
JP4901891B2 (ja) 画像処理プロセッサ
JP2007183712A (ja) データ駆動型情報処理装置
JP4896839B2 (ja) マイクロプロセッサおよびデータ処理方法
JP5145659B2 (ja) ベクトルリネーミング方式およびベクトル型計算機
JP2017500812A (ja) 再構成可能命令セルアレイのシリアル構成
JP4703735B2 (ja) コンパイラ、コード生成方法、コード生成プログラム
KR101484600B1 (ko) 카운터 기반 멀티 사이클 프로세서 제어 장치
JP2008102715A (ja) 演算装置
JP2011145886A (ja) 情報処理装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170224

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20170224

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20180315

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20180508

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20180709

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20180717

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20180727

R150 Certificate of patent or registration of utility model

Ref document number: 6378515

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees