JP2015179774A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can achieve refinement of an element while inhibiting deterioration in characteristics.SOLUTION: A semiconductor device manufacturing method of an embodiment comprises: a process of forming an insulation film which is provided on a second conductivity type semiconductor substrate where a plurality of first conductivity type semiconductor regions are provided and which has a first opening on each semiconductor region; a process of forming a metal film on the openings and the insulation film; a process of forming a protection film on the metal film; a process of forming a resist which is provided on the protection film and has a second opening on an upper part of the insulation film; a process of removing the protection film located under the second opening by dry etching; and a process of removing the metal film located under the second opening by dry etching.

Description

  Embodiments described herein relate generally to a method for manufacturing a semiconductor device.

  A semiconductor device for high current and high withstand voltage includes an element region in which current flows in the vertical direction of the semiconductor device, and a termination region surrounding the element region. In the termination region, in order to achieve a high breakdown voltage, a contrivance is made so that the depletion layer easily extends from the element region of the semiconductor device toward the outer peripheral end.

  For example, a guard ring structure in which a plurality of semiconductor regions are formed in the termination region in a direction from the element region of the semiconductor device toward the termination region can be given. In addition, with the miniaturization of the element region of the semiconductor device, the guard ring structure provided in the termination region is also required to be miniaturized.

JP 2008-243943 A

  The problem to be solved by the present invention is to provide a method of manufacturing a semiconductor device that enables miniaturization of elements while suppressing deterioration of characteristics.

  The method of manufacturing a semiconductor device according to the embodiment is provided on a second conductivity type semiconductor substrate having an element region and a termination region surrounding the element region and provided with a plurality of first conductivity type semiconductor regions, Forming an insulating film having a first opening on the semiconductor region; forming a metal film on the opening and the insulating film; forming a protective film on the metal film; and A step of forming a resist provided on the film and having a second opening on the insulating film; a step of removing the protective film located under the second opening by dry etching; and the second Removing the metal film located under the opening by wet etching.

1 is a plan view showing a structure of a semiconductor device 1 according to an embodiment. Sectional drawing which shows the cross section in the A-A 'line shown in FIG. Sectional drawing which shows a cross-section for every manufacturing process of the semiconductor device 1 which concerns on this embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings used in the description in the embodiments are schematic for ease of description, and the shape, size, magnitude relationship, etc. of each element in the drawings are not necessarily shown in the drawings in actual implementation. The present invention is not limited to the above, and can be appropriately changed within a range where the effects of the present invention can be obtained. The first conductivity type will be described as N-type, and the second conductivity type will be described as P-type. However, the opposite conductivity types may be used. As a semiconductor, silicon will be described as an example, but it can also be applied to a compound semiconductor such as silicon carbide (SiC) or gallium nitride (GaN).

  A semiconductor device 1 according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view showing a structure of a semiconductor device 1 according to the present embodiment, and FIG. 2 is a cross-sectional view showing a cross section taken along line A-A ′ shown in FIG. 1. 1 shows a plan view in which the P-type base region 3, the insulating film 5, the source electrode 6, the guard ring electrode 7, and the passivation film 8 are omitted.

  As shown in FIG. 1, the semiconductor device 1 according to the present embodiment includes an element region 31 in which a semiconductor element is formed and a current flows in a stacking direction (vertical direction), and a termination region 30 that surrounds the element region 31 in a horizontal plane. It has an N-type semiconductor substrate 2 (semiconductor substrate). The semiconductor device 1 is rectangular and has four sides and four corners that connect the sides. The semiconductor device 1 according to the present embodiment will be described with a structure in which a MOSFET semiconductor element is formed in the element region 31 as an example. The present invention, including the following embodiments, is not limited to this, and the embodiments of the present invention can also be applied to the case where the element region 31 is formed with a diode or another power semiconductor element such as an IGBT. .

  The semiconductor device 1 according to this embodiment includes an N-type semiconductor substrate 2, a P-type base region 3, a P-type guard ring region 4 (semiconductor region), an insulating film 5, a source electrode 6, a guard ring electrode 7, a passivation film 8, And a drain electrode 12. The N-type semiconductor substrate 2 is, for example, a silicon substrate.

  The N-type semiconductor substrate 2 has a first surface and a second surface opposite to the first surface. The P-type base region 3 is selectively formed on the first surface of the N-type semiconductor substrate 2. Since the present embodiment will be described by taking a MOSFET as an example, a plurality of P-type base regions 3 are formed. A region where the P-type base region 3 is formed on the first surface of the N-type semiconductor substrate 2 becomes an element region 31 in which a current flows in the stacking direction (vertical direction) as will be described later.

  Among the plurality of P-type base regions 3, the boundary between the element region 31 and the termination region 30 exists in the P-type base region 3 closest to the outer peripheral end of the semiconductor device 1. Termination region 30 occupies the outside of element region 31 on the first surface of N-type semiconductor substrate 2. That is, the termination region 30 surrounds the element region 31 in a horizontal plane parallel to the N-type semiconductor substrate 2. As will be described later, in the termination region 30, no operating current flows when the MOSFET is in the on state, and when the MOSFET is in the off state, the termination region 30 is directed from the outer peripheral edge of the P-type base region 3 closest to the outer peripheral edge of the chip toward the outer peripheral edge of the chip. This is the area where the depletion layer spreads.

  The P-type guard ring region 4 is a region between the outer peripheral end of the P-type base region 3 on the most outer peripheral end side and the outer peripheral end of the semiconductor device 1 (that is, the termination region 30) on the first surface of the N-type semiconductor substrate 2. ). The P-type guard ring region 4 is an annular structure that surrounds the entire P-type base region 3. As shown in FIG. 1, the P-type guard ring region 4 has a rectangular annular structure in a plan view, and has four sides and four corners. A side portion of the P-type guard ring region 4 extends along a first surface of the N-type semiconductor substrate 2 linearly along the outer peripheral edge of the semiconductor device 1. The corner portion of the P-type guard ring region 4 has an arcuate structure on the first surface of the N-type semiconductor substrate 2. In the present embodiment, three P-type guard ring regions 4 having such a shape are provided and are separated from each other. When the impurity concentration of the P-type impurity in the P-type guard ring region 4 is higher than the impurity concentration of the P-type impurity in the P-type base region 3, the depletion layer spreads in the direction from the element region 31 to the termination region 30 described later. Can be promoted.

  An insulating film 5 is provided so as to cover the first surface of the N-type semiconductor substrate 2, the P-type base region 3, and the P-type guard ring region 4. The insulating film 5 is an insulator, for example, silicon oxide, but may be another insulator such as silicon nitride or silicon oxynitride.

  A source electrode 6 is provided so as to be electrically connected to the P-type base region 3 through an opening (first opening) of the insulating film 5 provided on the P-type base region 3. Each of the plurality of field plate electrodes 7 is provided in an annular shape along the plurality of P-type guard ring regions 4. Each of the plurality of field plate electrodes 7 is connected to each P-type guard ring region 4 via an opening (first opening) of the insulating film 5 provided on each of the plurality of P-type guard ring regions 4. And electrically connected. Further, each of the plurality of field plate electrodes 7 is separated from each other and insulated. The drain electrode 12 is provided on the second surface of the N-type semiconductor substrate 2 so as to be electrically connected. The source electrode 6, the field plate electrode 7, and the drain electrode 12 are made of metal such as copper or aluminum, for example, but may be made of other metals.

  The passivation film 8 is provided so as to cover the source electrode 6, the field plate electrode 7, and the insulating film 5 from a part of the element region 31 to the entire termination region 30. The passivation film 8 has an opening on the source electrode 6, and the source electrode 6 is drawn to the source terminal outside the chip through this opening (details are not shown). The passivation film 8 is an insulator. For example, silicon oxide is used, but an insulator such as silicon nitride, silicon oxynitride, or polyimide can also be used.

  In the element region 31, a semiconductor element that is a MOSFET is formed. An N-type source layer (not shown) is selectively formed in each of the plurality of P-type base regions 3. A gate electrode is provided on the P-type base region 3 between the N-type source layer and the N-type semiconductor substrate 2 via a gate insulating film (not shown). The MOSFET includes the gate electrode, source electrode 6, drain electrode 12, N-type source layer, P-type base region 3, and N-type semiconductor substrate 2. The gate electrode controls the current flowing between the source electrode 6 and the drain electrode 12.

  In the present embodiment, the case where the semiconductor element formed in the element region 31 is a MOSFET will be described as an example. However, if a semiconductor element in which a current flows between electrodes facing each other, other elements such as a diode or an IGBT are provided in the element region 31. It is also possible to form a semiconductor element.

  When a diode is formed in the element region 31, the P-type base region 3 functions as an anode layer, and a plurality of anode layers are not necessarily formed in the element region 31. The N-type semiconductor substrate 2 functions as a cathode layer. At that time, the source electrode 6 is an anode electrode, and the drain electrode 12 is a cathode electrode.

  When an IGBT is formed in the element region 31, a P-type collector layer is further provided between the nN type semiconductor substrate 2 and the drain electrode 12 when the MOSFET is formed. At that time, the drain electrode 12 is a collector electrode, and the source electrode 6 is an emitter electrode.

  Next, a method for manufacturing the semiconductor device 1 according to the present embodiment will be described with reference to FIGS. 3A to 3E are sectional views showing a sectional structure for each manufacturing process of the semiconductor device 1 according to the present embodiment.

  First, as described above, in the N-type semiconductor substrate 2, the P-type base region 3 is formed in the element region 31, and the P-type guard ring region 4 is formed in the termination region 30 by ion implantation. When forming the P-type semiconductor region, for example, boron (B) is ion-implanted into the N-type semiconductor substrate 2. Although not shown in the present embodiment, an N-type semiconductor layer is epitaxially grown on the N-type semiconductor substrate 2, and ions are implanted into the N-type semiconductor layer to form a P-type base region 3 and a P-type guard ring region 4. May be.

  An insulating film 5 is formed on the N-type semiconductor substrate 2 on which the P-type base region 3 and the P-type guard ring region 4 are formed by a thermal oxidation method, a chemical vapor deposition (CVD) method, or the like. As shown in FIG. 3A, the insulating film 5 has a first opening 20 on the P-type base region 3 and the P-type guard ring region 4 by a reactive ion etching (RIE) method. Etched.

  Next, a metal film 9 is formed on the insulating film 5 by sputtering or the like so as to fill the first opening 20. Then, a silicon nitride film 10 (protective film) is formed on the metal film 9, and a resist 11 is formed on the silicon nitride film 10, and the semiconductor device 1 has a structure shown in FIG. 3B. In this embodiment, the silicon nitride film 10 is used. However, the present invention is not limited to the silicon nitride film in order to obtain the effects described later. The silicon nitride film 10 can be implemented as long as it is less susceptible to wet etching than the metal film 9. The metal film 9 is made of, for example, aluminum (Al) or an aluminum compound.

  As shown in FIG. 3C, a plurality of second openings 21 are formed in the resist 11 by exposure or the like. The second opening 21 is located above the insulating film 5 positioned between the adjacent P-type guard ring regions 4 and between the P-type guard ring region 4 and the P-type base region 3 closest to the element region 31. It is formed on the insulating film 5 to be formed. That is, the second opening 21 is formed between the adjacent first openings 20. The resist 11 located between the P-type guard ring region 4 farthest from the element region 31 and the end of the N-type semiconductor substrate 2 is also removed.

  As shown in FIG. 3D, the portion of the silicon nitride film 10 exposed by the second opening 21 is removed by dry etching. Due to the anisotropic etching, the silicon nitride film 10 is removed substantially reflecting the shape of the second opening 21. That is, the side surface of the etched silicon nitride film 10 has a substantially vertical shape.

  Then, the portion of the metal film 9 exposed by the removed silicon nitride film 10 is removed by wet etching, and the semiconductor device 1 has a structure as shown in FIG. 3E. In the etched metal film 9, the portion located on the element region 31 side becomes the source electrode 6, and the portion located on the termination region 30 side becomes the field plate electrode 7. Finally, the passivation film 8 is provided from a part of the element region 31 to the entire termination region 30, and the semiconductor device 1 has a structure as shown in FIG.

  Next, effects of the method for manufacturing the semiconductor device 1 according to the present embodiment will be described. First, a case where the silicon nitride film 10 is not formed on the metal film 9 in the manufacturing process as in the method for manufacturing the semiconductor device 1 according to the present embodiment will be described. In that case, the resist 11 is formed on the metal film 9 without forming the silicon nitride film 10 on the metal film 9, and the second opening 21 is formed in the resist 11. Thereafter, the portion of the metal film 9 exposed from the second opening 21 is removed by wet etching. In the case of wet etching, there is a possibility that the etching also proceeds to the metal film 9 located immediately below the resist 11. That is, the source electrode 6 and the field plate electrode 7 formed by etching a part of the metal film 9 have a shape that spreads upward. As the semiconductor device 1 is miniaturized, it is necessary to reduce the interval between adjacent field plate electrodes 7. However, as described above, it is difficult to miniaturize the semiconductor device 1 when the electrodes have a shape that spreads upward. Therefore, when the miniaturization of the semiconductor device 1 progresses, the interval between the adjacent field plate electrodes 7 cannot be reduced, and it becomes difficult to increase the breakdown voltage of the semiconductor device 1 and to ensure the reliability. Further, it is generally difficult to remove the metal by dry etching.

  In the method of manufacturing the semiconductor device 1 according to the present embodiment, the silicon nitride film 10 is formed between the metal film 9 and the resist 11, and the silicon nitride film 10 exposed from the second opening 21 is removed by dry etching. ing. Thereafter, the metal film 9 is etched by wet etching. Since the silicon nitride film 10 is provided between the metal film 9 and the resist 11, the etching of the metal film 9 immediately below the resist 11 is suppressed. Further, since the silicon nitride film 10 has resistance to wet etching, the silicon nitride film 10 directly under the resist 11 is not etched.

  Therefore, in the case of the method for manufacturing the semiconductor device 1 according to the present embodiment, the etching of the metal film 9 immediately below the resist 11 can be suppressed, so that the semiconductor device 1 can be miniaturized. That is, since the interval between adjacent field plate electrodes 7 can be narrowed, the breakdown voltage and reliability of the semiconductor device 1 can be ensured.

  Since the silicon nitride film 10 has a relatively large stress on the silicon substrate, if the silicon nitride film 10 is thickened, the N-type semiconductor substrate 2 may be warped in the manufacturing process of the semiconductor device 1. Therefore, it is desirable that the thickness of the silicon nitride film 10 is smaller than the thickness of the metal film 9.

  In this embodiment, the case where the silicon nitride film 10 is used has been described. However, the present invention is not limited to silicon nitride, and can be removed by dry etching and can be performed if it has resistance to wet etching.

  The manufacturing method described above is merely an example, and the order of forming the element part and the terminal part is not particularly limited. In addition to the CVD method, the film formation method is an atomic layer deposition (ALD) method capable of controlling the growth of a single atomic layer, a sputtering method, or a physical vapor deposition (PVD) method. It can also be carried out by a method, a coating method, a spraying method, or the like.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... N-type semiconductor substrate (semiconductor substrate), 3 ... P-type base region, 4 ... P-type guard ring region (semiconductor region), 5 ... Insulating film, 6 ... Source electrode, 7 ... Field plate electrode , 8 ... Passivation film, 9 ... Metal film, 10 ... Silicon nitride film (protective film), 11 ... Resist, 12 ... Drain electrode, 20 ... First opening, 21 ... Second opening, 30 ... Termination region, 31 ... Element region

Claims (3)

Provided on a second conductivity type semiconductor substrate having an element region and a termination region surrounding the element region and provided with a plurality of first conductivity type semiconductor regions, and having a first opening on the semiconductor region Forming an insulating film;
Forming a metal film on the opening and the insulating film;
Forming a protective film on the metal film;
Forming a resist provided on the protective film and having a second opening on the insulating film;
Removing the protective film located under the second opening by dry etching;
Removing the metal film located under the second opening by wet etching;
A method for manufacturing a semiconductor device comprising:   The method for manufacturing a semiconductor device according to claim 1, wherein the protective film is a nitride film.   The method for manufacturing a semiconductor device according to claim 1, wherein the thickness of the metal film is formed to be larger than the thickness of the protective film.

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