JP2011082411A - Method of manufacturing semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor element that can improve the yield. <P>SOLUTION: The method of manufacturing a semiconductor element includes the steps of forming a first insulation film on a semiconductor substrate; forming a plurality of stepped portions by an etching portion of the first insulation film, forming a conductive layer on the first insulation film, in such a manner as to cover the stepped portions; and etching a portion of the conductive layer that covers the step portions. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor element, and more particularly to a method for manufacturing a semiconductor element in which a step is generated in a structure such as an insulating film on a semiconductor substrate in a predetermined process.

  In recent years, devices using power semiconductor elements tend to be larger and larger in capacity. Accordingly, there is an increasing need for power semiconductor devices having large current characteristics and high breakdown voltage characteristics. In particular, in a circuit using a power semiconductor element, when a certain power semiconductor element changes from an on state to an off state, the power semiconductor element that is in the off state or a pn junction of another power semiconductor element. A high reverse voltage may be applied. Even in such a case, a high breakdown voltage characteristic that does not cause breakdown is required in the pn junction of these power semiconductor elements (for example, Patent Document 1).

  The breakdown voltage of the semiconductor element is determined by the depletion region of the pn junction. This is because most of the voltage applied to the pn junction is applied to the depletion region. Further, this breakdown voltage is affected by the curvature of the depletion region.

  For this reason, in the planar junction, the electric field concentrates on the edge portion where the curvature of the depletion region is larger than that of the flat portion, and avalanche breakdown is likely to occur from the edge portion. Accordingly, in the planar junction, the breakdown voltage of the entire depletion region is determined by the breakdown voltage at the edge portion.

  Therefore, as a method for increasing the breakdown voltage of the depletion region in the planar junction, a method of improving the curvature of the depletion region at the edge by forming a field plate at the edge is known (for example, Non-Patent Document 1). . In this method, the curvature of the depletion layer is controlled by changing the surface potential of the semiconductor substrate by applying a voltage to the field plate.

  In this method, the field plate is formed on the upper surface of an insulating film provided on the semiconductor substrate. In order to increase the breakdown voltage, it is necessary to increase the thickness of the insulating film. However, when the film thickness is increased, a step between the upper surface of the semiconductor substrate and the upper surface of the insulating film is increased.

Japanese Patent Laid-Open No. 10-335631

“Power Semiconductor Devices”, 1966, by B.J.Baliga, p. 100-102

  When forming a field plate on the upper surface of the insulating film, first, a conductive film is formed on the upper surface of the insulating film. At this time, the conductive film is also formed on the side surface of the insulating film. As described above, when the step between the upper surface of the semiconductor substrate and the upper surface of the insulating film becomes large, the conductive film formed on the side surface of the insulating film has a large thickness in the direction perpendicular to the upper surface of the semiconductor substrate. Become.

  For this reason, when the unnecessary conductive film is removed by dry etching or the like and the conductive film is left on the upper surface of the insulating film to form a field plate, the conductive film on the side surface of the insulating film may not be completely removed. In this case, a residue of the conductive film is generated on the side surface of the insulating film.

  As a result, the process after the field plate is formed is performed with the conductive film residue remaining. In the process after the field plate is formed, the conductive film residue is peeled off and reattached to the semiconductor substrate. As a result, the yield of power semiconductor elements decreases.

  In addition, as described above, when the field plate is formed, if the step between the upper surface of the semiconductor substrate and the upper surface of the insulating film becomes large, a conductive film different from the conductive film for the field plate is used as the insulating film. A film may be formed on top. Also in this case, a residue of the conductive film is generated on the side surface of the insulating film. Then, the residue of the conductive film is peeled off in a later process and reattached to the semiconductor substrate. As a result, the yield of power semiconductor elements decreases.

  The present invention has been made to solve this problem, and an object of the present invention is to provide a method for manufacturing a semiconductor device capable of improving the yield.

  According to a first aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a first insulating film on a semiconductor substrate; and forming a plurality of steps by etching a part of the first insulating film. And a step of forming a conductive layer on the first insulating film so as to cover the stepped portion, and a step of etching a portion of the conductive layer covering the stepped portion. is there.

  According to the present invention, the yield of semiconductor elements can be improved.

1 is a longitudinal sectional view showing a main part of a power semiconductor element according to a first embodiment. FIG. 6 is a process cross-sectional view illustrating a main part of the method for manufacturing the power semiconductor device according to the first embodiment. FIG. 6 is a process cross-sectional view illustrating a main part of the method for manufacturing the power semiconductor device according to the first embodiment. FIG. 6 is a process cross-sectional view illustrating a main part of the method for manufacturing the power semiconductor device according to the first embodiment. FIG. 6 is a process cross-sectional view illustrating a main part of the method for manufacturing the power semiconductor device according to the first embodiment. FIG. 6 is a process cross-sectional view illustrating a main part of the method for manufacturing the power semiconductor device according to the first embodiment. FIG. 6 is a process cross-sectional view illustrating a main part of the method for manufacturing the power semiconductor device according to the first embodiment. FIG. 6 is a process cross-sectional view illustrating a main part of the method for manufacturing the power semiconductor device according to the first embodiment. FIG. 6 is a process cross-sectional view illustrating a main part of the method for manufacturing the power semiconductor device according to the first embodiment. FIG. 6 is a process cross-sectional view illustrating a main part of the method for manufacturing the power semiconductor device according to the first embodiment. FIG. 6 is a process cross-sectional view illustrating a main part of the method for manufacturing the power semiconductor device according to the first embodiment. FIG. 6 is a process cross-sectional view illustrating a main part of the method for manufacturing the power semiconductor device according to the first embodiment. FIG. 6 is a process cross-sectional view illustrating a main part of the method for manufacturing the power semiconductor device according to the first embodiment. It is process sectional drawing which shows the principal part of the manufacturing method of the power semiconductor element which concerns on a 1st comparative example. It is process sectional drawing which shows the principal part of the manufacturing method of the power semiconductor element which concerns on a 1st comparative example. It is process sectional drawing which shows the principal part of the manufacturing method of the power semiconductor element which concerns on a 1st comparative example. It is a longitudinal cross-sectional view which shows the principal part of the power semiconductor element which concerns on a 1st modification. It is a longitudinal cross-sectional view which shows the principal part of the semiconductor element for electric power which concerns on a 2nd modification. FIG. 6 is a longitudinal sectional view showing a main part of a power semiconductor element according to a second embodiment. FIG. 10 is a process cross-sectional view illustrating the main part of the method for manufacturing the power semiconductor device according to the second embodiment. FIG. 10 is a process cross-sectional view illustrating the main part of the method for manufacturing the power semiconductor device according to the second embodiment. FIG. 10 is a process cross-sectional view illustrating the main part of the method for manufacturing the power semiconductor device according to the second embodiment. FIG. 10 is a process cross-sectional view illustrating the main part of the method for manufacturing the power semiconductor device according to the second embodiment. FIG. 10 is a process cross-sectional view illustrating the main part of the method for manufacturing the power semiconductor device according to the second embodiment. FIG. 10 is a process cross-sectional view illustrating the main part of the method for manufacturing the power semiconductor device according to the second embodiment. FIG. 10 is a process cross-sectional view illustrating the main part of the method for manufacturing the power semiconductor device according to the second embodiment. FIG. 10 is a process cross-sectional view illustrating the main part of the method for manufacturing the power semiconductor device according to the second embodiment. FIG. 10 is a process cross-sectional view illustrating the main part of the method for manufacturing the power semiconductor device according to the second embodiment. FIG. 10 is a process cross-sectional view illustrating the main part of the method for manufacturing the power semiconductor device according to the second embodiment. FIG. 10 is a process cross-sectional view illustrating the main part of the method for manufacturing the power semiconductor device according to the second embodiment. FIG. 10 is a process cross-sectional view illustrating the main part of the method for manufacturing the power semiconductor device according to the second embodiment. FIG. 10 is a process cross-sectional view illustrating the main part of the method for manufacturing the power semiconductor device according to the second embodiment. It is process sectional drawing which shows the principal part for the manufacturing method of the power semiconductor element which concerns on a 2nd comparative example. It is process sectional drawing which shows the principal part for the manufacturing method of the power semiconductor element which concerns on a 2nd comparative example. It is process sectional drawing which shows the principal part for the manufacturing method of the power semiconductor element which concerns on a 2nd comparative example.

Embodiment 1 FIG.
FIG. 1 is a longitudinal sectional view showing a main part of the power semiconductor element according to the first embodiment. The power semiconductor element 10 is a freewheeling diode. A p ⁺ -type impurity region 14 is formed on the upper surface side of the n-type semiconductor substrate 12. On the upper surface 12a of the semiconductor substrate, an insulating film 16 is formed from the position of the end 14b of the impurity region to the side surface 12b of the semiconductor substrate. A field plate 20 is formed on the upper surface 16a of the insulating film. A plurality of steps 18 are formed in the insulating film 16. An Al—Si electrode 20 is formed on the upper surface 14a of the impurity region. An n ⁺ type semiconductor layer 22 is formed on the lower surface side of the semiconductor substrate 12.

  The power semiconductor element 10 which is a freewheeling diode is used in the same circuit together with transistors such as IGBTs and MOSFETs. As described in the problem, when a transistor such as an IGBT or MOSFET is turned off from an on state, a high reverse voltage is applied to the pn junction between the impurity region 14 and the semiconductor substrate 12 in the power semiconductor element 10, Breakdown may occur. In order to prevent this, in the power semiconductor element 10, the electric field concentrated near the end 14 b of the impurity region is relaxed by the field plate 20.

  Hereinafter, the main part of the manufacturing method of the power semiconductor device 10 according to the first embodiment will be described. 2 to 13 are process cross-sectional views illustrating the main part of the method for manufacturing the power semiconductor device according to the first embodiment.

First, as shown in FIG. 2, p ⁺ -type impurity regions 14 are formed by diffusing p-type impurities in an n-type semiconductor substrate 12.

  Next, as shown in FIG. 3, an insulating film (first insulating film) 16 is formed on the upper surface 12a of the semiconductor substrate. Next, as shown in FIG. 4, a resist pattern 26 is formed on the insulating film 16 by photolithography. Next, as shown in FIG. 5, a part of the insulating film 16 is removed by dry etching or the like, and the insulating film 16 is left from the position of the end portion 14b of the impurity region to the side surface 12b of the semiconductor substrate. A part of the impurity region 14 is exposed from the insulating film 16. Further, a step 24 is formed between the upper surface 12a of the semiconductor substrate and the upper surface 16a of the insulating film.

  Next, as shown in FIG. 6, a resist pattern 26 is formed on the upper surface 16a of the insulating film other than a predetermined region on the step 24 side by photolithography. Next, as shown in FIG. 7, the insulating film 16 where there is no resist pattern 26 is etched to a predetermined thickness by dry etching or the like. Next, as shown in FIG. 8, the resist pattern 26 is formed again in a region other than the predetermined region on the step 24 side on the upper surface 16a of the insulating film, and the insulating film 16 where the resist pattern 26 does not exist is formed to a predetermined thickness. Etch. Next, as shown in FIG. 9, the remaining resist is removed. Thereby, a plurality of step portions 18 are formed in the insulating film 16 where the step 24 is generated.

  Next, as shown in FIG. 10, a doped polysilicon film (conductive layer) 28 is formed on the insulating film 16 so as to cover the plurality of steps 18. Next, as shown in FIG. 11, a resist pattern 26 is formed on the doped polysilicon film 28 on the upper surface 16a of the insulating film by photolithography. Next, as shown in FIG. 12, the portion covering the plurality of steps 18 in the doped polysilicon film 28 is removed by dry etching or the like, and the resist pattern 26 is removed as shown in FIG. . Thus, the doped polysilicon film 28 is left on the upper surface 16a of the insulating film to form the field plate 10. As described above, the power semiconductor element is manufactured.

  Here, the effect of the first embodiment will be described by comparing the manufacturing method according to the first embodiment with the method for manufacturing the power semiconductor element according to the first comparative example. 14-16 is process sectional drawing which shows the principal part of the manufacturing method of the power semiconductor device which concerns on a 1st comparative example.

  In the first comparative example, as shown in FIG. 14, a doped polysilicon film 28 is formed on the insulating film 16 without forming a plurality of steps 18 in the insulating film 16. Next, as shown in FIG. 15, a resist pattern 26 is formed on the doped polysilicon film 28. Next, as shown in FIG. 16, a part of the doped polysilicon film 28 is removed by dry etching or the like to form the field plate 10.

  Since a plurality of steps 18 are not formed in the insulating film 16, the doped polysilicon film 28 formed on the side surface 16b of the insulating film has a thickness in a direction perpendicular to the upper surface 12a of the semiconductor substrate. Therefore, the doped polysilicon film 28 on the side surface 16b of the insulating film cannot be completely removed, and the residue 30 remains.

  On the other hand, in the manufacturing method according to the first embodiment, a doped polysilicon film 28 is formed after a plurality of steps 18 are formed in the insulating film 16. Thus, as shown in FIG. 11, in the doped polysilicon film 28 formed on the side surface 16b of the insulating film, the thickness in the direction perpendicular to the upper surface 12a of the semiconductor substrate is smaller than that of the first comparative example. Become.

  Therefore, the doped polysilicon film 28 on the side surface 16b of the insulating film can be completely removed. For this reason, the residue 30 is not generated, and the yield of the power semiconductor element can be improved.

  If the thickness t of the insulating film shown in FIG. 13 is set to 1.5 μm or more, the residue 30 of the doped polysilicon film 28 is likely to occur when the plurality of steps 18 are not formed. For this reason, the above-mentioned effect is easy to obtain. The same applies to the following embodiments.

  Further, when the ratio of the height h of each step shown in FIG. 13 to the width w of each step of the plurality of steps shown in FIG. 13 is 1.0 or less, the effect of suppressing the generation of the residue 30 is large. Become. On the other hand, when the ratio is 0.1 or less, the effect is saturated. Further, when the ratio is reduced, the termination region 32 shown in FIG. 13 where the effect of the field plate 10 cannot be obtained becomes wider. For example, when the height h of each step is 2 μm and the ratio is 1.0, the width w of each step is 2 μm, but the height h of each step is 2 μm and the ratio is 0.01. In this case, the width w of each stage is 200 μm, and the termination region 32 is widened. Therefore, if the ratio is set to 0.1 to 1.0, it is possible to prevent the termination region 32 from being widened while effectively suppressing the generation of the residue 30. The same applies to the following embodiments.

  When the angle α between the upper surface 12a of the semiconductor substrate and the side surface 16b of the insulating film is 60 degrees or less, the doped polysilicon film 28 formed on the side surface 16b of the insulating film is perpendicular to the upper surface 12a of the semiconductor substrate. The thickness in a certain direction becomes smaller. For this reason, generation | occurrence | production of the residue 30 can be suppressed effectively. The same applies to the following embodiments.

  Furthermore, in the first embodiment, the semiconductor substrate 12 may be any of a silicon substrate, a SiC substrate, and a diamond substrate. In any case, the effects described above can be obtained. The same applies to the following embodiments.

  Further, in the first embodiment, when a step is generated between the upper surface 12a of the semiconductor substrate and the upper surface 16a of the insulating film, a plurality of steps 18 are formed in the insulating film 16. Even when a step is generated between the semiconductor substrate 12 and a member made of the same material, the same effect can be obtained by forming the plurality of step portions 18 in the same manner.

Below, the modification of Embodiment 1 is demonstrated.
Although the power semiconductor device according to the first embodiment is a free-wheeling diode, the method for manufacturing a power semiconductor device according to the first embodiment can be applied to power semiconductor devices other than the free-wheeling diode.

FIG. 17 is a longitudinal sectional view showing a main part of the power semiconductor device according to the first modification. The power semiconductor element 10 according to the first modification is an IGBT (insulated gate bipolar transistor). On the p ⁺ type collector layer 40, an n ⁺ type buffer layer 42 and an n ⁻ type epitaxial layer 44 are sequentially formed. A p base region 46 is formed on the upper surface side of the epitaxial layer 44. A polysilicon gate 48 is formed in a groove formed from the upper surface of the p base region 46 to the inside of the epitaxial layer 44. On the upper surface side of the p base region 46, an n ⁺ -type emitter region 52 is formed around the polysilicon gate 48 via a gate oxide film 50.

  Further, on the epitaxial layer 44, the insulating film 16 is formed from the position of the end portion 46b of the p base region to the side surface 44b of the epitaxial layer. As in the first embodiment, the insulating film 16 is provided with a plurality of steps 18. A field plate 20 is formed on the upper surface 16a of the insulating film.

  Even when the power semiconductor device according to the first modification is manufactured, the manufacturing method according to the first embodiment can be applied to form the multi-stepped portion 18 in the insulating film 16. Thereby, generation | occurrence | production of the residue of the conductive layer for field plates 20 can be suppressed, and the yield of the power semiconductor element can be improved.

FIG. 18 is a longitudinal sectional view showing a main part of a power semiconductor device according to a second modification. The power semiconductor element 10 according to the second modification is a MOSFET. An n ⁻ type epitaxial layer 56 is formed on the n ⁺ type semiconductor substrate 54. A p base region 58 is formed on the upper surface side of the epitaxial layer 56. A polysilicon gate 60 is formed in a groove formed from the upper surface of the p base region 58 to the inside of the epitaxial layer 56. On the upper surface side of the p base region 46, an n ⁺ type source region 64 is formed around the polysilicon gate 60 via a gate oxide film 62.

  Furthermore, on the epitaxial layer 52, the insulating film 16 is formed from the position of the end portion 58b of the p base region to the side surface 56b of the epitaxial layer. As in the first embodiment, the insulating film 16 is provided with a plurality of steps 18. A field plate 20 is formed on the upper surface 16a of the insulating film.

  Even when the power semiconductor device according to the second modification is manufactured, the manufacturing method according to the first embodiment can be applied to form the multi-stepped portion 18 in the insulating film 16. Thereby, generation | occurrence | production of the residue of the conductive layer for the field plate 20 can be suppressed, and the yield of the power semiconductor element can be improved.

Embodiment 2. FIG.
FIG. 19 is a longitudinal sectional view showing a main part of the power semiconductor device according to the second embodiment. The power semiconductor element 10 is an IGBT (insulated gate bipolar transistor). A p base region 46 is formed on the upper surface side of the n type semiconductor substrate 12, and an n ⁺ type emitter region 52 is formed in the p base region 46. A first insulating film 70 and a second insulating film 72 are formed on the semiconductor substrate 12.

  A field plate (not shown) is formed on the upper surface 70a of the first insulating film. In order to increase the breakdown voltage, the first insulating film 70 is formed thick. In addition, a plurality of steps 18 are formed in the first insulating film 70. Further, a contact hole 74 reaching the emitter region 52 is formed in the second insulating film 72. Inside the contact hole 74, a tungsten plug 76 is formed. An Al—Si electrode 78 is formed on the tungsten plug 76.

  Hereinafter, the main part of the manufacturing method of the power semiconductor device according to the second embodiment will be described. 20 to 31 are process cross-sectional views illustrating the main parts of the method for manufacturing the power semiconductor device according to the second embodiment.

First, as shown in FIG. 20, a first insulating film 70 is formed on the semiconductor substrate 12. A p base region 46 is formed on the upper surface side of the semiconductor substrate 12, and an n ⁺ -type emitter region 52 is formed in the p base region 46.

  Next, as shown in FIG. 21, after forming the resist pattern 26 by photolithography, a part of the first insulating film 70 is removed by dry etching or the like. The emitter region 52 is exposed. Further, a step 24 is formed between the upper surface 12a of the semiconductor substrate and the upper surface 70a of the first insulating film.

  Next, as shown in FIG. 22, a resist pattern 26 is formed on the upper surface 70a of the first insulating film other than a predetermined region on the emitter region 52 side by photolithography. Next, as shown in FIG. 23, the portion of the first insulating film 70 where the resist pattern 26 is absent is etched by dry etching or the like until a predetermined thickness is reached. Next, as shown in FIG. 24, on the upper surface 70a of the first insulating film, the resist pattern 26 is formed again in a region other than the predetermined region on the emitter region 52 side, and the portion of the first insulating film 70 where the resist pattern 26 is not present. Is etched to a predetermined thickness. Thereby, as shown in FIG. 25, in the first insulating film 70, a plurality of step portions 18 are formed at the place where the step 24 is generated.

  Next, as shown in FIG. 26, a second insulating film 72 is formed on the semiconductor substrate 12. Next, as shown in FIG. 27, a resist pattern 26 is formed on the second insulating film 72 by photolithography, and a part of the second insulating film 72 is removed by dry etching or the like. As a result, as shown in FIG. 28, a contact hole 74 reaching the emitter region 52 of the semiconductor substrate 12 is formed.

  Next, as shown in FIG. 29, a barrier metal 80 such as Ti / TiN is formed on the first insulating film 70 and the second insulating film 72 so as to cover the inner wall of the contact hole 74. Next, as shown in FIG. 30, a tungsten film (conductive layer) 82 is formed on the barrier metal 80 by a CVD method. At this time, the tungsten film 82 is formed so as to cover the plurality of steps 18, and further, the tungsten film 82 is formed so as to fill the inside of the contact hole 74.

  Next, as shown in FIG. 31, the tungsten film 82 is etched back to remove a portion of the tungsten film 82 that covers the above-described plurality of steps 18. As a result, the tungsten film 82 is left inside the contact hole 74 and a tungsten plug 76 is formed. Next, as shown in FIG. 32, an Al—Si electrode 78 is formed on the tungsten plug 76, and the unnecessary barrier metal 80 is removed.

  Here, the main part of the manufacturing method of the power semiconductor device according to the second comparative example will be described. 33 to 35 are process cross-sectional views illustrating the main part of the method for manufacturing the power semiconductor device according to the second comparative example.

  In the manufacturing method according to the second comparative example, as shown in FIG. 33, the tungsten film 82 is formed by the CVD method without forming the plurality of steps 18 in the first insulating film 70. Next, as shown in FIG. 34, the tungsten film 82 is etched and a tungsten plug 76 is formed. Next, as shown in FIG. 35, an Al—Si electrode 78 is formed, and unnecessary barrier metal 80 is removed.

  In the second comparative example, the plurality of steps 18 are not formed in the first insulating film 70. For this reason, in the tungsten film 82 formed on the side surface 70b of the first insulating film, the thickness in the direction perpendicular to the upper surface 12a of the semiconductor substrate increases. Therefore, when etching the tungsten film 82, the tungsten film 82 on the side surface 70b of the first insulating film cannot be completely removed, and the residue 30 remains.

  On the other hand, in the manufacturing method according to the second embodiment, the tungsten film 82 is formed after the plurality of steps 18 are formed in the insulating film 16. Thus, as shown in FIG. 30, the tungsten film 82 formed on the side surface 70b of the first insulating film has a thickness in a direction perpendicular to the upper surface 12a of the semiconductor substrate as compared with the second comparative example. Get smaller.

  Therefore, the tungsten film 82 on the side surface 70b of the first insulating film can be completely removed. For this reason, the residue 30 is not generated, and the yield of the power semiconductor element can be improved.

  In the second embodiment, the tungsten film 82 is formed by the CVD method as described above. For this reason, the tungsten film 82 is more likely to generate the residue 30 and more easily peeled off than a conductive layer formed by another method. For this reason, in Embodiment 2, the yield of the semiconductor element can be efficiently improved as compared with the case where the conductive layer is formed by a method other than the CVD method.

DESCRIPTION OF SYMBOLS 10 Power semiconductor element 12 Semiconductor substrate 14 Impurity region 16 Insulating film 18 Multi-stage step 28 Doped polysilicon film (conductive layer)
30 Residue 70 First insulating film 72 Second insulating film 74 Contact hole 82 Tungsten film

Claims (7)

Forming a first insulating film on the semiconductor substrate;
Etching a part of the first insulating film to form a plurality of steps;
Forming a conductive layer on the first insulating film so as to cover the stepped portion;
Etching a portion covering the step of the conductive layer;
The manufacturing method of the semiconductor element characterized by the above-mentioned. The semiconductor substrate is a first conductivity type semiconductor substrate;
A step of diffusing impurities of a second conductivity type in the semiconductor substrate to form an impurity region before forming the first insulating film;
Forming the first insulating film on an end portion of the impurity region so that a part of the impurity region is exposed when forming the first insulating film;
2. The method of manufacturing a semiconductor device according to claim 1, wherein when the conductive layer is etched, the conductive layer is left on the first insulating film to form a field plate. Forming a second insulating film on the semiconductor substrate after forming the step; and
Etching the second insulating film to form a contact hole reaching the semiconductor substrate before forming the conductive layer;
Further comprising
When forming the conductive layer, the conductive layer is formed inside the contact hole;
The method of manufacturing a semiconductor device according to claim 1, wherein the conductive layer is left inside the contact hole when the conductive layer is etched.   4. The method of manufacturing a semiconductor element according to claim 3, wherein when the conductive layer is formed, the conductive layer is made of tungsten and is formed by a CVD method.   5. The method of manufacturing a semiconductor element according to claim 1, wherein when the first insulating film is formed, the thickness of the first insulating film is set to 1.5 μm or more. 6. .   The ratio of the height of each step to the width of each step of the step portion is set to 0.1 to 1.0 when forming the step portion. The manufacturing method of the semiconductor element of description.   The semiconductor element manufacturing method according to claim 1, wherein when the step portion is formed, an angle between an upper surface of the semiconductor substrate and a side surface of the step portion is set to 60 degrees or less. Method.

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