JP2015158463A - Semiconductor chip measurement method and semiconductor chip - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable measurement method in which deterioration and destruction of a semiconductor chip under test are prevented.SOLUTION: A BIST circuit 3 for monitoring an input waveform is included in a semiconductor chip 8. During the execution of a DC contact test between pads and probe needles, the BIST circuit in the semiconductor chip determines AC waveform quality for each contact and returns a result of the determination to a tester. In addition, the BIST circuit has a power supply line different from that of an integrated circuit of an IC body and an individual control signal line separated from the operation of the IC body. In packaging, pads of them are wired to the ground so as not to operate.

Description

  The present invention relates to a method for measuring a semiconductor wafer using a probe card, and relates to a measuring apparatus and a measuring method for performing a functional inspection of a semiconductor chip on a semiconductor wafer.

  In order to measure the electrical characteristics of the semiconductor chip, the probe card attached to the probe device is brought into contact with the electrode pad on the semiconductor chip with the probe needle of the probe card. When conducting an electrical characteristic test on a semiconductor chip, a test for checking the contact between a probe needle and an electrode pad is usually performed before executing a test item for performing a function test. The electrode pads provided on the semiconductor chip are connected to the input / output circuit elements, and the contact property between the probe needle and the pad electrode is determined by measuring the characteristics of these elements.

  However, if a relatively thick natural oxide film remains on the surface of the electrode pad, or if the electrode protective film used in the process remains relatively thick due to insufficient etching, the insulating film on the electrode pad is attached to the probe needle. In many cases, the insulating film remains attached to the probe needle and the impedance of the pad electrode and the probe needle changes. The same applies when the pad electrode shavings or foreign matter in the probe device adheres with the probe needle.

  Even if the impedance changes, the DC contact resistance is 1Ω or less, so in the conventional test for measuring the contact resistance between the pad terminal and the probe needle, it is determined that there is no problem. The measurement accuracy of the functional inspection of the chip may be lowered, and the number of cases where a non-defective product is made defective is increased.

FIG. 2 is a diagram schematically showing a connection state between the tester and the semiconductor chip.
The environment for measuring the electrical characteristics and functions of the semiconductor chip 8 includes a tester 1, a probe card 13, a plurality of probe needles 12, a semiconductor chip 8, and a plurality of pads 4. The tester 1 is composed of several voltmeters, ammeters, a power source and a circuit for controlling timing, and a CPU, and executes a program in which items for conducting electrical characteristic tests and functional tests of semiconductor chips are described. The semiconductor chip 8 is inspected.

  The probe card 13 is arranged so as to be parallel to the semiconductor chip 8. The probe card 13 is connected to the tester 1, transmits a signal from the tester 1 to the semiconductor chip 8, and transmits a signal from the semiconductor chip 8 to the tester 1. I have a role to tell. A probe needle 12 having a sharp tip is fixed on the probe card 13 by soldering or the like, and the probe card 13 descends to contact the pad 4 on the semiconductor chip 8, and an output signal from the tester 1 is transmitted to the semiconductor. It has a function of propagating to the chip 8 and propagating an output signal from the chip to the tester 1.

  That is, when the probe card 13 is moved up and down and the probe needle 12 is brought into contact with the pad, the tester and the chip are electrically connected, and the contact is not established. FIG. 2 shows a state in which the probe needle 12 and the pad 4 on the semiconductor chip 8 are in contact with each other and the tester 1 can perform an electrical characteristic test and a function test on the semiconductor chip 8.

  Normally, when the probe needle 12 made of an alloy of beryllium or tungsten is contacted to the pad 4 made of aluminum, the aluminum is softer than the probe needle 12 alloy. The probe needle 12 comes into contact and good contact can be obtained. However, since the surface of the pad 4 has a hard film in many cases due to abnormal oxidation, an insulator, or a residual protective film, contact with the probe 4 with the probe needle 12 is not good, and the contact from the tester 1 is not good. In many cases, the waveform is deformed in the semiconductor chip 8.

  For example, when the reactance component of the conductance component of the contact portion is large, a voltage equal to or higher than the power supply voltage of the integrated circuit 2 is input from the pad 4 of the semiconductor chip 8 and the integrated circuit 2 malfunctions, and an accurate function test (IC operation) Function test) cannot be performed normally, and a non-defective IC may be determined to be defective, or the integrated circuit 2 may be broken while the function check of the integrated circuit 2 is being performed.

  In general, in order to solve the above problem, a circuit for preventing an excessive voltage from being input to the integrated circuit 2 is provided. However, if an input signal including a high-speed undershoot or overshoot including a high-frequency component is input from the pad 4, the input signal including an excessive voltage is directly input to the integrated circuit 2 without being able to follow the speed of the diode. End up. In order to prevent an excessive voltage with a high frequency component from being input to the integrated circuit 2, it is very important to detect an input signal including an excessive voltage with a high frequency component.

  Also, since the aluminum is soft, the probe needle 12 comes into contact with the aluminum of the pad 4 so that the scrap 11 is generated and remains in the semiconductor measurement environment. In some cases, the contact with the needle 13, the semiconductor chip 8, and the pad 4 may cause AC contact failure.

  In order to solve these problems, in a semiconductor wafer measurement method and measurement apparatus used for a probe card, an unnecessary film such as an insulating film on the pad is removed by the preceding probe needle contacting the pad, and thereafter A subsequent probe needle is brought into contact with the pad so as to improve the contact property between the probe needle and the pad on the IC chip, thereby ensuring measurement reliability. (For example, see Patent Document 1)

JP 2007-232536 A

  However, in these methods, although the DC contact resistance can be reduced, the AC impedance is not considered, and the waveform deformation due to the high frequency noise multiplexed in the signal is not considered. Therefore, it does not lead to improvement in the reliability of the function test.

In addition, it is considered that the probe needle that contacts the pad in advance will surely remove the film on the pad surface, and it is considered that the scrap remains also in the wafer measurement system, so that sufficient measurement reliability is ensured. It's hard to say.
Further, since the needle traces are always formed on the pad, it is easy for the neck to break when wire bonding is performed in the mounting process.

  The object of the present invention is to measure the electrical characteristics of a semiconductor wafer using a probe card, even when a thick insulating film or the like is formed on the surface of the electrode pad of each semiconductor chip. It is an object of the present invention to provide a measurement method capable of measuring the characteristics of a semiconductor chip satisfactorily by determining whether or not a good contact is formed between the pad electrodes and forming a good contact in terms of AC.

  In order to solve the problem, the present invention has a BIST (BUILT-IN SELF-TEST) circuit different from the integrated circuit of the IC body inside the semiconductor chip, and performs a DC contact test between the pad and the probe needle. In the meantime, the semiconductor wafer measuring method is such that the BIST circuit in the semiconductor chip determines the AC waveform quality at each contact and returns the result to the tester.

The BIST circuit operates with a power source different from that of the integrated circuit of the IC body.
The BIST circuit has an integrated circuit of the IC main body, a separate power line, and an individual control signal separated from the operation of the IC main body. When packaging, these pads wire to the ground and do not operate. It is characterized by doing so.

Further, the BIST circuit has a differentiating circuit realized by a delay circuit and a comparator.
In addition, when the tester during wafer measurement has a problem with the waveform quality, the tester performs a plurality of times per needle.

  According to the present invention, while performing a test for confirming the consistency per needle like a normal DC, the BIST circuit in the semiconductor chip detects the AC waveform quality, and the result is used as a tester. By transmitting a signal and performing contact again, the AC impedance change is removed, and if there is no problem, the next function test is executed as it is. Measurement reliability can be greatly improved.

  By making the contact between the pad electrode and the probe needle a plurality of times in this way, it is possible to more reliably obtain a good electrical contact between the probe and the pad electrode, and improve the measurement accuracy of the electrical characteristics of the semiconductor chip. Can be made.

The semiconductor measuring device figure which shows embodiment of this invention. The connection state figure which shows embodiment of this invention. 1 is a BIST circuit diagram illustrating an embodiment of the present invention. The timing diagram which shows embodiment of this invention.

FIG. 1 is an example of a method for measuring a semiconductor chip according to the present invention, and is a diagram schematically showing a semiconductor measuring device and a semiconductor chip.
In the semiconductor chip measurement method according to the present embodiment, the tester 1 for performing semiconductor characteristic evaluation, the integrated circuit 2 disposed in the semiconductor chip 8 to be measured and evaluated, and the contact between the tester 1 and the semiconductor chip 8 are used. A system including a plurality of pads 41, an input signal 5 connected to the tester 1, and a BIST circuit 3 for determining waveform quality on the semiconductor chip 8 is used.

  The integrated circuit 2 disposed on the semiconductor chip 8 is a circuit having a predetermined function as a semiconductor, and includes a digital circuit and / or an analog circuit, and includes a plurality of input / output signal terminals, a power supply It has a terminal, a GND terminal, etc., and is wired to the pad 41 on the semiconductor chip 8 by wiring such as aluminum.

  The BIST circuit 3 is connected to the BIST circuit power supply line 6 and the BIST circuit control signal line 7 via pads 42 on the semiconductor chip 8. The input signal 5 connected to the tester 1 is connected to the semiconductor chip 8. It is connected to the BIST circuit 3 through the pad 41. In the semiconductor chip 8, the input signal 5 is wired to the integrated circuit 2 and the BIST circuit 3 via a plurality of pads 41, but is connected in consideration of reflection, attenuation, and the like.

  In this embodiment, when an AC contact failure is detected, the probe card 12 is raised, the probe needle 13 is washed or cleaned with a polishing sheet, and then the probe card 12 is lowered to perform remeasurement. By doing so, the AC contact is improved.

FIG. 3 is a diagram showing the BIST circuit used in the embodiment of the present invention in more detail.
The BIST circuit 3 includes a timing controller 21, a voltage detection circuit (VD) 22, a comparator 23, a delay circuit 24, and a plurality of relays 25.

The control signal 7 of the BIST circuit is a signal obtained by multiplexing the input signal selection information 7a transmitted from the tester 1, the delay circuit delay amount information 7b, and the circuit reference voltage selection information 7c of the voltage detection circuit (VD) ( (Refer to FIG. 4 for the signals to be each information). The timing controller 21 outputs a relay control signal 31 for selecting a plurality of input signals 5 from the control signal 7 of the BIST circuit, sets an appropriate delay amount in the delay circuit 24, and sets a reference voltage in the VD 22. Set the value. The control signal 7 of the BIST circuit is a signal configured by the SPI protocol, and may be realized by various specifications such as I ² C, SPI, MICROWIRE, and the like.

  The timing controller 21 generates relay control, a delay amount set, and a reference voltage set at a timing at which the BIST circuit 3 operates normally, and controls the VD 22, the delay circuit 24, and the relay 25.

  The delay circuit 24 is a circuit in which the delay amount can be set in 1 nS steps from 1 nS to 100 nS. The delay circuit 24 creates a signal obtained by delaying the input signal 5 selected by the relay 25 by the set delay amount. On the negative side, an input signal 5 having no delay is inputted to the comparator 23 to generate a signal obtained by differentiating the input signal 5 by a set delay amount.

  Since the differential amount of the input signal 5 is an AC variation, it is considered that the noise component of the input signal 5 is converted into a signal, and the waveform quality of the input signal 5 is inspected by detecting the value of this signal with the VD 22. I can do it.

  The BIST circuit 3 including the timing controller 21, voltage detection circuit (VD) 22, comparator 23, delay circuit 24, and a plurality of relays 25 only needs to be mounted on a semiconductor chip. Confirmation of AC contact with the probe needle is sequentially performed in step S2.

FIG. 4 is a timing chart showing the first embodiment of the present invention.
When a predetermined voltage is applied from the tester 1 to the power supply 6 for the BIST circuit, the circuit in the BIST circuit 3 enters an operation standby state.

  After a predetermined time has elapsed since the voltage was applied to the BIST circuit power source 6, the BIST circuit control signal 7 includes the integrated circuit 2 input signal selection information 7a and the voltage detection circuit (VD) reference voltage selection information 7b. The delay circuit delay amount information 7c is input to the timing controller 21 by the serial communication method.

In the present embodiment, the SPI (Serial Peripheral Interface) communication method used for serial EEPROM or the like is used as the serial communication method, but other communication methods such as I ² C and MICROWIRE may be used.

  Upon receiving the control signal 7 of the BIST circuit from the tester 1, the timing controller 21 sets the reference voltage value in the VD 22, the delay amount in the delay circuit, and turns on the selected relay 25.

  When the input signal 5 is input from the tester 1 to the contact position between the probe needle 12 to be tested and the pad 4, the input signal 5 is divided by the delay circuit 24 of the BIST circuit 3 into several signals that have been set with a delay. Since adjacent delay signals are input to the + and-terminals of the analog comparator 23, the difference between the delay signals is detected, and the waveform of the input signal is differentiated electrically. Similar effects can be obtained. Here, since the waveform distortion and the differential waveform of the signal are correlated, the waveform distortion is detected as a differential signal 32 that is a voltage change of the differential waveform.

  When the differential signal 32 of the comparator 23 that detects the difference between the delay signals is compared with the reference voltage in the VD 22, if it is determined that the waveform distortion is large, it is detected and the determination signal 33 is set. This signal is sent to the timing controller 21, multiplexed with the control signal 7 of the BIST circuit, and sent to the tester 1.

  At this time, since the reference voltage set to the VD 22 determines the degree of waveform distortion, it is possible to set the value suitable for the waveform quality required for the measurement in advance so that there is no problem with AC contact. It is structured to be able to judge.

This is repeated a number of times corresponding to the pad 4, and when this operation is completed, the BIST circuit power supply 6 is set to the GND level, the AC contact test is terminated, and the normal function test of the integrated circuit 2 is subsequently executed.
When the tester 1 detects a signal having a large waveform distortion in the control signal 7 of the BIST circuit, the tester 1 executes an operation for improving AC contact.

  In the present embodiment, when the signal from the VD 22 indicating that the waveform quality is poor is multiplexed in the control signal 7 of the BIST circuit, the probe card 13 or the probe needle 12 is moved up and down to make contact again, and the probe needle 12 And an operation for improving the AC contact between the pad 4 and the pad 4.

  When the semiconductor chip 8 is packaged, the BIST circuit control signal 7 and the BIST circuit power supply 6 are wired to GND, so that after the product is shipped, the BIST circuit 3 malfunctions due to malfunction. It is made not to generate.

1 Tester 2 Integrated circuit 3 BIST circuit 4 Pad 5 Input signal 6 BIST circuit power supply, BIST circuit power supply line 7 BIST circuit control signal, BIST circuit control signal line 7a Input signal selection information 7b Delay circuit delay amount information 7c VD circuit reference voltage selection Information 8 Semiconductor chip (chip)
11 Cutting residue 12 Probe needle 13 Probe card 21 Timing controller 22 VD
23 Comparator 24 Delay Circuit 25 Relay 31 Relay Control Signal 32 Differential Signal 33 Determination Signal 41 Pad 42 Pad

Claims (6)

A semiconductor chip measuring method in which a BIST circuit is provided inside a semiconductor chip having an integrated circuit, and at the contact between each probe needle and a pad, the BIST circuit determines an AC waveform quality and returns the result to a tester. Because
Applying a voltage from the tester to the BIST circuit to place the BIST circuit in a standby state;
Step 1 of inputting the input signal selection information of the integrated circuit, the reference voltage selection information of the voltage detection circuit, and the delay circuit delay amount information as control signals from the tester to the timing controller of the BIST circuit by a serial communication method;
A step 2 in which the timing controller sets a reference voltage value in the voltage detection circuit, a delay amount in the delay circuit, and inputs an input signal to a contact position between the probe needle and the pad to be tested;
Step 3 in which the BIST circuit inputs a differential signal that is a differential waveform of the input signal to the voltage detection circuit;
Step 4 in which the BIST circuit sets the determination signal according to the magnitude of the differential signal, multiplexes it with the control signal, and transmits it to the tester.
Have
A method for measuring a semiconductor chip, wherein the steps 1 to 4 are repeated at the contact between each probe needle and a pad.   2. The semiconductor chip measuring method according to claim 1, wherein the power supply voltage of the BIST circuit is supplied from a pad different from the integrated circuit body.   3. The BIST circuit according to claim 1, wherein when the BIST circuit is packaged, the BIST circuit power supply and a pad for supplying a control signal are electrically connected to a GND terminal of the package. Measuring method of semiconductor chip.   4. The BIST circuit according to claim 1, wherein an analog differentiating circuit is configured by a delay circuit capable of setting a delay amount from 1 nS to 100 nS with a resolution of 1 nS and a high-speed comparator. The method for measuring a semiconductor chip according to item.   5. The BIST circuit according to claim 1, wherein the BIST circuit performs information regarding delay setting, VD reference voltage setting, and signal line selection using a one-line signal protocol. The measuring method of the semiconductor chip of description. An integrated circuit;
A plurality of pads for characterization of the integrated circuit;
A BIST circuit different from the integrated circuit;
Have
The BIST circuit is only one set,
A timing controller;
A delay circuit;
A comparator,
A voltage detection circuit;
A power pad for the BIST circuit;
A pad for inputting and outputting control signals;
A semiconductor chip, wherein differential waveforms of input signals sequentially applied to the plurality of pads are sequentially output from pads for inputting and outputting the control signals.

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