JP2015130457A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2015130457A
JP2015130457A JP2014002131A JP2014002131A JP2015130457A JP 2015130457 A JP2015130457 A JP 2015130457A JP 2014002131 A JP2014002131 A JP 2014002131A JP 2014002131 A JP2014002131 A JP 2014002131A JP 2015130457 A JP2015130457 A JP 2015130457A
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sealing resin
semiconductor element
case
semiconductor
surface electrode
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JP6057927B2 (en
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和弘 多田
Kazuhiro Tada
和弘 多田
万里子 ▲高▼原
万里子 ▲高▼原
Mariko Takahara
範之 別芝
Noriyuki Betsushiba
範之 別芝
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which inhibits peeling and cracks in a simple structure to achieve high reliability.SOLUTION: A semiconductor device 100 comprises: a heat sink 10 on which a plurality of internal modules each including a semiconductor element substrate in which a semiconductor electrode is fastened on a surface electrode, a plurality of main terminals 5a, 5b bonded to a top face of the semiconductor element and the surface electrode, respectively, and a first encapsulation resin 9 for encapsulating the inside of a first case 4 provided on a peripheral part of the surface electrode so as to cover the semiconductor element and the semiconductor element substrate; and a second encapsulation resin 13 for encapsulating the inside of a second case 12 provided on a peripheral part of the heat sink so as to cover the first encapsulation resin, the first case and the semiconductor element substrate. At least the surface electrode inside the first case covers a whole area of an insulation substrate and the surface electrode and a rear face electrode are formed symmetry with respect to the insulation substrate. The plurality of main terminals are exposed to the outside of the second encapsulation resin and an elastic modulus of the second encapsulation resin is smaller than an elastic modulus of the first encapsulation resin.

Description

この発明は、電力用半導体素子を実装した半導体装置、特に大容量で高温で動作する半導体装置の実装構造に関するものである。   The present invention relates to a semiconductor device mounted with a power semiconductor element, and more particularly to a mounting structure of a semiconductor device that operates at a high temperature with a large capacity.

従来のケース型の半導体装置は、一般にシリコーンゲルにてケース内の半導体素子周辺が封止されている。一方、エポキシ封止はチップ周辺を硬い樹脂で拘束することからヒートサイクルやパワーサイクル信頼性が高い。しかし、エポキシ樹脂は硬いことから接する部材との線膨張係数差大きいと界面に発生する応力が高く、剥離やクラックという問題が発生するため、構成部材との線膨張係数を合わせるなど制約が多い。   In a conventional case type semiconductor device, the periphery of a semiconductor element in a case is generally sealed with silicone gel. On the other hand, epoxy sealing has high heat cycle and power cycle reliability because the periphery of the chip is constrained by a hard resin. However, since the epoxy resin is hard, if the difference in linear expansion coefficient from the member in contact with the epoxy resin is large, the stress generated at the interface is high, causing problems such as peeling and cracking.

特許文献１に記載されている半導体装置は、金属ベースにカーボンナノチューブ膜を介して半導体素子基板を接合している。半導体素子と外部端子との接続に関し、主端子および信号端子ともケース材と一体成型したインサートケースを用いている。そのインサートケース内部をエポキシ樹脂で封止する構造を採用している。   In the semiconductor device described in Patent Document 1, a semiconductor element substrate is bonded to a metal base via a carbon nanotube film. Regarding the connection between the semiconductor element and the external terminal, an insert case integrally molded with the case material is used for both the main terminal and the signal terminal. A structure is employed in which the inside of the insert case is sealed with an epoxy resin.

また、特許文献２に記載されているケース型の半導体装置は、半導体素子基板の絶縁基板が露出している部分を、ケース内部を封止する封止樹脂よりも小さい弾性率の樹脂により覆って、剥離やクラックが発生し難くしている。   Further, in the case type semiconductor device described in Patent Document 2, the portion of the semiconductor element substrate where the insulating substrate is exposed is covered with a resin having a smaller elastic modulus than the sealing resin for sealing the inside of the case. , Peeling and cracking are less likely to occur.

特開２００８−２５８５４７号公報JP 2008-258547 A 国際公開ＷＯ２０１２／０７０２６１号International Publication WO2012 / 070261

高熱伝導性が要求される金属ベースとしては、銅やアルミニウムが用いられる場合が多い。また、半導体素子基板はセラミックス基板の両面に回路パターンが設けられ、回路パターンの上面には半導体素子が搭載されている。特許文献１に記載されている半導体装置のように、インサートケース内に半導体素子基板が設置され、インサートケース内をエポキシ樹脂で封止した場合、金属ベース、半導体素子基板、半導体素子の熱膨張係数が大きく異なることにより、ヒートサイクル時にエポキシ樹脂の割れや剥離などが発生する。このエポキシ樹脂の割れや剥離は、モジュール寿命の低下をまねく課題がある。   In many cases, copper or aluminum is used as a metal base that requires high thermal conductivity. The semiconductor element substrate is provided with circuit patterns on both sides of the ceramic substrate, and the semiconductor elements are mounted on the upper surface of the circuit pattern. As in the semiconductor device described in Patent Document 1, when a semiconductor element substrate is installed in an insert case and the inside of the insert case is sealed with an epoxy resin, the coefficient of thermal expansion of the metal base, the semiconductor element substrate, and the semiconductor element Due to the large difference, cracking or peeling of the epoxy resin occurs during the heat cycle. This cracking or peeling of the epoxy resin has a problem of reducing the module life.

特許文献２に記載されている半導体装置においては、半導体素子基板の絶縁基板が露出している部分を封止樹脂よりも小さい弾性率の封止樹脂で覆っているため、剥離やクラックの発生が抑制されるが、半導体装置の製造工程が増加するという問題がある。   In the semiconductor device described in Patent Document 2, the portion where the insulating substrate of the semiconductor element substrate is exposed is covered with a sealing resin having an elastic modulus smaller than that of the sealing resin. Although suppressed, there is a problem that the manufacturing process of the semiconductor device increases.

この発明は、上記のような問題点を解決するためになされたものであり、ケース型の半導体装置において、単純な構造で剥離やクラックが抑制され、高い信頼性を得ることを目的としている。   The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain high reliability in a case-type semiconductor device in which peeling and cracks are suppressed with a simple structure.

この発明は、絶縁基板の片面に表面電極が、および前記絶縁基板の他の面に裏面電極が、それぞれ形成された半導体素子基板と、表面電極の、絶縁基板とは反対側の面に接合材を介して固着された半導体素子と、表面電極に接合された第１の主端子および半導体素子の表面電極とは反対側の面に接合された第２の主端子と、半導体素子基板の周辺部の表面電極上に設置され信号端子が一体成型された第１のケースと、第１のケースの内部を、半導体素子と半導体素子基板とを覆うように封止する第１の封止樹脂とを備えた内部モジュールが、一面に複数、それぞれの内部モジュールの裏面電極を接合して配置された放熱板と、放熱板の周辺部であって、内部モジュール側に設けられた第２のケースと、第２のケースの内部を、第１の封止樹脂と第１のケースと半導体素子基板とを覆うように封止する第２の封止樹脂と、を備えた半導体装置において、少なくとも第１のケース内部の表面電極は、絶縁基板全体を被覆し、かつ表面電極と裏面電極は、絶縁基板に対して対称に形成されており、第１の主端子および第２の主端子は第１の封止樹脂および第２の封止樹脂を貫通して第２の封止樹脂の外部に露出するとともに、第２の封止樹脂の弾性率が第１の封止樹脂の弾性率よりも小さくしたものである。   The present invention relates to a semiconductor element substrate in which a surface electrode is formed on one surface of an insulating substrate and a back electrode is formed on the other surface of the insulating substrate, and a bonding material on a surface of the surface electrode opposite to the insulating substrate. A semiconductor element fixed via the surface electrode, a first main terminal bonded to the surface electrode, a second main terminal bonded to the surface opposite to the surface electrode of the semiconductor element, and a peripheral portion of the semiconductor element substrate A first case in which a signal terminal is integrally molded and a first sealing resin that seals the inside of the first case so as to cover the semiconductor element and the semiconductor element substrate. A plurality of internal modules provided on one side, a heat sink arranged by joining the back electrodes of the respective internal modules, and a second case provided on the side of the internal module at the periphery of the heat sink; The inside of the second case is replaced with the first sealing resin And a second sealing resin for sealing so as to cover the first case and the semiconductor element substrate. At least the surface electrode inside the first case covers the entire insulating substrate; and The front electrode and the back electrode are formed symmetrically with respect to the insulating substrate, and the first main terminal and the second main terminal pass through the first sealing resin and the second sealing resin and pass through the second sealing resin. And the elastic modulus of the second sealing resin is smaller than the elastic modulus of the first sealing resin.

この発明によれば、第１のケース内部の表面電極は絶縁基板全体を被覆しているため、表面電極の上面に配置された第１のケース内を熱硬化性のエポキシ樹脂で封止することにより、絶縁基板とエポキシ樹脂が触れることがなく、また半導体素子周囲を硬いエポキシ樹脂で覆うことから、エポキシ樹脂の割れや剥離を防止することが可能となり、耐ヒートサイクル性や耐パワーサイクル性が高く、信頼性の高い半導体装置を得ることができる。   According to the present invention, since the surface electrode inside the first case covers the entire insulating substrate, the inside of the first case disposed on the upper surface of the surface electrode is sealed with the thermosetting epoxy resin. This prevents the insulating substrate and the epoxy resin from touching each other and covers the periphery of the semiconductor element with a hard epoxy resin, so that it is possible to prevent cracking and peeling of the epoxy resin, resulting in heat cycle resistance and power cycle resistance. A highly reliable semiconductor device can be obtained.

この発明の実施の形態１による半導体装置の構成の一部である内部モジュールを示す側面断面図である。It is side surface sectional drawing which shows the internal module which is a part of structure of the semiconductor device by Embodiment 1 of this invention. この発明の実施の形態１による半導体装置の構成の一部である半導体素子基板の上面図である。1 is a top view of a semiconductor element substrate which is a part of a configuration of a semiconductor device according to a first embodiment of the present invention. この発明の実施の形態１による半導体装置の構成の一部である内部モジュールの第１の封止樹脂を取り除いた状態の上面図である。It is a top view of the state which removed the 1st sealing resin of the internal module which is a part of structure of the semiconductor device by Embodiment 1 of this invention. この発明の実施の形態１による半導体装置の全体構成を示す側面断面図である。1 is a side sectional view showing an overall configuration of a semiconductor device according to a first embodiment of the present invention. この発明の実施の形態２による半導体装置の製造工程のうち前半の工程を示す工程図である。It is process drawing which shows the process of the first half among the manufacturing processes of the semiconductor device by Embodiment 2 of this invention. この発明の実施の形態２による半導体装置の製造工程のうち図５に示した工程に続く工程を示す工程図である。FIG. 6 is a process diagram illustrating a process following the process illustrated in FIG. 5 among the processes for manufacturing a semiconductor device according to the second embodiment of the present invention; この発明の実施の形態３による半導体装置の製造工程を示す工程図である。It is process drawing which shows the manufacturing process of the semiconductor device by Embodiment 3 of this invention. この発明の半導体装置の実施例によるヒートサイクル試験結果の表を示す図である。It is a figure which shows the table | surface of the heat cycle test result by the Example of the semiconductor device of this invention.

実施の形態１．
図１は、本発明の実施の形態１による半導体装置の構成の一部である内部モジュール２０を示す側面断面図である。図１において、セラミックスなどの絶縁基板３ａの片面には、パターンを有さない単一の表面電極３ｂが形成され、他の面には、やはりパターンを有さない単一の裏面電極３ｃが形成されている。表面電極３ｂおよび裏面電極３ｃは銅などの導電性材料の薄板である。表面電極３ｂおよび裏面電極３ｃが形成された絶縁基板３ａを、ここでは半導体素子基板３と称する。半導体素子基板３の表面電極３ｂのうちの所定の位置に、半導体素子１ａ、１ｂが導電性の接合材２を用いて固定され、半導体素子１ａの一方の主電極と半導体素子１ｂの一方の主電極が電気的に接続される。ここで、半導体素子１ａは例えばＩＧＢＴ（Insulated Gate Bipolar Transistor）やＭＯＳＦＥＴ（Metal Oxide Semiconductor Field-Effect-Transistor）のようなスイッチング素子である。半導体素子１ｂは例えばスイッチング素子と並列に接続される還流ダイオードである。 Embodiment 1 FIG.
FIG. 1 is a side sectional view showing an internal module 20 which is a part of the configuration of the semiconductor device according to the first embodiment of the present invention. In FIG. 1, a single surface electrode 3b having no pattern is formed on one surface of an insulating substrate 3a such as ceramic, and a single back electrode 3c also having no pattern is formed on the other surface. Has been. The front electrode 3b and the back electrode 3c are thin plates made of a conductive material such as copper. The insulating substrate 3a on which the front electrode 3b and the back electrode 3c are formed is referred to as a semiconductor element substrate 3 here. The semiconductor elements 1a and 1b are fixed at predetermined positions on the surface electrode 3b of the semiconductor element substrate 3 by using the conductive bonding material 2, and one main electrode of the semiconductor element 1a and one main electrode of the semiconductor element 1b are fixed. The electrodes are electrically connected. Here, the semiconductor element 1a is a switching element such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field-Effect-Transistor). The semiconductor element 1b is, for example, a free wheel diode connected in parallel with the switching element.

スイッチング素子である半導体素子１ａのゲート電極や、電流センサあるいは温度センサといったセンサ類などの信号の入出力を行う信号端子６が第１のケース４と一体成型されて設けられている。信号端子６と半導体素子１ａのゲート電極やセンサ類との信号伝送のための電気的な接続はボンディングワイヤ７により行われる。また、半導体素子１ａ、１ｂの表面電極３ｂとの接合面との反対側の面に形成された主電極（他方の主電極）は、第２の主端子５ｂとなる金属板で導電性の接合材８を用いて固定されるとともに電気的に接続される。一方、表面電極３ｂには第１の主端子５ａが電気的に接合材を用いて接続される。第１の主端子５ａと第２の主端子５ｂをまとめて主端子５と称することもある。第１の主端子５ａと第２の主端子５ｂは、これらの端子を通じて半導体装置の半導体素子１ａや１ｂが制御する電力用の電流を、半導体素子１ａや１ｂに流すための端子である。   A signal terminal 6 for inputting / outputting signals such as a gate electrode of the semiconductor element 1a which is a switching element and sensors such as a current sensor or a temperature sensor is integrally formed with the first case 4. Electrical connection for signal transmission between the signal terminal 6 and the gate electrode and sensors of the semiconductor element 1 a is performed by a bonding wire 7. The main electrode (the other main electrode) formed on the surface opposite to the bonding surface with the surface electrode 3b of the semiconductor elements 1a and 1b is a metal plate serving as the second main terminal 5b and is conductively bonded. The material 8 is fixed and electrically connected. On the other hand, the first main terminal 5a is electrically connected to the surface electrode 3b using a bonding material. The first main terminal 5a and the second main terminal 5b may be collectively referred to as the main terminal 5. The first main terminal 5a and the second main terminal 5b are terminals for allowing a current for power controlled by the semiconductor elements 1a and 1b of the semiconductor device to flow through the semiconductor elements 1a and 1b through these terminals.

第１のケース４は、接着剤を介して表面電極３ｂの周辺部上に固定されている。半導体素子１ａ、１ｂや配線部材であるボンディングワイヤ７や主端子５を含めて、第１のケース４の内部が第１の封止樹脂９で封止されている。ただし、配線部材のうち第１の主端子５ａおよび第２の主端子５ｂは、外部との電気的接続を行うために上部が第１の封止樹脂９から露出している。   The first case 4 is fixed on the periphery of the surface electrode 3b via an adhesive. The inside of the first case 4 is sealed with a first sealing resin 9 including the semiconductor elements 1 a and 1 b, the bonding wires 7 that are wiring members, and the main terminals 5. However, the upper part of the first main terminal 5a and the second main terminal 5b of the wiring member is exposed from the first sealing resin 9 in order to make an electrical connection with the outside.

つぎに、各部材の詳細について説明する。半導体素子１ａ、１ｂは、シリコーン（Ｓｉ）を基材とした一般的な素子でも良いが、本発明は、より高温で動作する半導体素子に適用したときに好適な構造を目指している。半導体素子１ａ、１ｂが、例えば炭化ケイ素（ＳｉＣ）や窒化ガリウム（ＧａＮ）系材料、またはダイヤモンドといったシリコーンと較べてバンドギャップが広い、いわゆるワイドバンドギャップ半導体材料の半導体素子、特に炭化ケイ素を用いた半導体素子に本発明は好適である。デバイス種類としては、特に限定しないが、ＩＧＢＴ（Insulated Gate Bipolar Transistor）やＭＯＳＦＥＴ（Metal Oxide Semiconductor Field-Effect-Transistor）のようなスイッチング素子、またはダイオードのような整流素子が考えられる。   Next, details of each member will be described. The semiconductor elements 1a and 1b may be general elements based on silicone (Si), but the present invention aims at a suitable structure when applied to a semiconductor element operating at a higher temperature. The semiconductor elements 1a and 1b use semiconductor elements of a so-called wide band gap semiconductor material, particularly silicon carbide, which has a wider band gap than silicon carbide (SiC), gallium nitride (GaN) based materials, or silicone such as diamond. The present invention is suitable for semiconductor elements. Although it does not specifically limit as a device kind, Switching elements, such as IGBT (Insulated Gate Bipolar Transistor) and MOSFET (Metal Oxide Semiconductor Field-Effect-Transistor), or a rectifier element like a diode can be considered.

例えば半導体素子１ａがＭＯＳＦＥＴの場合、半導体素子１ａの表面電極３ｂ側の面にはドレイン電極が形成されている。ドレイン電極と反対側（図１では上側）の面には、ゲート電極やソース電極が、領域を分けて形成されている。なお、ドレイン電極の表面には接合材との接合を良好とするための複合金属膜が形成されている。ソース電極の表面にも、厚さ数μｍの薄いアルミニウムなどの電極膜やチタン、モリブデン、ニッケル、金などの薄膜層が形成されている。   For example, when the semiconductor element 1a is a MOSFET, a drain electrode is formed on the surface of the semiconductor element 1a on the surface electrode 3b side. On the surface opposite to the drain electrode (upper side in FIG. 1), a gate electrode and a source electrode are formed in divided regions. Note that a composite metal film is formed on the surface of the drain electrode to improve the bonding with the bonding material. On the surface of the source electrode, a thin electrode film such as aluminum having a thickness of several μm and a thin film layer such as titanium, molybdenum, nickel, and gold are formed.

接合材２や接合材８としては、はんだや、例えば銀を主成分とする焼結性フィラーやろう材、錫中に銅を分散した材料といった、熱伝導性が良く導電性の接合材料が適用できる。配線部材としてのボンディングワイヤ７の材質として、アルミニウム、銅、金、銀などがあげられる。配線部材としての主端子５は、大電流が流れることから導電性のよい金属が用いられる。中でも、銅材が電気抵抗、加工性やコストの点から最適である。   As the bonding material 2 and the bonding material 8, a conductive bonding material having good thermal conductivity, such as solder, a sinter filler or brazing material mainly composed of silver, or a material in which copper is dispersed in tin, is applied. it can. Examples of the material of the bonding wire 7 as the wiring member include aluminum, copper, gold, and silver. The main terminal 5 as the wiring member is made of a highly conductive metal because a large current flows. Of these, copper is the most suitable from the viewpoint of electrical resistance, workability and cost.

また、配線部材としての信号端子６は、主端子５のように大電流が流れることはない。したがって、導電性の金属材料であればよいが、主端子５と同様に銅材を使用することが可能である。銅材を使用する場合、第１のケース４と一体成型するため、第１のケース４成型時の３００℃前後の高温下で表面状態が変化しないことが必要である。そのため、銅材等を使用する場合は、３００℃の高温下では表面の酸化が激しく、酸化するとボンディングワイヤ７との接合が困難となる問題があり、酸化防止として表面にニッケルメッキを施す必要がある。   Further, the signal terminal 6 as a wiring member does not flow a large current unlike the main terminal 5. Accordingly, a conductive metal material may be used, but a copper material can be used similarly to the main terminal 5. When using a copper material, since it is integrally molded with the first case 4, it is necessary that the surface state does not change at a high temperature of about 300 ° C. when the first case 4 is molded. Therefore, when using a copper material or the like, there is a problem that the oxidation of the surface is severe at a high temperature of 300 ° C., and if it is oxidized, it becomes difficult to join the bonding wire 7. is there.

半導体素子基板３の表面電極３ｂおよび裏面電極３ｃとも、パターンが形成されていないべた状の導電性材料である。図２に、半導体素子基板３の上面図、すなわち表面電極３ｂ側から見た図を示す。図２に示すように、表面電極３ｂにはパターンが形成されておらず、周辺部以外は絶縁基板３ａが露出していない。半導体素子基板３のコア材となる絶縁基板３ａとしては、伝熱性に優れた窒化アルミニウム、窒化ケイ素、窒化ホウ素、酸化アルミニウム（アルミナ）などのセラミックス材料を用いることができる。表面電極３ｂおよび裏面電極３ｃは、銅、アルミニウムなどの導電性材料またはそれらを主成分とする合金材料からなり、ろう材などで絶縁基板３ａに対して接合されている。そして表面電極３ｂおよび裏面電極３ｃの表面には、酸化防止や接合材料の濡れ性を考慮して、ニッケルなどのめっき被膜が形成されている場合がある。表面電極３ｂと裏面電極３ｃとを絶縁基板３ａに対して対称に形成することで、半導体素子基板３の反りを抑制することができ、半導体素子１ａおよび１ｂの接合材２を用いての実装が容易となる。   Both the front surface electrode 3b and the back surface electrode 3c of the semiconductor element substrate 3 are solid conductive materials on which no pattern is formed. FIG. 2 shows a top view of the semiconductor element substrate 3, that is, a view seen from the surface electrode 3b side. As shown in FIG. 2, no pattern is formed on the surface electrode 3b, and the insulating substrate 3a is not exposed except in the periphery. As the insulating substrate 3a serving as the core material of the semiconductor element substrate 3, a ceramic material such as aluminum nitride, silicon nitride, boron nitride, and aluminum oxide (alumina) having excellent heat conductivity can be used. The front electrode 3b and the back electrode 3c are made of a conductive material such as copper or aluminum or an alloy material containing them as a main component, and are joined to the insulating substrate 3a with a brazing material or the like. A plating film such as nickel may be formed on the surfaces of the front electrode 3b and the back electrode 3c in consideration of oxidation prevention and wettability of the bonding material. By forming the front surface electrode 3b and the back surface electrode 3c symmetrically with respect to the insulating substrate 3a, the warp of the semiconductor element substrate 3 can be suppressed, and mounting of the semiconductor elements 1a and 1b using the bonding material 2 can be performed. It becomes easy.

第１のケース４は信号端子６と一体成型され、第１の封止樹脂９を注入する際に樹脂漏れを防止するために設ける。第１のケース４の材料としては、少なくとも第１の封止樹脂９の硬化温度や、半導体素子１ａ、１ｂが動作する際の半導体装置の温度以上の融点を有する樹脂材であれば良い。この条件を満足する材料として、通常ケースとして良く用いられるポリｐ−フェニレンサルファイド樹脂（ＰＰＳ）やポリブチレンテレフタレート樹脂（ＰＢＴ）、ナイロン樹脂、液晶ポリマー（ＬＣＰ）などがある。   The first case 4 is formed integrally with the signal terminal 6 and is provided to prevent resin leakage when the first sealing resin 9 is injected. The material of the first case 4 may be a resin material having a melting point equal to or higher than at least the curing temperature of the first sealing resin 9 and the temperature of the semiconductor device when the semiconductor elements 1a and 1b operate. Examples of materials that satisfy this condition include poly p-phenylene sulfide resin (PPS), polybutylene terephthalate resin (PBT), nylon resin, and liquid crystal polymer (LCP) that are often used as a case.

第１の封止樹脂９は、室温で液体の性状を示すエポキシ系などの熱硬化性樹脂に、溶融シリカなどのセラミックス粒子・繊維等のフィラーを混入し、硬化後の熱膨張係数や弾性率を調整した材料である。注入の際は、硬化反応が起こらない温度範囲で、加温して流動性を良くして注入することができる。第１の封止樹脂９の熱膨張係数を、半導体素子基板の熱膨張係数に近い熱膨張係数とすることで、界面に発生する応力を低減でき界面剥離や樹脂破断を防止でき、モジュールの信頼性を向上させることができる。絶縁基板３ａの熱膨張係数は、窒化アルミニウムが４．５ｐｐｍ／Ｋ、窒化ケイ素が３ｐｐｍ／Ｋ、酸化アルミニウムが７．３ｐｐｍ／Ｋであり、表面電極３ｂや裏面電極３ｃの熱膨張係数は、銅が１７ｐｐｍ／Ｋ、アルミニウムが２４ｐｐｍ／Ｋである。したがって、絶縁基板３ａと表面電極３ｂおよび裏面電極３ｃの厚み構成によるが、絶縁基板３ａに表面電極３ｂおよび裏面電極３ｃが接合された半導体素子基板３全体としての熱膨張係数は、７〜１５ｐｐｍ／Ｋとなる。したがって、第１の封止樹脂９のガラス転移温度以下の熱膨張係数も７〜１５ｐｐｍ／Ｋであることが望ましい。   The first sealing resin 9 is an epoxy-based thermosetting resin that exhibits liquid properties at room temperature, mixed with fillers such as ceramic particles and fibers such as fused silica, and has a thermal expansion coefficient and elastic modulus after curing. It is a material adjusted. At the time of injection, it can be injected in a temperature range in which a curing reaction does not occur with heating to improve fluidity. By making the thermal expansion coefficient of the first sealing resin 9 close to the thermal expansion coefficient of the semiconductor element substrate, it is possible to reduce the stress generated at the interface and prevent interface peeling and resin breakage, and the reliability of the module Can be improved. The thermal expansion coefficients of the insulating substrate 3a are 4.5 ppm / K for aluminum nitride, 3 ppm / K for silicon nitride, and 7.3 ppm / K for aluminum oxide. The thermal expansion coefficients of the front electrode 3b and the back electrode 3c are copper. Is 17 ppm / K, and aluminum is 24 ppm / K. Therefore, depending on the thickness configuration of the insulating substrate 3a, the front electrode 3b, and the back electrode 3c, the thermal expansion coefficient of the entire semiconductor element substrate 3 in which the front electrode 3b and the back electrode 3c are joined to the insulating substrate 3a is 7 to 15 ppm / K. Therefore, it is desirable that the thermal expansion coefficient of the first sealing resin 9 not higher than the glass transition temperature is also 7 to 15 ppm / K.

図３に、内部モジュール２０のうち、第１の封止樹脂９を取り除いた上面図を示す。第１のケース４が表面電極３ｂ上に形成されているため、第１のケース４内の半導体素子基板３には、絶縁基板３ａが露出している部分が無い。従って、第１のケース４内を第１の封止樹脂９で封止したとき、第１の封止樹脂９が絶縁基板３ａと接触する部分が無い。このため、第１の封止樹脂９を、半導体素子基板３全体としての熱膨張係数に近い熱膨張係数としておくことで、ヒートサイクルによる剥離が生じ難くなる。本発明の半導体装置に対し、例えば特許文献１の半導体装置では、表面電極にパターンが形成されており、封止樹脂とセラミックスが直接接する部分が存在するため、ヒートサイクルによりこの部分に剥離が生じる恐れがあった。   FIG. 3 shows a top view of the internal module 20 with the first sealing resin 9 removed. Since the first case 4 is formed on the surface electrode 3b, the semiconductor element substrate 3 in the first case 4 has no portion where the insulating substrate 3a is exposed. Therefore, when the inside of the first case 4 is sealed with the first sealing resin 9, there is no portion where the first sealing resin 9 contacts the insulating substrate 3a. For this reason, the 1st sealing resin 9 is made into the thermal expansion coefficient close | similar to the thermal expansion coefficient as the whole semiconductor element substrate 3, and it becomes difficult to produce peeling by a heat cycle. In contrast to the semiconductor device of the present invention, for example, in the semiconductor device of Patent Document 1, a pattern is formed on the surface electrode, and there is a portion where the sealing resin and the ceramic are in direct contact, and therefore this portion is peeled off by heat cycle. There was a fear.

また、例えば、特許文献１など従来の半導体装置では、半導体素子の大電流が流れる主電極と半導体装置外部との接続のための端子を、ケースに設け、この端子と主電極との間を表面電極のパターンを介してボンディングワイヤなどにより接続していた。一方、本発明の半導体装置の内部モジュール２０では、表面電極３ｂにパターンを形成していないため、半導体素子１ａや１ｂの大電流が流れる主電極と半導体装置外部との接続のための端子を、パターンを設けた表面電極を介さず、また第１のケース４に設けた端子とせず、表面電極３ｂから第１の封止樹脂９を貫通して直接引き出す第１の主端子５ａとして設けた。また、半導体素子１ａや１ｂのもう一方の主電極から外部に引き出すための端子も、表面電極を介さず、また第１のケース４に設けた端子とせず、第１の封止樹脂９を貫通して直接引き出す第２の主端子５ｂとして設けた。   Further, for example, in a conventional semiconductor device such as Patent Document 1, a terminal for connecting a main electrode through which a large current of a semiconductor element flows and the outside of the semiconductor device is provided in a case, and the surface between the terminal and the main electrode It was connected by a bonding wire or the like through an electrode pattern. On the other hand, in the internal module 20 of the semiconductor device of the present invention, since no pattern is formed on the surface electrode 3b, a terminal for connecting the main electrode through which a large current of the semiconductor elements 1a and 1b flows and the outside of the semiconductor device is provided. The first main terminal 5a was not drawn through the surface electrode provided with the pattern and was not used as the terminal provided in the first case 4 but directly pulled out from the surface electrode 3b through the first sealing resin 9. Further, a terminal for leading out from the other main electrode of the semiconductor element 1a or 1b is not provided with a surface electrode or a terminal provided in the first case 4, and penetrates the first sealing resin 9. And provided as the second main terminal 5b directly drawn out.

図４は、本発明の実施の形態１による半導体装置の全体構成を示す側面断面図である。図１に示した内部モジュール２０を複数、放熱板１０の上に配置し、放熱板１０の周辺部に設けた第２のケース１２の内部を第２の封止樹脂１３で封止する構造になっている。また、第１の封止樹脂９を貫通して第１の封止樹脂９の外部に取り出された第１の主端子５ａおよび第２の主端子５ｂは、第２の封止樹脂１３も貫通して第２の封止樹脂１３の外部に露出させる構成となっている。   FIG. 4 is a side sectional view showing the overall configuration of the semiconductor device according to the first embodiment of the present invention. A plurality of internal modules 20 shown in FIG. 1 are arranged on the heat sink 10 and the inside of the second case 12 provided in the periphery of the heat sink 10 is sealed with the second sealing resin 13. It has become. In addition, the first main terminal 5a and the second main terminal 5b that have been taken out of the first sealing resin 9 through the first sealing resin 9 also penetrated the second sealing resin 13. Thus, the second sealing resin 13 is exposed to the outside.

金属製の放熱板１０は、熱伝導性の良い金属材料、例えば銅の板材で構成されている。銅が主成分であれば良く、銅以外の金属を含有していても構わない。また、軽量で熱伝導性の高いアルミニウムまたはその合金でもよい。放熱板１０は接合材１１を介して半導体素子基板３の裏面電極３ｃと接合している。放熱板１０と裏面電極３ｃとの接合材は半導体素子１と表面電極３ｂとの接合材と同様に熱伝導性の良いはんだや、例えば銀を主成分とする焼結性フィラーやろう材を用いることもできる。さらに、熱伝導性の良い絶縁性の接着剤でも構わない。   The metal heat sink 10 is made of a metal material having good thermal conductivity, for example, a copper plate. It suffices if copper is a main component, and a metal other than copper may be contained. Also, aluminum or an alloy thereof having light weight and high thermal conductivity may be used. The heat sink 10 is bonded to the back electrode 3 c of the semiconductor element substrate 3 through the bonding material 11. As the bonding material between the heat radiating plate 10 and the back surface electrode 3c, a solder having a good thermal conductivity, for example, a sinterable filler or brazing material containing silver as a main component, is used similarly to the bonding material between the semiconductor element 1 and the front surface electrode 3b. You can also. Furthermore, an insulating adhesive having good thermal conductivity may be used.

第２のケース１２は、放熱板１０と接着剤等で固定されている。第２のケース１２は硬化前の第２の封止樹脂１３を注入する際に樹脂漏れを防止するために設けている。第２のケース１２の材料としては第１のケース４で説明した材料と同じものを用いることができる。第２の封止樹脂１３は、硬化後、第１の封止樹脂９よりも軟らかい、すなわち弾性率が小さい樹脂を用いる。したがって、第２の封止樹脂１３は、硬化前に室温で流動性を示す樹脂であれば良いが、大型のモジュール全体を封止するとともに、硬化後、発生応力が大きくならないよう、シリコーン系やウレタン系の軟らかい樹脂が良い。   The second case 12 is fixed to the heat sink 10 with an adhesive or the like. The second case 12 is provided to prevent resin leakage when the second sealing resin 13 before curing is injected. As the material of the second case 12, the same material as that described in the first case 4 can be used. The second sealing resin 13 uses a resin that is softer than the first sealing resin 9 after curing, that is, a resin having a low elastic modulus. Therefore, the second sealing resin 13 may be any resin that exhibits fluidity at room temperature before curing, but seals the entire large module and, after curing, does not increase the generated stress. Urethane soft resin is good.

以上説明したように、本発明の実施の形態１による半導体装置は、表面電極３ｂにパターンを形成せず、第１の封止樹脂９と半導体素子基板３の絶縁基板３ａが直接接する部分が無ため、第１の封止樹脂９が半導体素子基板３から剥離し難い。また、表面電極３ｂにパターンを形成していないため、表面電極３ｂに電気的に接続された第１の主端子５ａを第１の封止樹脂９および第２の封止樹脂１３を貫通して第２の封止樹脂１３の外部に露出させる構成にした。また、半導体素子１ａや１ｂの、表面電極３ｂに接合された側と反対側に形成された主電流を流すための主電極に電気的に接続された第２の主端子５ｂも第１の封止樹脂９および第２の封止樹脂１３を貫通して第２の封止樹脂１３の外部に露出させる構成にした。すなわち半導体素子１ａや１ｂに半導体装置外部から主電流を流すための主端子５を第１の封止樹脂９および第２の封止樹脂１３を貫通させて第２の封止樹脂１３の外部に露出させる構成とした。このように、主端子を従来のようにケースに設けず第２の封止樹脂１３から直接露出する構成としたので端子配置の自由度が増すというメリットがある。また、半導体素子基板３のうち、絶縁基板３ａと封止樹脂が接する部分は封止樹脂としては弾性率が小さい第２の封止樹脂１３となっているため、応力が低減され、この部分での剥離が抑制される。   As described above, the semiconductor device according to the first embodiment of the present invention does not form a pattern on the surface electrode 3b, and there is no portion where the first sealing resin 9 and the insulating substrate 3a of the semiconductor element substrate 3 are in direct contact. Therefore, the first sealing resin 9 is difficult to peel from the semiconductor element substrate 3. Further, since no pattern is formed on the surface electrode 3b, the first main terminal 5a electrically connected to the surface electrode 3b passes through the first sealing resin 9 and the second sealing resin 13. The second sealing resin 13 is exposed outside. The second main terminal 5b electrically connected to the main electrode for flowing the main current formed on the side opposite to the side joined to the surface electrode 3b of the semiconductor elements 1a and 1b is also the first seal. The structure is such that it passes through the stop resin 9 and the second sealing resin 13 and is exposed to the outside of the second sealing resin 13. That is, the main terminal 5 for allowing a main current to flow to the semiconductor elements 1a and 1b from the outside of the semiconductor device passes through the first sealing resin 9 and the second sealing resin 13 to the outside of the second sealing resin 13. It was set as the structure exposed. As described above, since the main terminal is not directly provided in the case as in the conventional case and is directly exposed from the second sealing resin 13, there is an advantage that the degree of freedom of terminal arrangement is increased. Further, in the semiconductor element substrate 3, the portion where the insulating substrate 3 a contacts the sealing resin is the second sealing resin 13 having a low elastic modulus as the sealing resin, so that the stress is reduced. Is prevented from peeling.

実施の形態２．
実施の形態２では、本実施の形態１による半導体装置１００の製造方法について、製造方法の工程を図示する図５および図６を参照して説明する。図５のＳＴ１に示すように、半導体素子基板３は半導体素子が配置される上面に表面電極３ｂを、下面にも裏面電極３ｃをパターン無で形成している。この半導体素子基板３の表面電極３ｂに半導体素子１ａおよび半導体素子１ｂを導電性の接合材２を用いて固定する。同時もしくはその後、スイッチング素子である半導体素子１ａと還流ダイオードである半導体素子１ｂの表面に形成された主電極と接続し外部電極となる第２の主端子５ｂと、表面電極３ｂから直接外部電
極を取り出す第１の主端子５ａを形成する。 Embodiment 2. FIG.
In the second embodiment, a method for manufacturing the semiconductor device 100 according to the first embodiment will be described with reference to FIGS. 5 and 6 illustrating the steps of the manufacturing method. As shown in ST1 of FIG. 5, the semiconductor element substrate 3 has a surface electrode 3b formed on the upper surface on which the semiconductor element is disposed and a back electrode 3c formed on the lower surface without a pattern. The semiconductor element 1 a and the semiconductor element 1 b are fixed to the surface electrode 3 b of the semiconductor element substrate 3 using the conductive bonding material 2. At the same time or thereafter, a second main terminal 5b that is connected to the main electrode formed on the surface of the semiconductor element 1a that is a switching element and a semiconductor element 1b that is a free-wheeling diode and serves as an external electrode, and an external electrode directly from the surface electrode 3b A first main terminal 5a to be taken out is formed.

次に、ＳＴ２に示すように、信号端子６が一体成型された第1のケース４を表面電極３ｂ上に接合する。接合には接着剤等を用いる。次に、ＳＴ３に示すように、半導体素子１ａと第1のケース４内にある信号端子６との間をボンディングワイヤ７で接続する。次に、ＳＴ４に示すように、エポキシ系からなる第１の封止樹脂９を形成するための硬化前の樹脂を第１のケース４の内部に注入する。この際、室温で流動性を示す硬化前の樹脂の注入作業を良くするために、樹脂の硬化反応が進行しない範囲で加温してもよい。樹脂の注入量は、第１のケース４を超えない範囲であればよい。第１の封止樹脂９を形成するための硬化前の樹脂を注入後に、加温することで樹脂の硬化を行う。ＳＴ４で内部モジュール２０が形成された。   Next, as shown in ST2, the first case 4 in which the signal terminal 6 is integrally molded is joined onto the surface electrode 3b. An adhesive or the like is used for bonding. Next, as shown in ST 3, the semiconductor element 1 a and the signal terminal 6 in the first case 4 are connected by the bonding wire 7. Next, as shown in ST4, a resin before curing for forming the first sealing resin 9 made of epoxy is injected into the first case 4. At this time, in order to improve the injection operation of the resin before curing that exhibits fluidity at room temperature, the resin may be heated in a range in which the resin curing reaction does not proceed. The injection amount of the resin may be in a range not exceeding the first case 4. The resin is cured by heating after injecting the uncured resin for forming the first sealing resin 9. In ST4, the internal module 20 was formed.

次に、図６に示すＳＴ５のように、ＳＴ４で形成した内部モジュール２０を複数個、放熱板１０の所定位置に、裏面電極３ｃの面と接合材１１を介して接合する。さらに、ＳＴ６に示すように、放熱板１０の外周部に第２のケース１２を接合する。接合には接着剤等を用いる。最後に、ＳＴ７に示すように、第２のケース１２の内部にシリコーン系やウレタン系からなる第１の封止樹脂９よりも軟らかい第２の各封止樹脂１３を形成する硬化前の樹脂を注入し、樹脂の硬化を行う。   Next, as in ST5 shown in FIG. 6, a plurality of internal modules 20 formed in ST4 are bonded to predetermined positions of the heat radiating plate 10 via the bonding material 11 and the surface of the back electrode 3c. Furthermore, as shown in ST6, the second case 12 is joined to the outer peripheral portion of the heat radiating plate 10. An adhesive or the like is used for bonding. Finally, as shown in ST7, a resin before curing that forms the second sealing resin 13 that is softer than the first sealing resin 9 made of silicone or urethane inside the second case 12 is used. Inject and cure the resin.

以上のようにして製造した半導体装置１００の動作について説明する。半導体装置１００を駆動させると、半導体素子１ａ、１ｂをはじめとする半導体装置１００内の様々な素子に電流が流れ、その際に電気抵抗成分やスイッチングによる電力ロスが熱に変換され発熱する。半導体素子１ａ、１ｂで発生した熱は半導体素子基板３を経由して、放熱板１０を介して外部に放熱されることになるが、半導体装置１００全体の温度も上昇する。このとき半導体素子１ａ、１ｂとして、ＳｉＣのような高温動作が可能な半導体材料の半導体素子を用いると、電流が大きく、動作時の温度は３００℃にまで達する。しかし、本発明による半導体装置１００では、半導体素子１や配線部材であるボンディングワイヤ７や主端子５等の回路部材を含む半導体素子基板の回路面側をエポキシ系からなる封止樹脂９により拘束し、しかも、第1の封止樹脂９の熱膨張係数を半導体素子基板の熱膨張係数に近くなるように調整しているので、半導体素子基板や回路部材に対する熱応力の発生を抑えることができる。   The operation of the semiconductor device 100 manufactured as described above will be described. When the semiconductor device 100 is driven, current flows through various elements in the semiconductor device 100 including the semiconductor elements 1a and 1b, and at that time, electric resistance components and power loss due to switching are converted into heat to generate heat. The heat generated in the semiconductor elements 1a and 1b is radiated to the outside via the semiconductor element substrate 3 and the heat radiating plate 10, but the temperature of the entire semiconductor device 100 also rises. At this time, when a semiconductor element made of a semiconductor material capable of high-temperature operation such as SiC is used as the semiconductor elements 1a and 1b, the current is large and the temperature during operation reaches 300 ° C. However, in the semiconductor device 100 according to the present invention, the circuit surface side of the semiconductor element substrate including circuit elements such as the semiconductor elements 1 and the wiring members 7 such as the bonding wires 7 and the main terminals 5 is restrained by the sealing resin 9 made of epoxy. In addition, since the thermal expansion coefficient of the first sealing resin 9 is adjusted to be close to the thermal expansion coefficient of the semiconductor element substrate, the generation of thermal stress on the semiconductor element substrate and circuit members can be suppressed.

半導体素子基板３の沿面の絶縁性の確保は、軟らかい第２の封止樹脂１３で行う。もし、エポキシ系の封止樹脂で覆った場合、半導体素子基板と銅やアルミニウムからなる放熱板１０とは熱膨張係数が異なることから、発生応力をエポキシ系の封止樹脂吸収できなく、剥離や樹脂クラックなどの問題を引き起こす。そこで、軟らかい第２の封止樹脂１３で応力低減を図る。   The insulation of the creeping surface of the semiconductor element substrate 3 is ensured by the soft second sealing resin 13. If it is covered with an epoxy-based sealing resin, the semiconductor element substrate and the heat sink 10 made of copper or aluminum have different coefficients of thermal expansion. Causes problems such as resin cracks. Therefore, the stress is reduced by the soft second sealing resin 13.

したがって、放熱特性に優れ、ヒートサイクル信頼性の高い半導体装置を得ることが可能となる。   Therefore, it is possible to obtain a semiconductor device having excellent heat dissipation characteristics and high heat cycle reliability.

実施の形態３．
本実施の形態３では、実施の形態２とは別の半導体装置の製造方法について、製造方法の工程を図示する図７を参照して説明する。ＳＴ１からＳＴ３までの工程は図５に示す実施の形態２と同様である。ＳＴ３の後、図７に示すＳＴ１１のように、第１の封止樹脂９による封止をしていない内部モジュール２１を複数個、放熱板１０に配置し、接合材１１により接合した後、ＳＴ１２に示すように、各内部モジュール２１の第１のケース４の内部を第１の封止樹脂９により封止する。ＳＴ１２の工程の後は、図６に示したＳＴ６およびＳＴ７の工程を実施する。このように、本実施の形態３は、実施の形態２におけるエポキシ系の第１の封止樹脂９の封止工程を、半導体素子基板を放熱板１０に接合した後に実
施するものである。接合材１１にて放熱板１０に半導体素子基板を接合する工程で、接合材２または接合材８として、半田材のように加熱すると再溶融する可能性がある。半田が再溶融すると体積膨張が大きく、高温下でエポキシ系の第１の封止樹脂９の強度低下もあって、樹脂割れが発生する。 Embodiment 3 FIG.
In the third embodiment, a method of manufacturing a semiconductor device different from that of the second embodiment will be described with reference to FIG. 7 illustrating the steps of the manufacturing method. The steps from ST1 to ST3 are the same as in the second embodiment shown in FIG. After ST3, as in ST11 shown in FIG. 7, a plurality of internal modules 21 not sealed with the first sealing resin 9 are arranged on the heat sink 10 and joined with the joining material 11, and then ST12. As shown in FIG. 2, the inside of the first case 4 of each internal module 21 is sealed with the first sealing resin 9. After the step ST12, the steps ST6 and ST7 shown in FIG. 6 are performed. As described above, in the third embodiment, the sealing step of the epoxy-based first sealing resin 9 in the second embodiment is performed after the semiconductor element substrate is joined to the heat sink 10. In the step of bonding the semiconductor element substrate to the heat radiating plate 10 with the bonding material 11, there is a possibility that the bonding material 2 or the bonding material 8 may be remelted when heated like a solder material. When the solder is re-melted, the volume expansion is large, and the strength of the epoxy-based first sealing resin 9 is reduced at a high temperature, causing a resin crack.

本実施の形態３によれば、接合材１１にて放熱板１０に半導体素子基板を接合する工程で、接合材２または接合材８が再溶融しても周囲が第１の封止樹脂９で覆われていないために樹脂割れの問題が解決される。   According to the third embodiment, in the step of bonding the semiconductor element substrate to the heat radiating plate 10 with the bonding material 11, even if the bonding material 2 or the bonding material 8 is remelted, the periphery is the first sealing resin 9. The problem of resin cracking is solved because it is not covered.

実施例．
図４の構造の半導体装置を実施の形態３で説明した製造工程により作製し、ヒートサイクル信頼性試験に投入した。まず、半導体装置１００の具体的な構成について説明する。 Example.
A semiconductor device having the structure shown in FIG. 4 was manufactured by the manufacturing process described in the third embodiment and put into a heat cycle reliability test. First, a specific configuration of the semiconductor device 100 will be described.

窒化ケイ素からなる絶縁基板３ａ（４０ｍｍ×２０ｍｍ、厚み０．３２ｍｍ）表面に０．５ｍｍ厚の銅製の表面電極３ｂおよび裏面電極３ｃを形成して半導体素子基板３とする。半導体素子１ａとして、１５ｍｍ×１５ｍｍ、厚み０．２５ｍｍのＩＧＢＴチップと、半導体素子１ｂとして、１５ｍｍ×１０ｍｍ、厚み０．２５ｍｍのダイオードチップ各１個を、半田接合材２を用いて、半導体素子基板３に接合する。銅製（ニッケルメッキなし）の主端子５ａおよび５ｂも半田接合材を用いて接合する。   A surface element 3b and a back electrode 3c made of copper having a thickness of 0.5 mm are formed on the surface of an insulating substrate 3a (40 mm × 20 mm, thickness 0.32 mm) made of silicon nitride to obtain a semiconductor element substrate 3. The semiconductor element 1a is a 15 mm × 15 mm IGBT chip having a thickness of 0.25 mm, and the semiconductor element 1b is a diode chip having a size of 15 mm × 10 mm and a thickness of 0.25 mm. 3 is joined. The main terminals 5a and 5b made of copper (without nickel plating) are also bonded using a solder bonding material.

銅にニッケルメッキを施した信号端子６を一体成型したＰＰＳ製の第１のケース４をシリコーン系の接着剤を用いて半導体素子基板３の表面電極３ｂ上に接合する。０．１５ｍｍ径のアルミニウムからなるボンディングワイヤ７で電気配線を行い、内部モジュール２１を作製する。   A first case 4 made of PPS, in which a signal terminal 6 in which nickel is plated on copper, is integrally formed, is bonded onto the surface electrode 3b of the semiconductor element substrate 3 using a silicone-based adhesive. Electrical wiring is performed with a bonding wire 7 made of aluminum having a diameter of 0.15 mm to produce an internal module 21.

その後、２個の上記内部モジュール２１を放熱板１０の所定位置に半田接合材１１を用いて接合する。室温で液状である硬化前のエポキシ系の第１の封止樹脂９を第１のケース４内に注入した後、第１の封止樹脂９の硬化を行う。   Thereafter, the two internal modules 21 are joined to predetermined positions of the heat sink 10 using the solder joint material 11. After injecting the epoxy-based first sealing resin 9 that is liquid at room temperature into the first case 4, the first sealing resin 9 is cured.

ＰＰＳからなる第２のケース１２を放熱板１０の周囲にシリコーン系接着剤を用いて固定し、シリコーン系の硬化前の第２の封止樹脂１３を注入する。シリコーン系の第２の封止樹脂１３は硬化後にゲル状の性状を示す。   A second case 12 made of PPS is fixed around the heat sink 10 using a silicone adhesive, and a second sealing resin 13 before silicone curing is injected. The silicone-based second sealing resin 13 exhibits a gel-like property after being cured.

さらに、実施の形態２および実施の形態３には記載していないが、第２のケース１２にＰＰＳ製の蓋を固定し、蓋から外部に露出している主端子５を曲げ加工して半導体装置１００を完成させる。   Further, although not described in the second embodiment and the third embodiment, a PPS lid is fixed to the second case 12, and the main terminal 5 exposed to the outside from the lid is bent and processed. The apparatus 100 is completed.

この半導体装置１００を−４０℃から１２５℃（各３０分間保持）のヒートサイクル信頼性試験に投入し、５００サイクル毎に取り出し、外観上の損傷、半導体素子の動作、半導体素子基板の絶縁試験（２．５ｋＶ、１分間印加）を実施して問題ないかを確認した。   This semiconductor device 100 is put into a heat cycle reliability test at -40 ° C. to 125 ° C. (held for 30 minutes each), taken out every 500 cycles, damaged in appearance, operation of the semiconductor element, insulation test of the semiconductor element substrate ( 2.5 kV, 1 minute application) was carried out to confirm whether there was any problem.

第１の封止樹脂は、ヒートサイクル信頼性を確保する上で、半導体素子や半導体素子基板に近い熱膨張係数にする必要があるために、接着性の優れたエポキシ系樹脂にフィラーを充填した材料とした。また、第２の封止樹脂は、絶縁を確保することと大容積を封止することから低応力性が要求されるため、第１の封止樹脂よりも弾性率が小さい、軟らかいシリコーン系の樹脂とした。図８に、充填するフィラーを調整することにより熱膨張係数および粘度（弾性率）が異なる６種類の第１の封止樹脂９を準備し、半導体装置１００を試作して信頼性試験を行った結果を示す。信頼性試験の目標として１０００サイクルとした場合、樹脂Ａから樹脂Ｄは目標を満足することになる。ここで、半導体素子基板の熱膨張係数は１０ｐｐｍ／Ｋであるので、半導体素子基板の熱膨張係数と第１の封止樹脂の熱
膨張係数の差が５ｐｐｍ／Ｋであれば目標を満足する。 In order to ensure heat cycle reliability, the first sealing resin needs to have a coefficient of thermal expansion close to that of a semiconductor element or a semiconductor element substrate. Therefore, an epoxy resin having excellent adhesion is filled with a filler. Material was used. In addition, since the second sealing resin is required to have low stress because it ensures insulation and seals a large volume, it is a soft silicone-based resin having a smaller elastic modulus than the first sealing resin. Resin was used. In FIG. 8, six kinds of first sealing resins 9 having different thermal expansion coefficients and viscosities (elastic moduli) are prepared by adjusting fillers to be filled, and a semiconductor device 100 is prototyped and subjected to a reliability test. Results are shown. When the reliability test target is 1000 cycles, the resin A to the resin D satisfy the target. Here, since the thermal expansion coefficient of the semiconductor element substrate is 10 ppm / K, the target is satisfied if the difference between the thermal expansion coefficient of the semiconductor element substrate and the thermal expansion coefficient of the first sealing resin is 5 ppm / K.

なお、本発明は、その発明の範囲内において、各実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、あるいはその構成要件を省略したりすることが可能である。   In the present invention, it is possible to freely combine the respective embodiments within the scope of the invention, to appropriately modify the respective embodiments, or to omit the constituent elements thereof.

１ａ、１ｂ 半導体素子、２、接合材、３ 半導体素子基板、３ａ 絶縁基板、３ｂ 表面電極、３ｃ 裏面電極、４ 第１のケース、５ 主端子、５ａ 第１の主端子、５ｂ 第２の主端子、６ 信号端子、８ 接合材、９ 第１の封止樹脂、１０ 放熱板、１１ 接合材、１２ 第２のケース、１３ 第２の封止樹脂 DESCRIPTION OF SYMBOLS 1a, 1b Semiconductor element 2, 2. Bonding material, 3 Semiconductor element substrate, 3a Insulating substrate, 3b Front surface electrode, 3c Back electrode, 4 1st case, 5 Main terminal, 5a 1st main terminal, 5b 2nd main Terminal, 6 Signal terminal, 8 Bonding material, 9 First sealing resin, 10 Heat sink, 11 Bonding material, 12 Second case, 13 Second sealing resin

Claims (5)

絶縁基板の片面に表面電極が、および前記絶縁基板の他の面に裏面電極が、それぞれ形成された半導体素子基板と、前記表面電極の、前記絶縁基板とは反対側の面に接合材を介して固着された半導体素子と、前記表面電極に接合された第１の主端子および前記半導体素子の前記表面電極とは反対側の面に接合された第２の主端子と、前記半導体素子基板の周辺部の前記表面電極上に設けられ、電気信号の入出力を行うための信号端子が一体成型された第１のケースと、前記第１のケースの内部を前記半導体素子と前記半導体素子基板とを覆うように封止する第１の封止樹脂とを備えた内部モジュールが、一面に複数、それぞれの前記内部モジュールの前記裏面電極を接合して配置された放熱板と、
前記放熱板の周辺部であって、前記内部モジュールを内側に含むように設けられた第２のケースと、
前記第２のケースの内部を、前記第１の封止樹脂と前記第１のケースと前記半導体素子基板とを覆うように封止する第２の封止樹脂と、を備えた半導体装置において、
少なくとも前記第１のケース内部の前記表面電極は、前記絶縁基板全体を被覆し、かつ前記表面電極と前記裏面電極とは、前記絶縁基板に対して対称に形成されており、
前記第１の主端子および前記第２の主端子は前記第１の封止樹脂および前記第２の封止樹脂を貫通して前記第２の封止樹脂の外部に露出するとともに、
前記第２の封止樹脂の弾性率が前記第１の封止樹脂の弾性率よりも小さいことを特徴とする半導体装置。 A semiconductor element substrate having a surface electrode on one side of the insulating substrate and a back electrode on the other side of the insulating substrate, and a surface of the surface electrode opposite to the insulating substrate via a bonding material The first main terminal bonded to the surface electrode, the second main terminal bonded to the surface of the semiconductor element opposite to the surface electrode, and the semiconductor element substrate. A first case provided on the surface electrode in the peripheral portion and integrally formed with signal terminals for inputting and outputting electrical signals, and the interior of the first case with the semiconductor element and the semiconductor element substrate A plurality of internal modules each including a first sealing resin that seals so as to cover the heat sink, the heat sink disposed by joining the back surface electrodes of the internal modules,
A second case provided at a peripheral portion of the heat dissipation plate so as to include the internal module inside;
In a semiconductor device comprising: a second sealing resin that seals the inside of the second case so as to cover the first sealing resin, the first case, and the semiconductor element substrate;
At least the surface electrode inside the first case covers the entire insulating substrate, and the surface electrode and the back electrode are formed symmetrically with respect to the insulating substrate,
The first main terminal and the second main terminal are exposed to the outside of the second sealing resin through the first sealing resin and the second sealing resin,
A semiconductor device, wherein an elastic modulus of the second sealing resin is smaller than an elastic modulus of the first sealing resin. 前記第１の封止樹脂はフィラーを混入したエポキシ系樹脂であり、前記第２の封止樹脂はシリコーン系樹脂であることを特徴とする請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the first sealing resin is an epoxy resin mixed with a filler, and the second sealing resin is a silicone resin. 前記第１の封止樹脂の熱膨張係数と、前記半導体素子基板の熱膨張係数との差が、５ｐｐｍ／Ｋ以下であることを特徴とする請求項１または２に記載の半導体装置。   The semiconductor device according to claim 1, wherein a difference between a thermal expansion coefficient of the first sealing resin and a thermal expansion coefficient of the semiconductor element substrate is 5 ppm / K or less. 前記半導体素子がワイドバンドギャップ半導体により形成されていることを特徴とする請求項１から３のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the semiconductor element is formed of a wide band gap semiconductor. 前記ワイドバンドギャップ半導体は、炭化ケイ素、窒化ガリウム系材料またはダイヤモンドの半導体であることを特徴とする請求項４に記載の半導体装置。   The semiconductor device according to claim 4, wherein the wide band gap semiconductor is a silicon carbide, a gallium nitride-based material, or a diamond semiconductor.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017028159A (en) * 2015-07-24 2017-02-02 富士電機株式会社 Semiconductor device and method of manufacturing the same
WO2018011853A1 (en) * 2016-07-11 2018-01-18 三菱電機株式会社 Semiconductor device
JP2019201113A (en) * 2018-05-16 2019-11-21 富士電機株式会社 Semiconductor device and method of manufacturing semiconductor device
DE112021004954T5 (en) 2021-02-03 2023-07-13 Hitachi Power Semiconductor Device, Ltd. POWER SEMICONDUCTOR DEVICE
JP7439653B2 (en) 2020-06-04 2024-02-28 三菱電機株式会社 Semiconductor devices and power conversion devices

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7280789B2 (en) 2019-09-24 2023-05-24 株式会社東芝 power module

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH062714U (en) * 1992-06-03 1994-01-14 株式会社三社電機製作所 Power semiconductor module
JP2004349300A (en) * 2003-05-20 2004-12-09 Toshiba Corp Semiconductor device and its manufacturing method
JP2012209470A (en) * 2011-03-30 2012-10-25 Mitsubishi Electric Corp Semiconductor device, semiconductor device module, and manufacturing method of the semiconductor device
WO2012144070A1 (en) * 2011-04-22 2012-10-26 三菱電機株式会社 Semiconductor device
WO2013111276A1 (en) * 2012-01-25 2013-08-01 三菱電機株式会社 Power semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH062714U (en) * 1992-06-03 1994-01-14 株式会社三社電機製作所 Power semiconductor module
JP2004349300A (en) * 2003-05-20 2004-12-09 Toshiba Corp Semiconductor device and its manufacturing method
JP2012209470A (en) * 2011-03-30 2012-10-25 Mitsubishi Electric Corp Semiconductor device, semiconductor device module, and manufacturing method of the semiconductor device
WO2012144070A1 (en) * 2011-04-22 2012-10-26 三菱電機株式会社 Semiconductor device
WO2013111276A1 (en) * 2012-01-25 2013-08-01 三菱電機株式会社 Power semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017028159A (en) * 2015-07-24 2017-02-02 富士電機株式会社 Semiconductor device and method of manufacturing the same
WO2018011853A1 (en) * 2016-07-11 2018-01-18 三菱電機株式会社 Semiconductor device
JPWO2018011853A1 (en) * 2016-07-11 2018-09-20 三菱電機株式会社 Semiconductor device
JP2019201113A (en) * 2018-05-16 2019-11-21 富士電機株式会社 Semiconductor device and method of manufacturing semiconductor device
JP7067255B2 (en) 2018-05-16 2022-05-16 富士電機株式会社 Semiconductor devices and methods for manufacturing semiconductor devices
JP7439653B2 (en) 2020-06-04 2024-02-28 三菱電機株式会社 Semiconductor devices and power conversion devices
DE112021004954T5 (en) 2021-02-03 2023-07-13 Hitachi Power Semiconductor Device, Ltd. POWER SEMICONDUCTOR DEVICE

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