JP2015170785A - Insulation substrate and electric power semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reliably handling a high temperature.SOLUTION: An insulation substrate 2 is formed of a ceramic base material 5 which has conductor layers 6 formed over both sides thereof, and one side of the conductor layers 6 (conductor layer 6a) is joined with an electric power semiconductor element 1. The base material 5 is a silicon nitride plate having a first thickness (thickness 5t). The conductor layers 6 on both sides are formed of a copper material having a second thickness (thickness 6t); a value (6t/5t) obtained by dividing the second thickness by the first thickness is 2.19-3.44.

Description

  The present invention relates to an insulating substrate for mounting a power semiconductor element and a power semiconductor device using the same.

  A power semiconductor device is a power circuit formed by using power semiconductor elements (chips), but as the size and capacity increase, the amount of heat generation increases and efficient heat dissipation is required. Yes. Therefore, an insulating substrate in which a copper or copper alloy conductor layer is formed on both surfaces of a ceramic material excellent in thermal conductivity has been used. In order to protect the power circuit, the circuit surface is sealed with a thermosetting resin such as an epoxy resin or a gel resin.

  For example, a gel-like resin such as silicone gel is very soft and easy to handle. However, because of the high permeability of oxygen and moisture, insulation reliability is improved due to insufficient heat resistance under high temperature environment, and bubbles are generated inside the gel and peeling occurs at the interface between the gel and the conductor layer due to the effect of oxidation of the conductor layer. There is a concern about the decline. On the other hand, for example, a thermosetting resin used as a mold resin has a high effect of preventing bubble generation and oxidation of the conductor layer in a high temperature environment, but has a higher elastic modulus than a gel resin. Therefore, there is a problem that peeling at the interface between the mold resin and the chip and the mold resin and the insulating substrate is likely to occur due to thermal stress.

  Therefore, in order to bring the apparent thermal expansion coefficient of the insulating substrate closer to the metal base plate, it has been proposed to increase the thickness of the circuit wiring pattern (conductor layer) formed on both surfaces of the insulating substrate (for example, Patent Document 1). reference.).

JP 2010-10505 A (paragraphs 0124 to 0144, FIGS. 15 to 19)

  However, in patent document 1, the thickness range of a ceramic material and the thickness range of a conductor layer are only prescribed | regulated separately, and the concrete parameter | index about the thermal expansion coefficient of an insulated substrate is not shown at all. Therefore, it has been difficult to effectively reduce thermal stress in power semiconductor devices using various members. In particular, a chip using silicon carbide (SiC), which is called a wide band gap semiconductor, which is expected to have high efficiency, has a higher elastic modulus than that of conventional silicon (Si), so that the generated thermal stress is increased. . Furthermore, since there is no polar group such as a hydroxyl group on the Si surface on the SiC surface, the adhesive strength with the mold resin is lowered, and the countermeasure against peeling becomes increasingly important.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a highly reliable power semiconductor device corresponding to a high temperature.

  An insulating substrate according to the present invention is an insulating substrate in which a conductor layer is formed on both surfaces of a ceramic base material, and a power semiconductor element is bonded to one of the two conductor layers. The linear expansion coefficient is adjusted to 8 ppm / K or more and 11 ppm / K or less.

  Alternatively, the insulating substrate according to the present invention is an insulating substrate in which a conductor layer is formed on both surfaces of a ceramic base material, and a power semiconductor element is joined to one of the two conductor layers. Is a silicon nitride plate having a first thickness, the conductor layers on both sides are each a copper material having a second thickness, and a value obtained by dividing the second thickness by the first thickness is 2.19 or more. 44 or less.

  According to the present invention, since the stress applied between the sealing body and the power semiconductor element and between the sealing body and the insulating substrate can be reduced, peeling at the interface between the sealing body and the power semiconductor element and the insulating substrate interface is prevented. Both can be prevented, and a highly reliable power semiconductor device corresponding to high temperatures can be obtained.

It is a cross-sectional schematic diagram for demonstrating the structure of the power semiconductor device concerning Embodiment 1 of this invention. It is a top view for demonstrating the structure of the insulated substrate concerning Embodiment 1 of this invention. It is a side view for demonstrating the measuring method of the linear expansion coefficient of the insulated substrate concerning Embodiment 1 of this invention. It is a cross-sectional schematic diagram for demonstrating the structure of the insulated substrate concerning Embodiment 2 of this invention. It is a cross-sectional schematic diagram for demonstrating the structure of the power semiconductor device concerning Embodiment 3 of this invention.

Embodiment 1 FIG.
1 to 3 are diagrams for explaining an insulating substrate and a power semiconductor device using the insulating substrate according to the first embodiment of the present invention, and FIG. 1 is a schematic cross-sectional view of the power semiconductor device. FIG. 2 is a plan view of the insulating substrate portion. FIG. 3 is a schematic side view illustrating a method of measuring a linear expansion coefficient as an insulating substrate that is a composite material, and shows a state when the insulating substrate is installed in a measuring device. Details will be described below.

  As shown in FIG. 1, the insulating substrate 2 according to the first embodiment of the present invention has conductor layers 6 a and 6 b (collectively conductor layers 6) formed on both surfaces of a ceramic base material 5 having excellent thermal conductivity. It is a thing. In the power semiconductor device 10 according to the first embodiment, the power semiconductor element 1 (the back electrode thereof) is formed on the conductor layer 6 a on one surface (circuit surface) of the insulating substrate 2 by the bonding layer 3. One end of the lead frame 4B is bonded to the main electrode on the front side of the power semiconductor element 1 by the bonding layer 3. In addition, one end portion of the lead frame 4A is joined to another portion of the conductor layer 6a by the joining layer 3. A control electrode (not shown) on the surface side of the power semiconductor element 1 is electrically connected to the outside by an aluminum wire bond (not shown).

  And it seals with sealing resin (sealing body 9) so that the whole circuit surface including power semiconductor element 1 may be wrapped in the state where the surface of conductor layer 6b on the other side of insulating substrate 2 is exposed. . At this time, the other end portions of the lead frames 4A and 4B (collectively, the lead frame 4) are exposed from the sealing body 9, and electrical connection between the power semiconductor element 1 and the external circuit becomes possible. In the following description, when simply describing mechanical properties, or when describing a plurality of specifications collectively, the power semiconductor device 10 is referred to as a “module”, the power semiconductor element 1 as a “chip”, and the insulating substrate 2 as “ Sometimes referred to as “substrate”.

  As shown in FIG. 2, the insulating substrate 2 uses a silicon nitride (SN) plate having an outer shape of 25 mm × 15 mm and a thickness of 0.32 mm as the base material 5, and the conductor layer 6 on both sides is 22 mm × 12 mm. A pattern of oxygen-free copper (C1020) having a thickness of 1.0 mm is formed. As the ceramic material to be the base material 5, SN, aluminum nitride (AlN), alumina, Zr-containing alumina can be used. In particular, AlN and SN are preferable from the viewpoint of thermal conductivity, and SN is more preferable from the viewpoint of material strength.

  The conductor layers 6a and 6b need to have the same thickness, but the areas are not necessarily the same. For example, if the ratio of the area of one conductor layer to the other conductor layer is in the range of 1 to 0.85, it is possible to suppress the occurrence of warpage or the like due to the difference in specifications in the thickness direction. In general, the area of the conductor layer 6a on the side where the chip is mounted is often narrower than the area of the other conductor layer 6b. For example, the area of the conductor layer 6a is 85% of the area of the conductor layer 6b. % To 100% or less. As a constituent material of the conductor layer 6, a metal excellent in electrical conduction and thermal conductivity, for example, aluminum and aluminum alloy, copper and copper alloy can be used. In particular, it is preferable to use copper from the viewpoints of heat conduction and electric conduction.

  The power semiconductor element 1 is an element for controlling electric power, and is also referred to as a power semiconductor element. Specifically, for example, a switching element such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor) or a rectifying element such as a freewheeling diode is used. As described in the background art, the power semiconductor element 1 is a wide bandgap semiconductor in which overcoming peel resistance is more important than conventional silicon in the first embodiment and the following embodiments. An example using some SiC will be described.

  In addition, as a material (semiconductor material) which comprises a wide band gap semiconductor, there exist a gallium nitride type material or diamond other than SiC, for example. When a wide band gap semiconductor is used, the allowable current density is high and the power loss is low, so that the device can be miniaturized. In this embodiment, a wide band gap semiconductor whose conditions are severe is shown as an example, but it goes without saying that the present invention can also be applied to a conventional silicon semiconductor.

  A power semiconductor element 1 having a chip thickness of 0.3 mm was used, but there is no particular limitation. However, it is preferable to adjust to the range of 0.1 to 0.4 mm. In order to reduce the chip thickness to less than 0.1 mm, a very hard SiC wafer is ground, which requires extra time and money. On the other hand, when it is thicker than 0.4 mm, there is a problem that the heat dissipation of the chip is lowered and the vertical direction of the module becomes thick. In other words, the chip thickness is selected in consideration of the influence on manufacturing or heat dissipation as a product, but it does not consider the temperature cycle resistance, and the configuration of the insulating substrate 2 is optimized as will be described later. By doing so, the reliability can be improved.

  Although an example in which solder is used is shown for the bonding layer 3 for bonding the chip and the insulating substrate 2 (strictly, the conductor layer 6), sintered silver or the like is applicable without being limited to solder. Since sintered silver has better thermal conductivity than solder, the heat dissipation of the chip is improved and the reliability is improved. Needless to say, all the bonding layers 3 need not be formed of the same bonding material and can be appropriately changed.

  The lead frame 4 is a copper lead frame having a thickness of 0.5 mm, for example, and is processed into a predetermined shape by etching and die punching.

  Next, in order to optimize the linear expansion coefficient of the insulating substrate 2 according to the first embodiment, the outer shapes of the base material 5 and the conductor layer 6 are constant with the above-described values, and the thickness t5 of the base material 5 and the conductor layer are determined. Various samples (examples) were prototyped using a thickness t6 (for one side) configuration of 6 as a parameter. And while measuring the linear expansion coefficient of the insulated substrate 2 single-piece | unit, it integrated in the module and implemented the temperature cycle test, and evaluated the presence or absence of peeling as temperature cycling resistance.

  The linear expansion coefficient of the insulating substrate 2 was measured using a thermomechanical analyzer TMA7100 (manufactured by Hitachi High-Tech SAIS). In order to measure the linear expansion coefficient in the plane direction of the substrate, in the sample for measuring the linear expansion coefficient, both ends of the substrate are cut so that the conductor layer 6 exists at both ends, and the outer shape is 20 mm × 10 mm. . Then, as shown in FIG. 3, one of the cut ends is brought into contact with the reference surface Fb of the analyzer and the other is brought into contact with the end surface Fp of the terminal, and the distance between the reference surface Fb and the end surface Fp at a temperature of 30 ° C. to 175 ° C. The linear expansion coefficient was calculated from the change in L2.

  On the other hand, the substrate for temperature cycle resistance evaluation is the one having the outer shape described in FIG. 2, and the chip and the lead frame 4 are soldered at predetermined positions as described in FIG. The circuit member thus formed is positioned and set in a mold using the lead frame 4 bonded to the chip and the substrate. And it mold-molded on condition of 180 degreeC-3 minutes with the sealing resin (linear expansion coefficient: 12 ppm / K) of the epoxy resin / phenol resin hardening | curing agent type | system | group filled with the silica particle with the transfer mold apparatus. Thereafter, the sealing resin was cured at 175 ° C. for 6 hours to produce an evaluation module.

  The presence or absence of peeling at the interface between the sealing resin (sealing body 9) and the substrate (insulating substrate 2) of the evaluation module and the interface between the sealing resin and the chip (power semiconductor element 1) is determined by an ultrasonic imaging device. Performed with FineSAT (manufactured by Hitachi Engineering & Service). The peeling observation was performed after 500 cycles of the initial stage and the temperature cycle test (-40 to 175 ° C .: 30 minutes each).

  Table 1 shows the specifications, measurement results, and evaluation results of each test sample (example) using the above-described thickness configuration as a parameter. In the table, Example 5 is the specification of the insulating substrate 2 used as the power semiconductor device 10 according to the first embodiment. Examples 1 to 12 differ only in the board specifications, and the other parts are modularized according to the same specifications (member configuration, manufacturing method). The linear expansion coefficient indicates an average value between 30 ° C. and 175 ° C., and in the result of the temperature cycle peeling determination, “○” indicates that no peeling is observed after the temperature cycle, and “×” indicates that peeling is observed. Show.

  As shown in Table 1, when the thickness t6 of the conductor layer is increased, peeling tends to occur at the interface between the sealing resin and the chip, and when the thickness t6 is decreased, peeling is likely to occur at the interface between the sealing resin and the substrate. It can be seen that there is an optimum region for the thickness t6 of the conductor layer 6. This is because the linear expansion coefficient of the SN plate constituting the substrate 5 is 3 ppm / K, and the linear expansion coefficient of copper constituting the conductor layer 6 is different from 16 ppm / K. Depending on the thickness ratio, the apparent linear expansion coefficient of the substrate varies. Therefore, when the ratio of the thickness t6 of the conductor layer 6 and the thickness t5 of the base material 5 is optimized and the linear expansion coefficient of the substrate is optimized, the interface between the sealing resin and the substrate, and the interface between the sealing resin and the chip In both cases, peeling can be prevented.

  From the results of Table 1, even if the thickness t5 of the base material 5 is different from 0.32 mm and 0.25 mm, peeling is prevented if the linear expansion coefficient of the substrate is in the range of 8 ppm / K or more and 11 ppm / K or less. I understand that I can do it. In addition, when the same evaluation was performed using the base material 5 which has thickness t5 other than shown in Table 1, the same result was obtained. In other words, it can be seen that no matter what thickness t5 SN plate is used for the base material 5, if the linear expansion coefficient of the substrate is adjusted to fall within the range of 8 ppm / K or more and 11 ppm / K or less, peeling can be prevented. It was.

  Furthermore, if the conductor layer 6 having the same thickness and material is formed on both surfaces, the conductor layer 6 and the base material 5 have different materials (linear expansion coefficient, elastic modulus) from the materials used in the evaluation of Table 1. Similar results could be obtained using the material. In other words, if the thickness configuration is adjusted so that the linear expansion coefficient of the substrate falls within the range of 8 to 11 ppm / K in any combination of materials, the interface between the sealing resin and the substrate, and the sealing resin and the chip It was found that peeling can be prevented at both of the interfaces.

On the other hand, when the relationship between the thickness t5 of the base material 5 using the SN plate and the thickness t6 of the conductor layer 6 using copper was examined, the ratio of t6 to t5 is expressed as 2.19 to It has been found that the linear expansion coefficient described above can be obtained by adjusting so as to fall within the range of 3.44.
2.19 ≤ t6 / t5 ≤ 3.44 (1)
Moreover, it turned out that the relationship of Formula (1) will be materialized if it is not only oxygen-free copper (C1020) shown in this Embodiment but the copper material used as a general wiring member.

  That is, the relationship shown in Formula (1) is an effective index for obtaining the above-described linear expansion coefficient when an SN plate is used for the substrate 5 and a copper material is used for the conductor layer 6. However, in order to maintain the above-described relationship, when the thickness t5 of the base material 5 is increased, the thickness t6 of the conductor layer 6 is also increased. As a result, since the total thickness of the substrate is increased, the thermal resistance increases and the workability also decreases. On the other hand, when the thickness t5 of the base material 5 is reduced, the withstand voltage is reduced and the strength of the substrate is lowered, and the substrate is cracked when the substrate is manufactured or when the module is assembled, and the manufacturing yield is reduced. From these viewpoints, it is desirable to adjust the thickness t5 of the base material 5 to a range of 0.2 mm or more and 0.4 mm or less.

Next, the influence of the coverage on the base material 5 of the conductor layer 6 in the substrate was evaluated. As samples for evaluation, samples with different dimensions (thickness 0.32 mm, outer shape 25 × 15) of the substrate 5 and conductor layer 6 and different outer shapes (coverage) of the conductor layer 6 were prepared. The coverage is defined as a value obtained by dividing the area (one side) of the conductor layer 6 by the area of the substrate 5. For example, with respect to outer shape 25 × 15 of the base member 5, when the outer shape of the conductive layer 6 is 22 × 12, 70% (0.704 : (22 × 12 = 264mm 2) / (25 × 15 = 375mm 2) ) The base material 5 is an SN plate, and the conductor layer 6 is formed of the oxygen-free copper described above.

  For the prepared substrates with different coverage ratios, modules were prepared in the same manner as the test using the thickness configuration as a parameter, and a temperature cycle test was performed to evaluate the presence or absence of peeling. In the test using the coverage as a parameter, whether or not the sealing resin was peeled off at the end portion of the base material 5 considered to be most affected by the coverage was used as a criterion. Table 2 shows the specifications and evaluation results of each test sample (example) using the above-described coverage as a parameter. In the table, Example 15 is the specification of the insulating substrate 2 used as the power semiconductor device 10 according to the first embodiment.

  As shown in Table 2, it can be seen that when the coverage of the conductor layer 6 is lowered, peeling is likely to occur at the interface between the sealing resin and the substrate at the end of the base material 5. When peeling occurs at the interface with the sealing resin at the end of the base material 5, a discharge or a short circuit occurs between the conductor layers 6 a-6 b on the front and back surfaces of the base material 5, and the insulation characteristics deteriorate and the reliability decreases. Therefore, this evaluation item is also important.

  The substrate portion where the conductor layer 6 and the base material 5 are bonded has an increased apparent linear expansion coefficient, a difference from the linear expansion coefficient with the sealing resin is decreased, and the thermal stress in the temperature cycle is decreased to cause peeling. Can be prevented. However, when the coverage of the conductor layer 6 is lowered, the end portion of the base material 5 is less affected by the conductor layer 6 on the thermal expansion, and exhibits a thermal expansion behavior almost similar to that of the SN plate alone. Furthermore, since the edge part of the base material 5 is the outermost periphery part of a board | substrate, it is a place where a thermal stress concentrates and peeling is easy to generate | occur | produce. Therefore, when the coverage of the conductor layer 6 is lowered, the difference between the linear expansion coefficient and the sealing resin at the end of the base material 5 is increased, and the thermal stress in the temperature cycle is increased to cause peeling.

  However, as is clear from this test, it has been found that if the coverage of the conductor layer is set to 62% or more, peeling at the interface between the end of the substrate 5 and the sealing resin can be prevented. In this test, the conductor layers 6a and 6b on both sides of the base material 5 have the same outer shape (coverage). However, as described above, the circuit surface side (conductor layer 6a) is generally used. This may be set so that the coverage is lower than the heat radiation surface side (conductor layer 6b). Thus, when the coverage of the conductor layers 6a and 6b is different, if the average coverage of both the conductor layers 6a and 6b is 62% or more, the end portion of the substrate 5 and the sealing resin Peeling at the interface can be prevented.

  In the first embodiment, as the sealing resin constituting the sealing body 9, an epoxy resin / phenolic resin curing agent resin, which is a matrix resin, filled with silica particles as a filler is used. An example is shown. In the sealing resin, an optimal amount of the silica particles to be filled is selected in consideration of a linear expansion coefficient of a member used for the module. For example, when the insulating substrate 2 having the linear expansion coefficient of 8 to 11 pp / K described above is used, the filling amount of the filler into the matrix resin is set so that the linear expansion coefficient of the sealing resin is 8 to 13 ppm / K. Is done. By doing in this way, the power semiconductor device 10 with a small thermal stress and without a curvature can be obtained. In addition, if the linear expansion coefficient of the sealing resin is within a range of 10 to 13 ppm / K, the peel resistance is further improved.

  As described above, according to the insulating substrate 2 according to the first embodiment of the present invention, the conductor layer 6 is formed on both surfaces of the ceramic base material 5, and one of the conductor layers 6 on both surfaces (for example, the conductor layer). 6a) is an insulating substrate 2 to which the power semiconductor element 1 is bonded, and the apparent linear expansion coefficient in the plane direction is adjusted to 8 ppm / K or more and 11 ppm / K or less. Thermal stress generated at the sealing resin and the interface between the substrate and the sealing resin is reduced, and peeling and cracking at the interface between the chip and the sealing resin and between the substrate and the sealing resin can be prevented. A highly reliable power semiconductor device 10 corresponding to the above can be obtained.

  Or according to the insulated substrate 2 concerning Embodiment 1 of this invention, the conductor layer 6 is formed in both surfaces of the ceramic base material 5, and one side (for example, conductor layer 6a) of the conductor layers 6 of both surfaces is formed. Insulating substrate 2 to which power semiconductor element 1 is bonded, base material 5 is a silicon nitride plate having a first thickness (thickness 5 t), and conductor layers 6 on both sides have a second thickness (thickness 6 t). Since the value obtained by dividing the second thickness by the first thickness (6t / 5t) is 2.19 or more and 3.44 or less, the chip and the sealing resin, and the substrate and the sealing Thermal stress generated at the interface with the stop resin is reduced, and peeling and cracking at the interface between the chip and the sealing resin, and at the interface between the substrate and the sealing resin can be prevented. The semiconductor device 10 can be obtained.

  If each of the conductor layers 6 on both sides (6a, 6b) is configured such that the average coverage of covering the base material 5 is 62% or more, at the interface between the end of the base material 5 and the sealing resin. Can be prevented from peeling.

  Further, according to the power semiconductor device 10 according to the first embodiment, the above-described insulating substrate 2, the power semiconductor element 1 bonded to one surface (conductor layer 6a) of the insulating substrate 2, and the power And a sealing body 9 that seals the circuit member including the semiconductor element 1. Therefore, peeling and cracking at the interface between the chip and the sealing resin and at the interface between the substrate and the sealing resin can be prevented. A highly reliable power semiconductor device 10 corresponding to the above can be obtained.

Embodiment 2. FIG.
In the insulating substrate according to the first embodiment and the power semiconductor device using the same, an example in which a single conductor layer is formed on both surfaces of a base material has been described. The insulating substrate according to the second embodiment uses a two-layered conductor layer. FIG. 4 is a schematic cross-sectional view for explaining the configuration of the insulating substrate according to the second embodiment of the present invention. In the figure, the same components as those in the first embodiment are denoted by the same reference numerals and detailed description thereof is omitted. The members other than the insulating substrate are the same as those in the first embodiment, and the power semiconductor device according to the second embodiment or the method for measuring the linear expansion coefficient is duplicated with the aid of FIGS. The description to be omitted is omitted.

  As shown in FIG. 4, in the insulating substrate 2 according to the second embodiment of the present invention, the conductor layers 6a and 6b formed on both surfaces of the base 5 are made of copper copper patterns 61a and 61b (collectively copper patterns 61a and 61b). The pattern 61) has a two-layer structure constituted by aluminum buffer layers 62a and 62b (collectively the buffer layer 62) interposed between the base material 5 and the copper pattern 61. Since the buffer layer 62 interposed between the ceramic (SN plate) base material 5 and the copper pattern 61 has a lower elastic modulus (softer) than copper, it exhibits a stress relaxation effect. Therefore, by providing the buffer layer 62, the stress between the base material 5 and the copper pattern 61 in the temperature cycle can be relieved, the peeling of the copper pattern 61 from the base material 5 can be prevented, and the reliability is improved.

  Next, as shown in Embodiment 1, the influence of the thickness of the copper pattern 61 on the performance was evaluated. As the sample for evaluation, the dimensions of the base material 5 (thickness 0.32 mm, outer shape 25 × 15), and the conductor layer 6 are the outer shape (the copper pattern 61 and the buffer layer 62 are the same: 21 × 11) and the buffer layer 62. The thickness t62 (0.5 mm) of the copper pattern 61 was made constant and the thickness t61 of the copper pattern 61 was different. Then, similarly to the test using the thickness configuration in the first embodiment as a parameter, a sample for measuring a linear expansion coefficient and a module for a peel resistance test in a temperature cycle were manufactured.

  Table 3 shows the specifications, measurement results, and evaluation results of each test sample (example) using the thickness t61 of the copper pattern 61 as a parameter on the substrate on which the buffer layer 62 is formed.

  As shown in Table 3, even when the buffer layer 62 is interposed between the copper pattern 61 and the base material 5, peeling can be prevented if the linear expansion coefficient of the substrate is in the range of 8 to 11 ppm / K or less. I understand. In Table 3, the case where the thickness t5 of the base material 5 is 0.32 mm and the thickness t62 of the buffer layer 62 is 0.5 mm is shown, but the linear expansion coefficient as the base material is also described in the other thickness configurations. If it can be adjusted within the range, the same effect can be obtained.

  When the thickness t62 of the buffer layer 62 was tested as a parameter, when the thickness t62 of the buffer layer 62 was reduced, the stress relaxation effect between the base material 5 and the copper pattern 62 was reduced, and the thickness t62 was set to 0.2 mm or more. It is preferable. On the other hand, it was found that when the thickness t62 of the buffer layer 62 is increased, the thickness t61 of the copper pattern 61 required to obtain the linear expansion coefficient in the above-described range increases. That is, if the thickness t62 of the buffer layer 62 is increased, it is necessary to increase the thickness of the copper pattern 62, the thermal resistance is increased, and the workability is also decreased. From these viewpoints, it was found that the thickness t62 of the buffer layer 62 is preferably in the range of 0.2 mm or more and 0.8 mm or less.

  In addition, even if it is the conductor layer 6 which provided the buffer layer 62, peeling at the interface of the edge part of the base material 5 and sealing resin is prevented by making the coverage with respect to a base material 62% or more. Can do.

  As described above, according to the insulating substrate 2 according to the second embodiment, each of the conductor layers 6 on both sides includes the first layer (copper pattern 61) formed of the first member (copper) and the first layer. Consists of a second layer (buffer layer 62) formed by a second member (Al) having a lower elastic modulus than the first member (copper), interposed between the layer (copper pattern 61) and the substrate 5 Therefore, the stress between the base material 5 and the copper pattern 61 in the temperature cycle can be relieved, and the peeling of the copper pattern 61 from the base material 5 can be prevented, thereby improving the reliability.

  Further, according to the power semiconductor device 10 according to the second embodiment, the insulating substrate 2 on which the conductor layer 6 having the buffer layer 62 is formed and bonded to one surface of the insulating substrate 2 (conductor layer 6a). Since the power semiconductor element 1 and the sealing body 9 for sealing the circuit member including the power semiconductor element 1 are provided, the interface between the chip and the sealing resin, and the interface between the substrate and the sealing resin Peeling and cracking can be prevented, and a highly reliable power semiconductor device 10 corresponding to high temperatures can be obtained.

Embodiment 3 FIG.
In the first or second embodiment, the sealing body is formed by molding using a molding die, such as transfer molding, and the sealing body also serves as a module housing. However, in the power semiconductor device according to the third embodiment, a case serving as a housing is separately manufactured, and a liquid resin material before curing is injected into the case to form a sealing body. is there. As the insulating substrate, the one described in the first or second embodiment is used. FIG. 5 is a schematic cross-sectional view for explaining the configuration of the power semiconductor device according to the third embodiment of the present invention. In the figure, the same components as those in the first or second embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIG. 5, the power semiconductor device 10 according to the third embodiment of the present invention joins the case 8 to the insulating substrate 2 with a silicone rubber adhesive (not shown) to enclose the circuit member. A container is formed, and a liquid resin material is injected into the container and sealed. Since the resin sealing is performed without using a mold, the lead frame 4 can be extended, and the module width can be narrowed. Therefore, the power semiconductor device 10 can be downsized.

  As the liquid resin material, a two-pack type epoxy resin / acid anhydride curing agent type liquid sealing resin (linear expansion coefficient: 13 ppm / K) filled with silica particles was used, and a vacuum injection device was used. Specifically, the two liquids degassed under reduced pressure were mixed with a mixer, and sealing was performed by injecting a predetermined amount of liquid sealing resin into the case 8 (the space formed by the substrate) in the vacuum chamber. (The sealing body 9 was formed). Thereafter, the sealing resin was cured under conditions of 100 ° C.-1 hr, and further 150 ° C.-2 hr, and the power semiconductor device 10 was manufactured.

  In order to evaluate the temperature cycle resistance when a module was formed using such a sealing body 9, an evaluation test was performed using the thickness configuration in the first embodiment as a parameter. Table 4 shows the specifications and evaluation results.

  As shown in Table 4, the ratio of the thickness t6 of the conductor layer 6 to the thickness t5 of the base material 5 (t6 / t5), and the temperature cycle peeling determination result with respect to the linear expansion coefficient of the substrate are the same results as in the first embodiment. was gotten. That is, even if a module is formed with the sealing body 9 using a liquid sealing resin, by adjusting the linear expansion coefficient of the substrate to a range of 8 to 11 ppm / K, the interface between the sealing resin and the chip, Further, it is possible to prevent peeling on both the sealing resin and the substrate surface, and to obtain the power semiconductor device 10 having high heat resistance and high reliability. Alternatively, when an SN plate is used for the substrate 5 and copper is used for the conductor layer 6, the thickness ratio (t6 / t5) between the substrate 5 and the conductor layer 6 (per one side) is adjusted to a range of 2.19 to 3.44. By doing so, peeling can be prevented both at the interface between the sealing resin and the chip and at the surface between the sealing resin and the substrate, and the power semiconductor device 10 having high heat resistance and high reliability can be obtained.

  Even when the sealing body 9 is formed by injecting a liquid sealing resin, by setting the coverage to the base material to 62% or more, at the interface between the end portion of the base material 5 and the sealing resin. Peeling can be prevented.

  Moreover, if the filling amount of the filler is adjusted so that the linear expansion coefficient of the sealing resin is within the range of 8 to 13 ppm / K, the power semiconductor device 10 with small thermal stress and no warpage can be obtained. Furthermore, if the linear expansion coefficient of the sealing resin is within the range of 10 to 13 ppm / K, the peel resistance is further improved.

  As described above, according to the power semiconductor device 10 of the third embodiment, the case 8 serving as the outer frame of the module is provided, and the sealing body 9 includes the liquid resin before curing in the case 8. Even if it is formed by injection, as long as the specification of the insulating substrate 2 is adjusted, the interface between the sealing resin and the chip, and the sealing resin Separation can be prevented both on the surface with the substrate, and the power semiconductor device 10 having high heat resistance and high reliability can be obtained.

  In the first to third embodiments, it is assumed that SiC, which is a wide bandgap semiconductor material, is applied to the power semiconductor element 1, but generally used silicon may be used. Needless to say, it is good. However, when using silicon carbide that can form a so-called wide gap semiconductor with a large band gap, gallium nitride-based material or diamond or gallium oxide-based material, high withstand voltage and high temperature resistant operation are required. The effect of the present invention is noticeable. In particular, since the SiC chip has low adhesiveness with the sealing resin, the effect of the present invention can be further exhibited. That is, by exhibiting the effect of the present invention, the characteristics of the wide band gap semiconductor can be utilized.

1: power semiconductor element, 2: insulating substrate, 3: bonding layer, 4: lead frame, 5: base material, 6: conductor layer, 8: case, 9: sealing body, 10: power semiconductor device, 61 : Copper pattern (first layer), 62: Buffer layer (second layer),
t5: thickness of substrate (first thickness), t6: thickness of conductor layer (each) (second thickness).

Claims (9)

A conductive layer is formed on both surfaces of a ceramic base material, and an insulating substrate to which a power semiconductor element is bonded to one of the conductive layers on both surfaces,
An insulating substrate, wherein an apparent linear expansion coefficient in a planar direction is adjusted to 8 ppm / K or more and 11 ppm / K or less.   Each of the conductor layers on both sides is formed by a first layer formed of a first member, a second member interposed between the first layer and the base material, and having a lower elastic modulus than the first member. The insulating substrate according to claim 1, comprising the formed second layer.   The insulating substrate according to claim 2, wherein the first member is copper and the second member is aluminum. A conductive layer is formed on both surfaces of a ceramic base material, and an insulating substrate to which a power semiconductor element is bonded to one of the conductive layers on both surfaces,
The substrate is a silicon nitride plate having a first thickness;
Each of the conductive layers on both sides is a copper material having a second thickness,
A value obtained by dividing the second thickness by the first thickness is 2.19 or more and 3.44 or less.   5. The insulating substrate according to claim 1, wherein an average value of a covering ratio of each of the conductor layers on both surfaces covering the base material is 62% or more. An insulating substrate according to any one of claims 1 to 5,
A power semiconductor element bonded to one surface of the insulating substrate;
A sealing body for sealing a circuit member including the power semiconductor element;
A power semiconductor device comprising:   The power semiconductor device according to claim 6, wherein the sealing body has a linear expansion coefficient of 8 ppm / K or more and 13 ppm / K or less.   The power semiconductor device according to claim 6 or 7, wherein the power semiconductor element is formed of a wide band gap semiconductor material.   9. The power semiconductor device according to claim 8, wherein the wide band gap semiconductor material is any one of silicon carbide, a gallium nitride-based material, and diamond.

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