JP2010283169A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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Publication number
JP2010283169A
JP2010283169A JP2009135500A JP2009135500A JP2010283169A JP 2010283169 A JP2010283169 A JP 2010283169A JP 2009135500 A JP2009135500 A JP 2009135500A JP 2009135500 A JP2009135500 A JP 2009135500A JP 2010283169 A JP2010283169 A JP 2010283169A
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Prior art keywords
solder
circuit board
lead
semiconductor device
manufacturing
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Inventor
Norito Takayanagi
教人 高柳
Masami Ogura
正巳 小倉
Tsukasa Aiba
司 合葉
Tomoko Yamada
友子 山田
Jun Kato
潤 加藤
Tsugio Masuda
次男 増田
Fumiaki Takano
文明 高野
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Honda Motor Co Ltd
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Honda Motor Co Ltd
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Priority to JP2009135500A priority Critical patent/JP2010283169A/en
Priority to EP10164743.6A priority patent/EP2265099B1/en
Priority to KR1020100052203A priority patent/KR20100130960A/en
Priority to CN201010198571.2A priority patent/CN101908521B/en
Priority to US12/794,012 priority patent/US8415801B2/en
Publication of JP2010283169A publication Critical patent/JP2010283169A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device that is more inexpensive than before with conventional normal general module constitution, and secures bonding reliability of a solder bonding part. <P>SOLUTION: This invention relates to the method of manufacturing the semiconductor device, including: a circuit board P formed by bonding metal plates to both surfaces of an insulating substrate; one semiconductor element bonded to an external surface of one metal plate through first solder; and a base plate for heat dissipation, bonded to an external surface of the other metal plate through second solder. The method includes steps of: manufacturing the circuit board P in such a way that the ratio (a) of the sum t<SB>M</SB>of plate thicknesses of both metal plates M1, M2 to the plate thickness t<SB>C</SB>of the insulating substrate C falls within a predetermined range for securing durability of solder H1 and solder H2 which are lead-free solder of the same kind, to temperature stress; and carrying out, under an identical heating condition, processing for bonding the semiconductors S, S' to the external surface of one metal plate M1 of the circuit board P through the first solder H1 concurrently with processing for bonding the base plate B to the external surface of the other metal plate M2 through the second solder H2. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、絶縁基板の両面に金属板を各々接合してなる回路基板と、一方の金属板の外面に第1はんだを介して接合される少なくとも1個の半導体素子と、他方の金属板の外面に第2はんだを介して接合される放熱用ベース板とを備えた半導体装置の製造方法に関する。   The present invention provides a circuit board formed by bonding metal plates to both surfaces of an insulating substrate, at least one semiconductor element bonded to the outer surface of one metal plate via a first solder, and the other metal plate. The present invention relates to a method of manufacturing a semiconductor device including a heat dissipation base plate joined to an outer surface via a second solder.

上記半導体装置、例えばモータ駆動制御システム等に用いられるパワーモジュールは、高出力化に伴い十分な絶縁性と放熱性が要求されるため、セラミック製の絶縁基板を用いてその一面に接合した第1銅板にパワー半導体素子を溶融温度の高い鉛系はんだで接合し、次いで絶縁基板の他面に接合した第2銅板に、前記鉛系はんだの接合部を再溶融させないよう溶融温度が比較的低い錫鉛系共晶はんだで放熱用ベース板を接合している。   The power module used in the semiconductor device, such as a motor drive control system, requires sufficient insulation and heat dissipation as the output increases. Therefore, the first is bonded to one surface using a ceramic insulating substrate. Tin having a relatively low melting temperature so as not to remelt the lead-based solder joint to the second copper plate joined to the copper plate with a lead-type solder having a high melting temperature and then joined to the other surface of the insulating substrate. The base plate for heat dissipation is joined with lead eutectic solder.

一方、近年は環境保護のために、はんだ材の鉛フリー化が進められているが、 その鉛フリーはんだは、その溶融温度が錫鉛系共晶はんだの溶融温度より高いものの、鉛系はんだの溶融温度より低いため、この鉛フリーはんだを用いて上記した従来の手法ではんだ接合を行うと、先に接合した半導体素子側のはんだ接合部が、放熱用ベース板の接合処理時にその熱で再溶融して接合信頼性を著しく低下させるといった問題があった。   On the other hand, in recent years, lead-free solder materials have been promoted to protect the environment, but the lead-free solder has a melting temperature higher than that of tin-lead eutectic solder. Since the soldering temperature is lower than the melting temperature, when solder bonding is performed with the above-described conventional method using this lead-free solder, the solder bonding portion on the semiconductor element side that has been bonded first is reheated by the heat during the bonding process of the base plate for heat dissipation. There has been a problem that the bonding reliability is remarkably lowered by melting.

また鉛フリーはんだは、鉛系や錫鉛系のはんだと比べて硬いため、亀裂が一旦、発生するとその進展が早く、耐久性に劣るといった問題があった。   Further, since lead-free solder is harder than lead-based or tin-lead-based solder, there is a problem that once a crack occurs, the progress is rapid and the durability is inferior.

そこで前者の問題を解決するために、半導体素子と放熱用ベース板を、溶融温度が相異なる二種の鉛フリーはんだを用いて接合する手法(例えば、特許文献1を参照)や、後者の問題を解決するために、鉛フリーはんだにビスマスやインジウム等のレアメタルを添加して耐久性を高める手法(例えば、下記特許文献2を参照)が知られている。さらにパワーモジュールの構造を大幅に変更し、はんだ接合部等をモールド樹脂で固めて樹脂封止するといった特殊な手法も知られている。   Therefore, in order to solve the former problem, a method of joining the semiconductor element and the heat radiating base plate using two kinds of lead-free solders having different melting temperatures (for example, refer to Patent Document 1) or the latter problem. In order to solve this problem, a technique is known in which a rare metal such as bismuth or indium is added to lead-free solder to increase durability (for example, see Patent Document 2 below). Furthermore, a special technique is known in which the structure of the power module is significantly changed, and the solder joints are hardened with a mold resin and sealed with resin.

特開2006−237057号公報JP 2006-237057 A 特開2007−141948号公報JP 2007-141948 A

ところが、上記特許文献1の手法では、溶融温度が相異なる二種の鉛フリーはんだを特別に選定、用意する必要がある上、その二種のはんだを、絶縁基板への半導体素子の接合と放熱用ベース板の接合とで使い分ける必要があり、その取り扱いが全体として煩雑であり、また上記特許文献2の手法では、高価なレアメタルを鉛フリーはんだへの添加材として特別に用いる必要があり、結局、何れの手法でも、材料費や管理費の高騰、更には製造工程の変更を強いられ、大幅なコスト増となる問題がある。   However, in the method of Patent Document 1, it is necessary to specially select and prepare two kinds of lead-free solders having different melting temperatures, and the two kinds of solders are used for joining a semiconductor element to an insulating substrate and dissipating heat. It is necessary to use differently for the base plate joining, and the handling thereof is complicated as a whole, and in the method of Patent Document 2 above, it is necessary to specially use an expensive rare metal as an additive to lead-free solder. In either method, there is a problem that the material cost and the management cost are soaring and the manufacturing process is forced to change, resulting in a significant increase in cost.

本発明は、かかる事情に鑑みてなされたものであり、従来普通の一般的なモジュール構成で、従来よりも安価で且つはんだ接合部の接合信頼性が確保可能な半導体装置の製造方法を提供することを目的とする。   The present invention has been made in view of such circumstances, and provides a method of manufacturing a semiconductor device that has a conventional and ordinary general module configuration, is cheaper than the conventional one, and can ensure the bonding reliability of the solder joint portion. For the purpose.

上記目的を達成するために、本発明は、一方の金属板の外面に第1はんだを介して接合される少なくとも1個の半導体素子と、他方の金属板の外面に第2はんだを介して接合される放熱用ベース板とを備えた半導体装置の製造方法において、
前記一方及び前記他方の金属板の板厚の和の、前記絶縁基板の板厚に対する比が、各はんだの温度ストレスに対する耐久性を確保し得る所定範囲に収まるようにして、前記回路基板を製造する工程と、前記回路基板の前記一方の金属板の外面に第1はんだを介して前記半導体を接合する処理と前記他方の金属板の外面に前記第2はんだを介して前記ベース板を接合する処理とを同一の加熱条件で同時に実行する工程とを含み、前記第1,第2はんだが、同種の鉛フリーはんだ材で構成されることを第1の特徴とする。
In order to achieve the above object, the present invention provides at least one semiconductor element bonded to the outer surface of one metal plate via a first solder and bonded to the outer surface of the other metal plate via a second solder. In a method for manufacturing a semiconductor device provided with a heat dissipation base plate,
The circuit board is manufactured such that the ratio of the sum of the thicknesses of the one and the other metal plates to the thickness of the insulating substrate is within a predetermined range that can ensure durability against temperature stress of each solder. A step of bonding the semiconductor to the outer surface of the one metal plate of the circuit board via a first solder, and bonding the base plate to the outer surface of the other metal plate via the second solder. A first feature is that the first and second solders are made of the same kind of lead-free solder material.

また本発明は、第1の特徴の構成に加えて、前記比が、1.5以上で且つ5.5以下であることを第2の特徴とする。   In addition to the configuration of the first feature, the present invention has a second feature that the ratio is 1.5 or more and 5.5 or less.

また本発明は、第1又は第2の特徴の構成に加えて、前記第1,第2はんだが、SnCu系、SnAg系またはSnAgCu系の合金であって、レアメタルを含まないことを第3の特徴とする。   According to the third aspect of the present invention, in addition to the first or second feature, the third and second solders are SnCu-based, SnAg-based, or SnAgCu-based alloys, and do not include a rare metal. Features.

本発明は、第1〜第3の特徴の構成のいずれかに加えて、前記処理が、リフロー炉内で行われ、その時のリフロー温度は、240°C以上で且つ320°C以下に設定されることを第4の特徴とする。   In the present invention, in addition to any of the configurations of the first to third features, the treatment is performed in a reflow furnace, and the reflow temperature at that time is set to 240 ° C. or more and 320 ° C. or less. This is the fourth feature.

本発明において、「同種の鉛フリーはんだ材」とは、主要成分が同一の合金よりなる鉛フリーはんだ材をいい、例えばSnCu系、SnAg系またはSnAgCu系の合金より選ばれる鉛フリーはんだ材が用いられる。そして、本発明の「同種の鉛フリーはんだ材」には、添加物が含まれても、含まれなくてもよいが、含まれる場合には、その含まれる添加物の組成や添加量が第1,第2はんだで同一であっても或いは異なっていてもよい。何れにせよ、第1,第2はんだの融点の差が20°C以内(即ち特許文献1(特開2006−237057)のように加熱条件を変える必要がない範囲)に収まるように第1,第2はんだの添加物の組成や添加量が選択されることが望ましい。   In the present invention, “the same kind of lead-free solder material” refers to a lead-free solder material composed of an alloy having the same main component. For example, a lead-free solder material selected from SnCu-based, SnAg-based or SnAgCu-based alloys is used. It is done. The “same kind of lead-free solder material” of the present invention may or may not contain an additive, but if included, the composition and amount of the additive contained in the The first and second solders may be the same or different. In any case, the first and second solders have a melting point difference within 20 ° C. (that is, a range in which heating conditions do not need to be changed as in Patent Document 1 (Japanese Patent Application Laid-Open No. 2006-237057)). It is desirable to select the composition and amount of the additive for the second solder.

本発明の第1,第2の各特徴によれば、半導体装置における回路基板両面の第1,第2金属板と素子、放熱用ベース板との間をそれぞれ接合するはんだ接合部の耐久信頼性を、樹脂封止等の特殊な手法を採ることなく、且つレアメタル等の高価な添加材を添加した特殊なはんだ材料を使用することなく、十分に確保可能となる。しかもその両はんだ接合部に同種のはんだを用いて一括で接合処理することが可能となるから、接合処理作業を簡単且つ迅速に能率よく行うことができる。従って、その両はんだ接合部に同種の鉛フリーはんだを用いても、それらの接合部の耐久信頼性を確保しながら、材料費低減や工程削減によるコストダウンを達成することができる。   According to the first and second features of the present invention, the durability reliability of the solder joint portion for joining the first and second metal plates on both sides of the circuit board in the semiconductor device to the element and the heat radiating base plate, respectively. Can be sufficiently secured without using a special technique such as resin sealing and without using a special solder material to which an expensive additive such as a rare metal is added. In addition, since it is possible to perform joint processing using the same kind of solder at both solder joint portions, the joint processing work can be easily and quickly performed efficiently. Therefore, even if the same kind of lead-free solder is used for both solder joints, it is possible to achieve material cost reduction and cost reduction by reducing processes while ensuring durability reliability of the joints.

また本発明の第3の特徴によれば、従来普通に使用される安価な鉛フリーはんだの使用が可能となり、更なるコストダウンを図ることができる。   In addition, according to the third feature of the present invention, it is possible to use an inexpensive lead-free solder that is conventionally used, thereby further reducing the cost.

また本発明の第4の特徴によれば、リフロー炉内ではんだ全体を均一に溶融させ且つ半導体素子との接合部の耐久信頼性が得られる加熱温度で各はんだを同時に加熱溶融させて的確に接合処理することができる。   Further, according to the fourth feature of the present invention, the entire solder is uniformly melted in a reflow furnace and each solder is simultaneously heated and melted at a heating temperature at which durability reliability of the joint portion with the semiconductor element is obtained. Bonding can be performed.

本発明の一実施例に係るパワーモジュールの要部断面図Sectional drawing of the principal part of the power module which concerns on one Example of this invention 前記パワーモジュールの要部の分解図Exploded view of the main part of the power module 放熱用ベース板側のはんだの熱による亀裂進展解析結果を示すグラフGraph showing the results of crack growth analysis by heat of solder on the base plate side for heat dissipation 前記パワーモジュールのはんだ接合部についての熱疲労試験の解析により、Coffin-Manson 則を用いて得た発生歪と温度サイクルとの関係を示すグラフGraph showing the relationship between generated strain and temperature cycle obtained using Coffin-Manson rule by analysis of thermal fatigue test on solder joint of the power module 回路基板の平均熱膨張係数αave とサイクル数との関係を示すグラフGraph showing the relationship between average thermal expansion coefficient α ave of circuit board and cycle number 回路基板の平均熱膨張係数αave と、回路基板における両銅板の板厚の和tM の、絶縁基板の板厚tC に対する比aとの関係を示すグラフA graph showing the relationship between the average thermal expansion coefficient α ave of the circuit board and the ratio a of the sum t M of the thicknesses of both copper plates in the circuit board to the thickness t C of the insulating board 回路基板における銅板の厚みとサイクル数との関係を示すグラフA graph showing the relationship between the thickness of the copper plate on the circuit board and the number of cycles

以下、本発明の実施の形態について、添付の図面を参照しながら説明する。   Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

先ず図1,図2において、半導体装置としてのパワーモジュールPMは、例えば窒化ケイ素などのセラミック材を主要材料とする絶縁基板Cの両面に第1,第2金属板としての第1,第2銅板M1,M2を各々一体的に接合してなる回路基板Pと、第1銅板M1の外面に第1はんだH1を介して接合される少なくとも1個の半導体素子S,S′と、第2銅板M2の外面に第2はんだH2を介して接合される銅製の放熱用ベース板Bとを備えており、各はんだH1,H2は、何れも鉛フリーはんだ材で構成される。   1 and 2, a power module PM as a semiconductor device includes first and second copper plates as first and second metal plates on both surfaces of an insulating substrate C mainly made of a ceramic material such as silicon nitride. A circuit board P formed by integrally joining M1 and M2, respectively, at least one semiconductor element S, S ′ joined to the outer surface of the first copper plate M1 via a first solder H1, and a second copper plate M2 And a heat-radiating base plate B made of copper, which is joined to the outer surface via the second solder H2, and each of the solders H1 and H2 is made of a lead-free solder material.

前記回路基板Pの構造は、従来公知のDCB基板と基本的に同一である。   The structure of the circuit board P is basically the same as a conventionally known DCB board.

また前記第1,第2はんだH1,H2としては、同種の(本実施例では同一の)鉛フリーはんだ材料、例えば、SnCu系、SnAg系またはSnAgCu系の合金であって、添加物を全く含まないか、或いは含むとしてもその添加物がNi、Co又はGeのうちの少なくとも1つである安価な鉛フリーはんだ材料が使用されており、これには、耐久性を高めるための高価な添加材、例えばビスマスやインジウム等のレアメタルは添加されていない。それら鉛フリーはんだは、その溶融温度が錫鉛系共晶はんだの溶融温度よりも高く、また鉛系はんだの溶融温度よりも低い。   The first and second solders H1 and H2 are the same kind (the same in this embodiment) of lead-free solder materials, for example, SnCu-based, SnAg-based or SnAgCu-based alloys, which do not contain any additives. An inexpensive lead-free solder material is used that does not contain or includes at least one of Ni, Co, or Ge, which is an expensive additive to increase durability For example, rare metals such as bismuth and indium are not added. These lead-free solders have a melting temperature higher than that of tin-lead eutectic solder and lower than that of lead-based solder.

従って、これらSnCu系、SnAg系またはSnAgCu系の鉛フリーはんだ材は、半導体素子S,S′側の第1はんだH1として使用された場合には、その素子の動作温度(160°C以下)に対して十分高い溶融温度(約220°C)を有していて、従来の鉛系高融点はんだと同様に半導体素子の使用に際しての発熱によっても再溶融せず、また放熱用ベース板B側の第2はんだH2として使用された場合には、従来の錫鉛系共晶はんだを使用した場合よりも熱に対する耐久性向上が見込まれることが本発明者による解析の結果により判明した。   Therefore, when these SnCu-based, SnAg-based or SnAgCu-based lead-free solder materials are used as the first solder H1 on the semiconductor element S, S 'side, the operating temperature of the element (160 ° C or lower) is reached. On the other hand, it has a sufficiently high melting temperature (about 220 ° C.), and does not remelt due to heat generated during use of a semiconductor element as in the case of a conventional lead-based high melting point solder. As a result of the analysis by the present inventor, when the second solder H2 is used, it is expected that the durability against heat is expected to be higher than when the conventional tin-lead eutectic solder is used.

即ち、図3には、厚さ(0.3mmと0.5mm)を異ならせた2枚の銅板に放熱用ベース板Bを錫鉛系共晶はんだ又は本発明の鉛フリーはんだでそれぞれ接合した場合における、所定のサイクル温度変化幅での温度サイクル試験(TCT)を行った場合の試験サイクル数と、はんだ接合部の亀裂進展長さとの関係を解析した結果を示しており、この解析からも、鉛フリーはんだを使用した場合の方が、錫鉛系はんだを使用した場合よりも、同一温度サイクルにおいてはんだ接合部の亀裂進展長さが短く、即ち、温度ストレスに対するはんだ接合部の耐久性が高いことが明らかである。   That is, in FIG. 3, the heat dissipation base plate B is joined to two copper plates of different thicknesses (0.3 mm and 0.5 mm) with tin-lead eutectic solder or the lead-free solder of the present invention. Shows the results of analyzing the relationship between the number of test cycles when a temperature cycle test (TCT) is performed at a predetermined cycle temperature variation range and the crack growth length of the solder joint. When using lead-free solder, the crack propagation length of the solder joint is shorter at the same temperature cycle than when using tin-lead solder, that is, the durability of the solder joint against temperature stress is reduced. Clearly high.

尚、本実施例で用いられる温度サイクル試験(TCT)は、JETA、即ち電子情報技術産業協会により定められている半導体の信頼性規格中の温度サイクル試験に準拠したものであって、例えば自動車に搭載した場合に一回の走行でオン・オフを繰り返す回数要件および材料特性で求まる条件にて試験が行われ、その試験の際のサイクル温度変化幅は、−40°C〜105°Cの範囲に設定されている。   The temperature cycle test (TCT) used in this example is based on the temperature cycle test in the semiconductor reliability standard established by the JETA, that is, the Japan Electronics and Information Technology Industries Association. When mounted, the test is performed under the conditions determined by the requirements for the number of times to turn on and off in one run and the material characteristics, and the cycle temperature variation range during the test is in the range of −40 ° C. to 105 ° C. Is set to

また前記半導体素子S,S′としては、従来公知のパワー半導体素子、例えば、IGBT、MOS−FET、或いはFWDといった各種素子が用いられ、それらは、シリコンを主要材料としている。   As the semiconductor elements S and S ′, conventionally known power semiconductor elements, for example, various elements such as IGBT, MOS-FET, or FWD, are used, which are mainly made of silicon.

また回路基板Pにおいては、各はんだH1,H2の温度ストレスに対する耐久性を十分に確保するために、前記第1,第2銅板M1,M2の板厚の和t1の、絶縁基板Cの板厚t2に対する比aが、各はんだH1,H2の温度ストレスに対する耐久性を確保し得る所定範囲(後述するように1.5以上で且つ5.5以下の範囲)に収まるように設定されている。   In addition, in the circuit board P, the thickness t1 of the insulating substrate C is equal to the sum t1 of the thicknesses of the first and second copper plates M1 and M2 in order to ensure sufficient durability against the temperature stress of the solders H1 and H2. The ratio a to t2 is set so as to be within a predetermined range (a range of 1.5 or more and 5.5 or less as will be described later) in which durability against temperature stress of the solders H1 and H2 can be secured.

本発明者は、前記比aが、各はんだH1,H2の温度ストレスに対する耐久性を確保する上で重要なパラメータであることを、はんだ接合部の疲労試験等の解析結果より究明したものであり、その解析の手法を以下に説明する。   The present inventor has clarified that the ratio a is an important parameter for ensuring the durability against the temperature stress of each solder H1, H2 from the analysis result such as a fatigue test of the solder joint. The analysis method will be described below.

先ず、回路基板Pの各構成要素、放熱用ベース板B、各はんだH1,H2、素子S,S′の解析モデルを作成し、次いで、半導体装置のはんだ接合部の熱疲労試験を行うために前記した温度サイクル試験(TCT)の所定の温度条件に合わせてサイクル温度変化幅を設定する等して、解析条件を設定する。   First, an analysis model of each component of the circuit board P, the heat radiating base plate B, each of the solders H1 and H2, and the elements S and S ′ is created, and then a thermal fatigue test of the solder joint portion of the semiconductor device is performed. Analysis conditions are set by setting a cycle temperature change width in accordance with a predetermined temperature condition of the temperature cycle test (TCT) described above.

次に構造解析を実際の実験により或いはコンピュータによる模擬実験(シミュレーション)により実施し、これで得た各はんだH1,H2の接合部の発生歪と、温度サイクル試験でのサイクル数との関係を Coffin-Manson 則に基づいて図4のように求め、この関係からはんだ接合部の耐久信頼性を評価、判断する。尚、この図4によれば、各温度サイクルにおいてはんだ接合部の発生歪(即ち温度ストレス)が小さければ小さいほど、ライフサイクル数(即ち接合部の亀裂進展長さが規定限界に至るまでの試験サイクル数)が大きくなって、はんだ接合部の耐久信頼性が高くなることが明らかである。   Next, structural analysis was carried out by actual experiments or computer simulations (simulations), and the relationship between the generated strain at the joints of each solder H1, H2 and the number of cycles in the temperature cycle test was determined. Based on the -Manson rule, it is obtained as shown in FIG. 4, and the durability reliability of the solder joint is evaluated and judged from this relationship. According to FIG. 4, the smaller the generated strain (that is, temperature stress) of the solder joint in each temperature cycle, the smaller the life cycle number (that is, the test until the crack propagation length of the joint reaches the specified limit). It is clear that the durability reliability of the solder joint becomes higher as the number of cycles) increases.

この解析結果に基づいて、各はんだH1,H2の接合部の耐久信頼性に対する、パワーモジュールPMの各部の厚さ(例えば素子S,S′の厚さ、各はんだH1,H2の厚さ、各銅板M1,M2の厚さ、両銅板M1,M2の厚さの差、ベース板Bの厚さ等)や熱膨張係数等の寄与率をそれぞれ解析したところ、パワーモジュールPMの各部の厚さのうち銅板M1,M2の厚さの寄与率が最も高く、他の部位の厚さの寄与率は比較的軽微であることが判明した。   Based on the analysis result, the thickness of each part of the power module PM (for example, the thickness of the elements S, S ′, the thickness of each solder H1, H2, The thicknesses of the copper plates M1 and M2, the difference between the thicknesses of the copper plates M1 and M2, the thickness of the base plate B, etc.) and the contribution factors such as the thermal expansion coefficient are analyzed. Of these, it was found that the contribution ratios of the thicknesses of the copper plates M1 and M2 were the highest, and the contribution ratios of the thicknesses of the other parts were relatively small.

さらに前記解析結果によれば、素子側の第1はんだH1は、回路基板Pの平均熱膨張係数が小さいと(即ち素子S,S′の主要材料であるシリコンに近くなるにつれて)耐久信頼性が高くなり、またベース板側の第2はんだH2は、回路基板Pの平均熱膨張係数が大きいと(即ちベース板Bの構成材料である銅に近くなるにつれて)耐久信頼性が高くなることが判明したが、これは、温度変化に伴い各はんだH1,H2に発生する歪が、これを挟む構造物の熱膨張係数の差に依存することに関係しているためと考えられる。   Further, according to the analysis result, the first solder H1 on the element side has durability reliability when the average thermal expansion coefficient of the circuit board P is small (that is, as it becomes closer to silicon which is the main material of the elements S and S ′). The second solder H2 on the base plate side becomes higher in durability reliability when the average thermal expansion coefficient of the circuit board P is larger (that is, as it becomes closer to copper as a constituent material of the base plate B). However, this is considered to be due to the fact that the strain generated in each solder H1, H2 with temperature change depends on the difference in the thermal expansion coefficient between the structures sandwiching the solder.

そこで次に、回路基板Pの平均熱膨張係数αave と、はんだ接合部のライフサイクル数との関係を調べたところ、図5のような結果となった。これによれば、素子側の第1はんだH1の耐久信頼性は、回路基板Pの平均熱膨張係数αave が小さくなるほど高くなり、一方、ベース板側の第2はんだH2の耐久信頼性は、回路基板Pの平均熱膨張係数αave が小さくなるほど低くなって、両者が相反する傾向を示すことが裏付けられた。従って、これらはんだH1,H2の耐久信頼性を同時に満足する平均熱膨張係数αave の特定領域に基づいて第1,第2銅板M1,M2の厚みを選定する必要がある。 Then, next, when the relationship between the average thermal expansion coefficient α ave of the circuit board P and the life cycle number of the solder joint portion was examined, the result as shown in FIG. 5 was obtained. According to this, the durability reliability of the first solder H1 on the element side becomes higher as the average thermal expansion coefficient α ave of the circuit board P becomes smaller, while the durability reliability of the second solder H2 on the base plate side is It was confirmed that the average thermal expansion coefficient α ave of the circuit board P decreases as the average thermal expansion coefficient α ave decreases, and the two tend to conflict. Therefore, it is necessary to select the thicknesses of the first and second copper plates M1 and M2 based on a specific region of the average thermal expansion coefficient α ave that satisfies the durability reliability of the solders H1 and H2.

その選定に当たっては、第1,第2はんだH1,H2の耐久信頼性を満足する目安として、前記した温度サイクル試験(TCT)において、はんだ接合部のライフサイクル数がパワーモジュールのはんだ接合部として要求される所定の要求サイクル数以上(本実施例では1000サイクル以上)の条件を満たすものとする。この条件を満たす回路基板Pの平均熱膨張係数αave は、図5において、7.5〜12ppm/℃の範囲となり、平均熱膨張係数αave がこの範囲である回路基板Pを使用すれば、両はんだH1,H2の耐久信頼性を同時に満足させることができ、パワーモジュールとしての耐久信頼性の要求レベルを満たすことが可能となる。 In the selection, the life cycle number of the solder joint part is required as the solder joint part of the power module in the temperature cycle test (TCT) as a guideline for satisfying the durability reliability of the first and second solders H1 and H2. It is assumed that the condition of a predetermined required number of cycles or more (1000 cycles or more in this embodiment) is satisfied. Average thermal expansion coefficient alpha ave satisfying this condition the circuit board P, in Figure 5, be in the range of 7.5~12ppm / ℃, average thermal expansion coefficient alpha ave is The use of the circuit board P is in this range, The durability reliability of both the solders H1, H2 can be satisfied at the same time, and the required level of durability reliability as a power module can be satisfied.

ところで、第1,第2銅板M1,M2の板厚の和tM の、絶縁基板の板厚tC に対する比をaとすれば、 a=tM /tC となり、
また回路基板Pの平均熱膨張係数をαave とし、またセラミックス製絶縁基板Cの熱膨張係数及びヤング率をそれぞれαC 及びEC とし、銅板M1,M2の銅材の熱膨張係数及びヤング率をそれぞれαM 及びEM としたとき、αave は次式で表すことができる。
By the way, if the ratio of the sum t M of the thicknesses of the first and second copper plates M1 and M2 to the thickness t C of the insulating substrate is a, a = t M / t C ,
The average thermal expansion coefficient of the circuit board P is α ave , the thermal expansion coefficient and Young's modulus of the ceramic insulating substrate C are α C and E C , respectively, and the thermal expansion coefficient and Young's modulus of the copper material of the copper plates M1 and M2 Α ave can be expressed by the following equation, where α M and E M respectively.

αave =(a・αM ・EM +αC ・EC )/(aEM +EC
そして、この式は、上記比aと回路基板Pの平均熱膨張係数αave との関係として、図6のグラフに表すことができる。そして、このグラフにおいて、前記したような第1,第2はんだH1,H2の耐久信頼性を同時に満足させるような回路基板Pの平均熱膨張係数αave の範囲(7.5〜12ppm/℃)を満足させる前記比aの範囲は、1.5〜5.5となる。
α ave = (a · α M · E M + α C · E C ) / (aE M + E C )
This equation can be expressed in the graph of FIG. 6 as the relationship between the ratio a and the average thermal expansion coefficient α ave of the circuit board P. In this graph, the range of the average thermal expansion coefficient α ave of the circuit board P that satisfies the durability reliability of the first and second solders H1 and H2 as described above (7.5 to 12 ppm / ° C.). The range of the ratio a that satisfies the above is 1.5 to 5.5.

従って、その比aの範囲を満足させるように第1,第2銅板M1,M2の板厚の選定を行えば、第1,第2はんだH1,H2の耐久信頼性を同時に満足させることができる第1,第2銅板M1,M2の板厚選定が可能となる。   Therefore, if the thicknesses of the first and second copper plates M1 and M2 are selected so as to satisfy the range of the ratio a, the durability reliability of the first and second solders H1 and H2 can be satisfied at the same time. The thickness of the first and second copper plates M1 and M2 can be selected.

例えば、絶縁基板の板厚tC が0.32mmである標準的なパワーモジュールPMにおいては、前記比a(=tM /tC )が1.5≦a≦5.5である前記条件を適用して第1,第2銅板M1,M2の板厚の和tM を算出すると、それは、0.48mm〜1.76mmの範囲となる。一方、図7は、このパワーモジュールPMに関して第1,第2銅板M1,M2の板厚の和tM を横軸とし、且つ前記温度サイクル試験(TCT)における温度サイクル数を縦軸として第1,第2はんだH1,H2のライフサイクル数を実験的に求めたグラフが示されている。そして、このグラフにおいて、第1,第2銅板M1,M2の板厚の和tM が前記0.48mm〜1.76mmの範囲(図7ではOK領域と表示)では、第1,第2はんだH1,H2のライフサイクル数が何れも所定の要求サイクル数(実施例では1000)以上となっていて、各はんだ接合部が十分な耐久信頼性を有していることが窺い知れる。 For example, in a standard power module PM in which the thickness t C of the insulating substrate is 0.32 mm, the ratio a (= t M / t C ) is 1.5 ≦ a ≦ 5.5. When applied to calculate the sum t M of the thicknesses of the first and second copper plates M1 and M2, it is in the range of 0.48 mm to 1.76 mm. On the other hand, FIG. 7 shows the first power module PM with the sum t M of the thicknesses of the first and second copper plates M1 and M2 as the horizontal axis and the number of temperature cycles in the temperature cycle test (TCT) as the vertical axis. The graph which calculated | required the life cycle number of 2nd solder H1, H2 experimentally is shown. In this graph, when the sum t M of the thicknesses of the first and second copper plates M1 and M2 is in the range of 0.48 mm to 1.76 mm (shown as an OK region in FIG. 7), the first and second solders. It is well known that the number of life cycles of H1 and H2 is equal to or greater than a predetermined required number of cycles (1000 in the embodiment), and each solder joint has sufficient durability reliability.

以上のようにして構成した回路基板Pの一面及び他面の銅板M1,M2に半導体素子S,S′及び放熱用ベース板Bをはんだ付けしてパワーモジュールPMを製造するに際しては、回路基板Pの素子側の第1銅板M1の外面に第1鉛フリーはんだH1を介して半導体S,S′を接合する処理と、ベース板側の第2銅板M2の外面に第2鉛フリーはんだH2を介して放熱用ベース板Bを接合する処理とを同一の加熱条件で同時に実行するようにする。   When the power module PM is manufactured by soldering the semiconductor elements S, S ′ and the heat radiating base plate B to the copper plates M1, M2 on one side and the other side of the circuit board P configured as described above, the circuit board P The process of joining the semiconductors S and S ′ to the outer surface of the first copper plate M1 on the element side via the first lead-free solder H1, and the second lead-free solder H2 on the outer surface of the second copper plate M2 on the base plate side Thus, the process of joining the base plate B for heat dissipation is performed simultaneously under the same heating conditions.

これらのはんだ付け処理は、処理炉としての従来周知のリフロー炉(図示せず)内で行われ、その時のリフロー温度は、リフロー炉内で各はんだH1,H2全体を均一に溶融させ且つ半導体素子S,S′との接合部の耐久信頼性が得られる加熱温度として、240°C以上で且つ320°C以下に設定される。このようなリフロー温度設定により、リフロー炉内ではんだH1,H2全体を均一に溶融させ且つ半導体素子S,S′との接合部の耐久信頼性が得られる加熱温度で各はんだH1,H2を同時に加熱溶融させて、両はんだ接合部を的確に接合処理することができる。   These soldering processes are performed in a conventionally known reflow furnace (not shown) as a processing furnace, and the reflow temperature at that time uniformly melts each of the solders H1 and H2 in the reflow furnace, and the semiconductor element. The heating temperature at which the durability reliability of the joint portion with S and S ′ is obtained is set to 240 ° C. or more and 320 ° C. or less. With such a reflow temperature setting, the solders H1 and H2 are simultaneously melted at a heating temperature at which the entire solders H1 and H2 are uniformly melted in the reflow furnace and durability of the joints with the semiconductor elements S and S ′ is obtained. By heating and melting, both solder joints can be accurately joined.

また各はんだH1,H2の接合処理に当たっては、例えば放熱用ベース板B上の所定位置に、所定形状に予め形成された薄板状の第2鉛フリーはんだH2を挟んで回路基板Pの、ベース板側の第2銅板M2の外面を載せ、更にその回路基板Pの素子側の第1銅板M1の外面の所定位置に、予め形成された薄板状の第1鉛フリーはんだH1を挟んで半導体素子S,S′を載せたものを、予め所定のリフロー温度に加熱したリフロー炉内にセットし、所定時間加熱することで各はんだH1,H2を溶融し、その後にリフロー炉より取り出して冷却、固化させることではんだ付け処理を行うようにする。   In the joining process of the solders H1 and H2, for example, the base plate of the circuit board P is sandwiched with a thin plate-like second lead-free solder H2 formed in a predetermined shape at a predetermined position on the base plate B for heat dissipation. The outer surface of the second copper plate M2 on the side is placed, and the semiconductor element S is sandwiched at a predetermined position on the outer surface of the first copper plate M1 on the element side of the circuit board P with a thin plate-like first lead-free solder H1 formed in advance. , S 'are placed in a reflow furnace heated to a predetermined reflow temperature in advance, and heated for a predetermined time to melt each solder H1, H2, and then taken out from the reflow furnace to cool and solidify. So that the soldering process is performed.

而して、本実施例のパワーモジュールPMの回路基板Pにおいては、絶縁基板C両側の第1,第2銅板M1,M2の板厚の和tM の、絶縁基板Cの板厚tC に対する比a(=tM /tC )が、同種の(本実施例では同一の)鉛フリーはんだ材よりなる第1,第2はんだH1,H2の温度ストレスに対する耐久性を確保するために、所定の制限された範囲、即ち1.5以上で且つ5.5以下の範囲内に設定されている。しかもその両はんだ接合部には、素子S,S′の動作温度(160°以下)に対し十分高い溶融温度(約220°C)を有していて素子の使用に際しての発熱によっても再溶融せず且つ錫鉛系はんだを使用した場合よりも熱に対する耐久性向上が見込まれる鉛フリーはんだを用いることで、これらをリフロー炉内で前記リフロー温度(即ち240°C以上で且つ320°C以下)で一括で接合処理することができる。 Thus, in the circuit board P of the power module PM of the present embodiment, the sum t M of the thicknesses of the first and second copper plates M1 and M2 on both sides of the insulating substrate C with respect to the plate thickness t C of the insulating substrate C. The ratio a (= t M / t C ) is predetermined in order to ensure durability against temperature stress of the first and second solders H1 and H2 made of the same kind (same in this embodiment) of lead-free solder materials. Is set within a limited range of 1.5, that is, 1.5 or more and 5.5 or less. Moreover, both the solder joints have a sufficiently high melting temperature (about 220 ° C.) with respect to the operating temperature of the elements S and S ′ (160 ° C. or less), so that they can be re-melted due to heat generated during use of the elements. In addition, by using lead-free solder, which is expected to have higher durability against heat than when tin-lead solder is used, these are reflow temperatures (that is, 240 ° C or higher and 320 ° C or lower) in a reflow furnace. It is possible to perform the joining process at once.

そのため、回路基板P両面の第1,第2銅板M1,M2と、素子S,S′、放熱用ベース板Bとの各間をそれぞれ接合する第1,第2はんだH1,H2による接合部の耐久信頼性を、樹脂封止等の特殊な手法を採ることなく、且つレアメタル等の高価な添加材を添加した特殊なはんだ材料を使用することなく、十分に確保可能となる。しかもその両はんだ接合部を一括で接合処理可能となることで、全体として接合処理作業を簡単且つ迅速に能率よく行うことができる。   Therefore, the first and second copper plates M1 and M2 on both sides of the circuit board P and the elements S, S ′ and the heat radiating base plate B are joined by first and second solders H1 and H2, respectively. Durability and reliability can be sufficiently secured without using a special technique such as resin sealing and without using a special solder material to which an expensive additive such as a rare metal is added. Moreover, since both the solder joints can be jointly processed, the joint processing operation can be easily and quickly performed efficiently as a whole.

かくして、その両はんだH1,H2の接合部に、従来普通に使用される安価な鉛フリーはんだ材料(即ち、SnCu系、SnAg系またはSnAgCu系の合金であって、添加物としてレアメタルを含まない安価な鉛フリーはんだ材料)が使用されても、それらのはんだ接合部の耐久信頼性を十分に確保可能としながら、従来装置と比べて材料費低減や工程削減によるコストダウンを達成できる。   Thus, an inexpensive lead-free solder material that is conventionally used at the joint between the solders H1 and H2 (that is, an inexpensive SnCu-based, SnAg-based or SnAgCu-based alloy that does not contain a rare metal as an additive). Even if a lead-free solder material) is used, it is possible to achieve a reduction in material cost and cost reduction by reducing processes compared to conventional devices while ensuring sufficient durability reliability of the solder joints.

以上、本発明の実施の形態について説明したが、本発明は上記実施の形態に限定されるものではなく、特許請求の範囲に記載された本発明を逸脱することなく種々の設計変更を行うことが可能である。   Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various design changes can be made without departing from the present invention described in the claims. Is possible.

例えば、前記実施例では、放熱用ベース板として用いる金属板として銅板を使用したが、本発明では、銅、アルミ、タングステン、モリブデン等の複合材でベース板を構成してもよい。   For example, in the above embodiment, a copper plate is used as the metal plate used as the heat radiating base plate. However, in the present invention, the base plate may be composed of a composite material such as copper, aluminum, tungsten, and molybdenum.

B・・・・放熱用ベース板
C・・・・絶縁基板
H1・・・第1はんだ
H2・・・第2はんだ
M1・・・第1金属板としての第1銅板
M2・・・第2金属板としての第2銅板
P・・・・回路基板
S,S′・・半導体素子
a・・・・比
C ・・・絶縁基板の板厚
M ・・・第1,第2金属板(第1,第2銅板)の板厚の和
B .... Heat dissipation base plate C ... Insulating substrate H1 ... First solder H2 ... Second solder M1 ... First copper plate M2 as first metal plate ... Second metal Second copper plate P as a plate... Circuit board S, S ′... Semiconductor element a... Ratio t C .. thickness t M of insulating substrate ... first and second metal plates ( Sum of thickness of first and second copper plates)

Claims (4)

絶縁基板(C)の両面に金属板(M1,M2)を各々接合してなる回路基板(P)と、一方の金属板(M1)の外面に第1はんだ(H1)を介して接合される少なくとも1個の半導体素子(S,S′)と、他方の金属板(M2)の外面に第2はんだ(H2)を介して接合される放熱用ベース板(B)とを備えた半導体装置の製造方法において、
前記一方及び前記他方の金属板(M1,M2)の板厚の和(tM )の、前記絶縁基板(C)の板厚(tC )に対する比(a)が、各はんだ(H1,H2)の温度ストレスに対する耐久性を確保し得る所定範囲に収まるようにして、前記回路基板(P)を製造する工程と、
前記回路基板(P)の前記一方の金属板(M1)の外面に第1はんだ(H1)を介して前記半導体(S,S′)を接合する処理と前記他方の金属板(M2)の外面に前記第2はんだ(H2)を介して前記ベース板(B)を接合する処理とを同一の加熱条件で同時に実行する工程とを含み、
前記第1,第2はんだ(H1,H2)は、同種の鉛フリーはんだ材で構成されることを特徴とする、半導体装置の製造方法。
A circuit board (P) formed by bonding metal plates (M1, M2) to both surfaces of the insulating substrate (C) and a first solder (H1) to the outer surface of one metal plate (M1). A semiconductor device comprising at least one semiconductor element (S, S ′) and a heat radiating base plate (B) joined to the outer surface of the other metal plate (M2) via a second solder (H2). In the manufacturing method,
The ratio (a) of the sum (t M ) of the thicknesses of the one and the other metal plates (M1, M2) to the thickness (t C ) of the insulating substrate (C) is determined by each solder (H1, H2 ) Manufacturing the circuit board (P) so as to be within a predetermined range in which durability against temperature stress can be secured;
The process of joining the semiconductor (S, S ′) to the outer surface of the one metal plate (M1) of the circuit board (P) via the first solder (H1) and the outer surface of the other metal plate (M2) And simultaneously performing the process of joining the base plate (B) via the second solder (H2) under the same heating conditions,
The method for manufacturing a semiconductor device, wherein the first and second solders (H1, H2) are made of the same kind of lead-free solder material.
前記比(a)は、1.5以上で且つ5.5以下であることを特徴とする、請求項1に記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the ratio (a) is 1.5 or more and 5.5 or less. 前記第1,第2はんだ(H1,H2)は、SnCu系、SnAg系またはSnAgCu系の合金であって、レアメタルを含まないことを特徴とする、請求項1又は2に記載の半導体装置の製造方法。   The semiconductor device according to claim 1, wherein the first and second solders (H 1, H 2) are SnCu-based, SnAg-based, or SnAgCu-based alloys and do not contain a rare metal. Method. 前記処理は、リフロー炉内で行われ、その時のリフロー温度は、240°C以上で且つ320°C以下に設定されることを特徴とする、請求項1又は2に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 1, wherein the process is performed in a reflow furnace, and a reflow temperature at that time is set to 240 ° C. or more and 320 ° C. or less. .
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015170785A (en) * 2014-03-10 2015-09-28 三菱電機株式会社 Insulation substrate and electric power semiconductor device
JP2016066806A (en) * 2011-06-01 2016-04-28 トヨタ モーター エンジニアリング アンド マニュファクチャリング ノース アメリカ,インコーポレイティド Multi-component power structures and methods for forming the same
JP2020533797A (en) * 2017-09-12 2020-11-19 ロジャーズ ジャーマニー ゲーエムベーハーRogers Germany GmbH Adapter elements for joining components such as laser diodes to heat sinks, systems including laser diodes, heat sinks and adapter elements, and methods of manufacturing adapter elements.

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006041363A (en) * 2004-07-29 2006-02-09 Hitachi Ltd Resin-sealed semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006041363A (en) * 2004-07-29 2006-02-09 Hitachi Ltd Resin-sealed semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016066806A (en) * 2011-06-01 2016-04-28 トヨタ モーター エンジニアリング アンド マニュファクチャリング ノース アメリカ,インコーポレイティド Multi-component power structures and methods for forming the same
JP2015170785A (en) * 2014-03-10 2015-09-28 三菱電機株式会社 Insulation substrate and electric power semiconductor device
JP2020533797A (en) * 2017-09-12 2020-11-19 ロジャーズ ジャーマニー ゲーエムベーハーRogers Germany GmbH Adapter elements for joining components such as laser diodes to heat sinks, systems including laser diodes, heat sinks and adapter elements, and methods of manufacturing adapter elements.
JP7034266B2 (en) 2017-09-12 2022-03-11 ロジャーズ ジャーマニー ゲーエムベーハー Adapter elements for joining components such as laser diodes to heat sinks, systems including laser diodes, heat sinks and adapter elements, and methods of manufacturing adapter elements.
US11476640B2 (en) 2017-09-12 2022-10-18 Rogers Germany Gmbh Adapter element for connecting a component, such as a laser diode, to a heat sink, a system comprising a laser diode, a heat sink and an adapter element and method for producing an adapter element

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