JP2015120081A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine, when arithmetic processing means of performance control means is not normally operated, reliably executing reset processing of the performance processing means and restoring the performance processing means into a normal operation state.SOLUTION: An ROM 24b of a performance control board 24 includes: a program area for storing respective types of control processing routines constituting a performance control program; a data area for storing data necessary for executing the respective types of control processing routines; and a program area in abnormality for storing a trap routine for executing loop processing that is dedicated to a case of the abnormality, and cannot be executed when the CPU 24a is normally operated. When the trap routine is executed in a case where the CPU 24a does not normally operate, the game machine stops the output of a reset signal and does not execute the respective types of control processing routines until the CPU 24a is reset by a WDT circuit.

Description

  The present invention relates to a gaming machine, and more particularly to a technique for interrupting the progress of control and processing by a CPU when a CPU of a control means does not operate normally.

  Conventionally, in a pachinko gaming machine, a control device provided on the back side of the game board includes a main control board that controls the progress of the game, an image display for presentation on an image display, an audio output from a speaker, a lamp And a sub-control board for controlling a game effect by the effect device such as lighting, and each of the control boards is provided with a computer including a CPU, a ROM, and a RAM.

  Conventionally, a pachinko gaming machine is provided with a WDT circuit (watchdog timer circuit) for monitoring the operation of the CPU of the main control board and detecting an abnormality of the CPU. The CPU of the main control board executes a game control program stored in the ROM to execute various control processes, and outputs a WDTCLR signal (watchdog timer clear signal) to the WDT circuit at every predetermined timing. Reset (initialize) the timer clock.

  On the other hand, when the CPU of the main control board becomes abnormal for some reason (for example, when it is in a runaway state, a hang-up state, or has failed due to an external noise or the like), a WDTCLR signal is sent from the CPU to the WDT circuit. When the timer section of the WDT circuit times out for a predetermined time after the state of not being output, a reset signal is output from the WDT circuit to the CPU, and the operation of the CPU is forcibly reset. (For example, refer to Patent Document 1).

  In addition, the CPU of the sub control board receives control information output from the main control board by one-way communication, and executes various control processes by executing the effect control program stored in the ROM based on the control information. . By the way, when the CPU of the sub control board is in an abnormal state for some reason (for example, when the CPU runs away due to an external noise or the like), the main control board can know the abnormal state of the CPU of the sub control board. Therefore, there is a problem that only the control / processing of the CPU of the main control board proceeds while the abnormal state of the CPU of the sub control board is left unattended.

  In order to solve the above problems, the bullet ball game machine of Patent Document 2 includes a display control board that controls video display control means for displaying video on a liquid crystal display board based on control information received from the CPU of the main board. And a monitoring circuit that monitors the CPU of the display control board and resets the CPU if there is an abnormality.

JP 2007-215953 A Japanese Patent Laid-Open No. 10-249032

  In the ROM of the sub control board, a plurality of processing routines (control processing) constituting the effect control program are allocated and stored in predetermined address areas of the program area, and a plurality of processing routines necessary for executing various processing routines are stored. Data is allocated and stored in a predetermined address area of the data area, and an empty area (unused area) is formed between the program area and the data area or in an area following the data area.

  When the CPU of the sub-control board runs away due to the influence of external noise or the like, an unexpected phenomenon such as entering an empty area that does not enter during normal operation after sequentially executing a plurality of processing routines in the program area occurs. In particular, when the processing routine for outputting the WDTCLR signal to the WDT circuit is executed even though the CPU is in a runaway state, the timing of the timer unit of the WDT circuit is cleared and the CPU is not reset (ie, WDT). Since the function of the circuit does not work), the runaway state of the CPU is left unattended, and if this runaway state continues, there is a risk that the program will be destroyed and the safety of computer control cannot be ensured.

In the ball game machine of Patent Document 2, even if the CPU of the display control board runs away, if the function of the monitoring circuit does not work, the runaway state of the CPU remains neglected. The game is progressed in a state where the display is not normally executed.
The object of the present invention is to reliably execute the reset processing of the arithmetic processing means and restore the arithmetic processing means to operate normally when the arithmetic processing means of the effect control means is not operating normally. .

The present invention has the following configuration. Note that the reference numerals show an example of the correspondence with the components shown in the drawings for the purpose of promoting the understanding of the present invention, and do not limit the technical scope of the present invention.
A first invention (game machine) comprises a game control means (22) for controlling a game, and an effect control means (24) for receiving information from the game control means (22) and controlling the effect. In (1), the effect control means (24) includes a nonvolatile storage means (24b) in which an effect control program is stored, and various controls constituting the effect control program stored in the nonvolatile storage means (24b). The processing routine (24a) that periodically outputs a reset signal is monitored and the reset signal output from the arithmetic processing means (24a) is monitored, and the reset signal is periodically Resetting means (29) for resetting the arithmetic processing means (24a) when the data is not output automatically, the nonvolatile storage means (24b) is configured so that the arithmetic processing means (24a) operates normally. Before being assigned to the address to use Not used when the program area storing various control processing routines, the data area storing data necessary for executing the various control processing routines, and the arithmetic processing means (24a) are operating normally An abnormal program area storing a trap routine assigned to an address, and the trap routine is a loop different from the loop process executed when the arithmetic processing means (24a) is operating normally. Processing, and the output of the reset signal by the arithmetic processing means (24a) is limited by executing a loop process dedicated to an abnormality that cannot be executed when the arithmetic processing means (24a) is operating normally. The arithmetic processing means (24a) limits the output of the reset signal by executing the trap routine, and performs the reset procedure. The various control processing routines are not executed until the arithmetic processing means (24a) is reset by the stage (29).

  According to the present invention, when the arithmetic processing means of the effect control means is not operating normally, the arithmetic processing means can be reliably reset to restore the arithmetic processing means to operate normally. .

It is a front view of a pachinko gaming machine. It is a block diagram of the control system of a pachinko gaming machine. It is a block diagram which shows the structure of a WDT circuit. It is a memory map explaining the structure of the program stored in ROM of an effect control board. It is a flowchart of the main process which the computer of a game control board performs. It is a flowchart of a timer interruption process. It is a flowchart of the main process which the computer of an effect control board performs. It is a flowchart of a timer interruption process. It is a flowchart of a trap process.

  Hereinafter, modes for carrying out the present invention will be described based on examples.

  As shown in FIGS. 1 and 2, a pachinko gaming machine 1 includes an outer frame 2 fixed to an island structure of a game hall, and an open / close frame 3 pivotally supported by the outer frame 2 (inner frame 3). The game board 4 attached to the open / close frame 3 and the open / close door 5 having a transparent plate 5a pivotally supported by the open / close frame 3 so that the front side of the game board 4 can be opened and closed are provided. A storage tray 6, a firing handle 7, and an effect button 14 are attached to the open / close door 5.

  The game board 4 includes a guide rail 8, a number of obstacle nails 9, a first start port 10, a variable start port device 11 having an openable second start port 11a, a gate 12, and an openable large winning port 13a. The big winning opening device 13 and the plurality of general winning openings 15 are provided in the illustrated arrangement so that the game balls can pass (win). The first starting port 10, the gate 12, and the plurality of general winning ports 15 are respectively provided with a first starting port SW10a, a gate SW12a, and a plurality of general winning ports SW15a for detecting a winning game ball. “SW” means a switch.

  The variable start port device 11 includes a second start port 11a, an opening / closing member 11b for opening / closing the second start port 11a, a second start port SW11c for detecting a game ball won in the second start port 11a, and an opening / closing member 11b. Has a second start port SOL11d ("SOL" means a solenoid actuator).

  The big prize opening device 13 opens and closes the big prize opening 13a, the opening / closing member 13b for opening / closing the big prize opening 13a, the big winning opening SW13c for detecting a game ball won in the big prize opening 13a, and the opening / closing member 13b. It has a big prize opening SOL13d.

  When a game ball wins any one of the winning openings 10, 11a, 13a, 15, the number of game balls set for each winning opening 10, 11a, 13a, 15 is stored as a winning ball for each winning game ball. It is paid out to the tray 6. A big hit lottery is performed when a game ball wins one of the first or second start openings 10, 11a, and when a win is won by the big hit lottery, the big win opening 13a is opened, which is advantageous to the player. Will occur. When the game ball passes through the gate 12, a winning lottery is performed, and when the winning lottery is won, an auxiliary game in which the normally closed second start port 11a is opened or closed one or more times occurs.

  A center accessory 16 is attached to the game board 4, and the center accessory 16 is equipped with an image display 17 for game effect and a movable accessory device 20. The center accessory 16 is fitted and attached to a center opening 4a in which the center frame 16a is formed relatively large in the game board 4. The image display 17 is arranged inside the center frame 16a so that the screen can be viewed from the front side of the pachinko gaming machine 1. An effect image for game effect is displayed on the screen of the image display 17.

  A game display board 19 is provided in the lower right part of the game board 4, and this game display board 19 has a first special figure display 19a, a second special figure display 19b, a general figure display 19c, and a first special figure holding lamp. 19d, a second special figure holding lamp 19e, and a general figure holding lamp 19f. A control device 21 is mounted on the back side of the game board 4.

Next, a control system of the pachinko gaming machine 1 will be described.
As shown in FIG. 2, the control device 21 includes a game control board 22, a payout control board 23, an effect control board 24, an image control board 25, and a lamp control board 26.
The game control board 22 stores a CPU 22a that executes a game control program and executes various control processes (processing routines) along with the progress of game contents, and data necessary for executing the game control program and the game control program. The computer includes a ROM 22b, a computer having a RAM 22c that functions as a data work area when the CPU 22a performs arithmetic processing, and a WDT circuit 27 (watchdog timer circuit). The game control board 22 is connected to the game information output terminal board 28.

  The computer of the game control board 22 receives the game ball detection signal from the first and second start openings SW10a and 11c, the gate SW12a, the big prize opening SW13c, the plurality of general prize openings SW15a, and the control information from the payout control board 23. The second start opening SOL11d, the special winning opening SOL13d, the symbol displays 19a to 19c, and the symbol holding lamps 19d to 19f are controlled to output control information to the payout control board 23 and to the effect control board 24 in one direction. To output control information.

  As shown in FIG. 3, the WDT circuit 27 monitors whether the operation of the CPU 22a of the game control board 22 is in an abnormal state (for example, a runaway state, a hang-up state, a failure, etc.). A counter unit 27a having a watchdog reset function for forcibly resetting the CPU 22a and counting a preset count value in synchronization with a CLK (clock signal) from an oscillator (not shown); and a CPU reset circuit 27b.

  While the CPU 22a is operating normally, the WDTCLR signal (watchdog timer clear signal) is periodically output (for example, every 4 ms) from the CPU 22a to the WDT circuit 27, and the count value of the counter unit 27a is set by this WDTCLR signal. Cleared (reset). On the other hand, when the operation of the CPU 22a is in an abnormal state, the counter unit 27a counts up (time up) when a state in which the WDTCLR signal is not output from the CPU 22a to the WDT circuit 27 continues for a predetermined time or longer. Upon detecting this, the CPU reset circuit 27b outputs a RESET signal (reset signal) to the CPU 22a for a predetermined time to forcibly reset the CPU 22a.

  The payout control board 23 includes a computer having a CPU 23a, a RAM 23b, and a RAM 23c. The payout control board 23 of the payout apparatus receives the control information from the game control board 22 and the ball detection signal from the payout ball count SW31. While the number of game balls set for each of the winning ports 10, 11a, 13a, 15 is paid out to the storage tray 5 for one winning game ball to the winning ports 10, 11a, 13a, 15 In response to the door opening detection signal from the opening / closing door opening SW 32, the dispensing motor 30 is controlled to stop.

  The effect control board 24 executes an effect control program based on the control information received from the game control board 22 and executes various control processes (processing routines), an effect control program, and an effect control. ROM 24b (non-volatile storage means) storing data necessary for program execution, RAM 24c functioning as a data work area at the time of arithmetic processing of the CPU 24a, and RTC 24d (real time) as time measuring means for measuring and outputting real time A computer having a clock) and a WDT circuit 29 (watchdog timer circuit) (reset means).

  The computer of the effect control board 24 receives the control information from the game control board 22 and the image control board 25 and the detection signal from the effect button 14 and outputs the control information to the image control board 25 and the lamp control board 26.

  As shown in FIG. 3, the WDT circuit 29 includes a counter unit 29 a and a CPU reset circuit 29 b, similar to the WDT circuit 27 of the game control board 22. When the CPU 24a is in a runaway state, a hang-up state or a failure due to an external noise or the like, if the WDTCLR signal is not output from the CPU 24a to the WDT circuit 29 for a predetermined time or more, the counter unit 29a counts up (time up) ) Upon detecting this, the CPU reset circuit 29b outputs a RESET signal to the CPU 24a to forcibly reset the CPU 24a.

  The image control board 25 includes a computer having a CPU 25 a, a ROM 25 b, and a RAM 25 c, controls the game display image display 17 and the speaker 34, and outputs control information to the effect control board 24. The lamp control board 26 includes a computer having a CPU 26a, a ROM 26b, and a RAM 26c. Based on the control information received from the effect control board 24, a game effect frame lamp 35, a panel lamp 36, and a movable accessory device. 20 is controlled.

  As shown in FIG. 4, the memory area of the ROM 24b of the effect control board 24 includes a program area for storing various control processes (processing routines) constituting the effect control program, and data necessary for executing the effect control program. An empty area (unused area) is formed in the data area for storing the class, and the area between the program area and the data area and the area following the data area.

  In the program area, a plurality of processing routines constituting the presentation control program are assigned and stored in a predetermined address area, and in the data area, a plurality of data are assigned and stored in a predetermined address area, respectively. Has been. Specifically, in the program area, an “initialization process routine”, a “watchdog process routine”, an “error process routine”, and a “timer interrupt process routine” are stored in consecutive address areas a to d, respectively. Has been. In the data area, “effect data 1”, “effect data 2”, and “effect data 3” are respectively stored in continuous address areas eg.

  While the CPU 24a of the effect control board 24 is operating normally, each processing routine stored in the address areas a to d of the program area is sequentially executed, and when data is required to execute the processing routine. The data processing of the data stored in the address areas e to g of the data area is sequentially executed.

  Among the empty areas, the address area h following the address area d at the end of the program area, the address area i immediately before the address area e at the beginning of the data area, the address area j following the address area g at the end of the data area, and the end Each address area k stores a “trap routine”. The address area h, i, j, k in which the trap routine is stored corresponds to the abnormal program area.

  When the CPU 24a runs away due to the influence of external noise or the like and enters the empty area, a trap routine is executed. The trap routine is an infinite loop process (loop process dedicated to an abnormal time) configured such that, once the CPU 24a starts executing the instruction process in the trap routine, only the instruction process in the routine is repeated. When the CPU 24a enters the trap routine, it cannot stop from the trap routine until the RESET signal is output from the WDT circuit 29 to the CPU 24a, so that the progress of the control and processing of the CPU 24a is interrupted, and this interrupted state is maintained for a predetermined time. Subsequently, the output of the WDTCLR signal from the CPU 24a to the WDT circuit 29 is stopped.

  Here, although illustration is omitted, the effect control board 24 is provided with a notification lamp (LED) for notifying the operation state of the CPU 24a, and when the trap routine is executed, the history is stored in the RAM 24c. The notification lamp is continuously lit and blinking a predetermined number of times to notify that the trap routine has been executed.

Next, main processes executed by the computer of the game control board 22 will be described based on flowcharts. However, the symbol Si (i = 1, 2, 3...) In the figure is each step.
As shown in FIG. 5, the main process is started by turning on the power. In this main process, first, the process waits for 1000 ms (S1), and then the permission to access the RAM is set (S2). It is determined whether or not is on (S3).

  If the RAM clear SW is not on (S3; No), it is determined whether the backup flag is ON (S4). If the determination is Yes, it is determined whether the checksum is normal (S5), and the determination is Yes. In this case, the recovery process is executed (S6), and the process proceeds to S10.

  On the other hand, when the determination at S3 is Yes, the determination at S4 is No, or the determination at S5 is No, RAM clear (S7), work area setting at the time of clear (S8), peripheral initial setting (S9) ) Are sequentially executed, and then the process proceeds to S10. Here, the peripheral portions are the payout control board 23, the effect control board 24, and the like. The peripheral part initial setting in S9 is a process of transmitting an initial setting command for instructing execution of the initial setting to the computers of the control boards 23 and 24.

  In S10, a timer counter (CTC) cycle (for example, 4 ms) is set, and a timer interrupt process described later is executed in the cycle set in S10. After execution of S10, watchdog processing is executed (S11). In this watchdog process, as described with reference to FIG. 3, the WDTCLR signal is output to the watchdog circuit 27, and the count value of the counter unit 27a of the WDT circuit 27 is cleared.

  After execution of S11, power-off monitoring process (S12), fluctuation pattern (fluctuation time) random number update process (S13), timer interrupt process prohibition setting process (S14), initial value random number update process (S15), timer interrupt After the process permission setting process (S16) is sequentially executed, the process returns to S11. Thereafter, a loop process in which the processes of S11 to S16 are repeated is executed, and the WDTCLR signal is periodically output to the WDT circuit 27.

  As shown in FIG. 6, in the timer interrupt process, a random number update process (S21), a switch process (S22), a symbol process (S23), an electric accessory process (S24), a prize ball process (S25), an output process ( S26) is sequentially executed.

  In the switch process of S22, the start port SW process is executed. In this starting port SW process, when the first or second starting port SW10a or 11c is ON by the game ball winning at the first or second starting port 10 or 11a, the first or second special figure holding number is added. At the same time, the first or second special figure determination information (big hit determination value, symbol determination value, reach determination value and fluctuation pattern determination value) is acquired, a special figure pending increase command including special figure determination information is set, It is output to the effect control board 24 by the output process of S26.

  In the symbol processing of S23, special symbol processing is executed. In this special symbol process, based on the acquired special symbol determination information, a determination process for determining whether or not a big hit, a selection process for a big hit / missing symbol, and a special symbol variation pattern setting process are sequentially performed, and a special symbol including these pieces of information is included. A figure change start command is set and output to the effect control board 24 by the output process of S26. In the electric accessory process of S24, a big prize opening process is executed. In this big winning opening process, in the case of big winning, the opening / closing pattern of the big winning opening is set according to the type of the big winning symbol selected from a plurality of types of the big winning symbol set in advance. A big hit game that opens the big prize opening is executed.

Next, main control processing (processing routine) executed by the computer of the effect control board 24 will be described based on a flowchart. However, symbol Si (i = 31, 32, 33...) In the figure is each step.
As shown in FIG. 7, in the main process, initial setting (S31), timer counter (CTC) cycle setting (S32), and random number update process (S33) are sequentially executed. The processing from S31 to S33 corresponds to initialization processing. A timer interrupt process, which will be described later, is executed in the CTC cycle set in S32.

  Next, a random number update process (S33), a watchdog process (S34), an error process (S35), and a timer interrupt process (S36) are sequentially executed, and then the process returns to S33. Thereafter, a loop process for repeatedly performing the processes of S33 to S36 is executed. In the watchdog process of S34, as described with reference to FIG. 3, the WDTCLR signal is output to the watchdog circuit 29, and the count value of the counter unit 29a of the WDT circuit 29 is cleared.

  As shown in FIG. 8, in the timer interruption process, a command reception process (S41), a button operation process (S42) by an effect button operation, and a command transmission process (S43) are sequentially executed. In the command reception process of S41, the special figure determination information obtained from the special figure hold increase command received from the game control board 22 is analyzed, and based on the content of the analyzed special figure determination information, the symbol variation effect selection process, A jackpot effect selection process is executed, and a command including information such as a symbol effect and a jackpot effect is set. The set command is transmitted to the image control board 25 and the lamp control board 26 by the command transmission process of S43.

  As shown in FIG. 9, in the trap process, an infinite loop process is executed in which only the instruction process of S51 is repeatedly executed until a RESET signal is transmitted from the WDT circuit 29 to the CPU 24a.

The operation and effect of the pachinko gaming machine 1 according to the embodiment described above will be described.
The CPU 24a of the effect control board 24 enters a runaway state due to the influence of external noise or the like. For example, after sequentially executing the processing routines stored in the continuous address areas a to d of the program area shown in FIG. When entering the address area h of the empty area following the data area, jumping from the address area c of the data area to the address area i of the empty area, entering the address area j of the empty area following the address area g of the data area. In this case, when jumping from the address area f in the data area to the address area k in the empty area, the trap routine is executed.

  Once the CPU 24a enters the trap routine and starts executing the instruction processing in the trap routine, only the instruction processing in the routine is repeated, and the trap routine is exited until a reset signal is output from the WDT circuit 29 to the CPU 24a. I can't do that. That is, when the trap routine is executed, the progress of the presentation control / processing of the CPU 24a is interrupted, so the output of the WDTCLR signal from the CPU 24a to the WDT circuit 29 is stopped, and the output stop of the WDTCLR signal is stopped for a predetermined time. Subsequently, the count value of the count unit 29a of the WDT circuit 29 is incremented, and a RESET signal is output from the CPU reset circuit 29b to the CPU 24a for a predetermined time, forcibly resetting the CPU 24a. Therefore, when the CPU 24a of the effect control board 24 is not operating normally, it is possible to avoid the adverse effect that the reset process of the CPU 24a is not executed by the WDT circuit 29 and to avoid the runaway state of the CPU 24a in a short time. Can do.

  The trap routine is stored in an empty area following the address area at the end of the program area and an empty area following the address area at the end of the data area. Therefore, when the CPU 24a of the effect control board 24 is not operating normally, it is possible to reliably avoid the adverse effect that the reset process of the CPU 24a of the WDT circuit 29 is not executed.

In addition, you may change an Example as follows.
(1) The trap routine may be stored in the empty areas of the ROM 25a of the image control board 25 and the ROM 26a of the lamp control board 26.
(2) The trap routine may be stored in all the empty areas of the ROM 24a.
(3) In addition, various modifications can be made without departing from the spirit of the present invention, and the present invention can be applied to various pachinko gaming machines.

1 Pachinko machine 22 Game control board 24 Production control board 24a CPU
24b ROM
29 WDT circuit

Claims (1)

In a gaming machine comprising a game control means for controlling a game and an effect control means for receiving information from the game control means and controlling the effect,
The production control means includes
Non-volatile storage means storing a production control program;
Arithmetic processing means for periodically executing various control processing routines constituting the effect control program stored in the non-volatile storage means and outputting a reset signal periodically;
A reset signal that monitors the reset signal output from the arithmetic processing means, and resets the arithmetic processing means when the reset signal is not periodically output;
The nonvolatile storage means includes
A program area storing the various control processing routines assigned to addresses used when the arithmetic processing means is operating normally;
A data area storing data necessary for executing the various control processing routines;
An abnormal time program area that stores a trap routine assigned to an address that is not used when the arithmetic processing means is operating normally;
The trap routine is a loop process different from the loop process that is executed when the arithmetic processing unit is operating normally, and is an abnormality that cannot be executed when the arithmetic processing unit is operating normally It is a process for limiting the output of the reset signal by the arithmetic processing means by executing a loop process dedicated to time,
The arithmetic processing means limits the output of the reset signal by executing the trap routine, and does not execute the various control processing routines until the arithmetic processing means is reset by the reset means. A gaming machine.