JP2015115470A - Ceramic wiring board and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a ceramic wiring board the reliability of which can be enhanced by suppressing occurrence of peeling of an electrode pad, and to provide a manufacturing method therefor.SOLUTION: A ceramic wiring board 11 includes a substrate body 23 formed planarly by using a ceramic material so as to have a substrate principal surface 21, and an electrode pad 24 arranged on the substrate principal surface 21. On the substrate principal surface 21 side, a power semiconductor element to be connected electrically with the electrode pad 24 can be mounted. The electrode pad 24 is constituted to include a thin film layer 41, a copper layer 51 and a coating layer 61. The thin film layer 41 is formed on the substrate principal surface 21, and the copper layer 51 is formed entirely on the upper surface 44 of the thin film layer 41. The coating layer 61 is principally composed of copper and an inorganic material of the same type as the ceramic material composing the substrate body 23, and connected with the substrate principal surface 21 while covering the outer periphery of the upper surface 52 of the copper layer 51 and the side face 53 thereof.

Description

  The present invention relates to a ceramic wiring board in which electrode pads are arranged on a main surface of a board and a method for manufacturing the same.

  In power conversion devices (inverters and DC-DC converters) such as devices that pass large currents, power semiconductor elements for power are used, and the power semiconductor elements are used in a state of being mounted on a ceramic wiring board. (For example, refer to Patent Document 1). In the ceramic wiring board of Patent Document 1, a conductor layer (circuit pattern) and a via conductor (main power straight via) for flowing an input current and an output current of a semiconductor element are formed. The via conductor is a through conductor extending in the thickness direction of the substrate so that the front surface side on which the semiconductor element is mounted and the back surface side thereof are electrically connected, and a conductive material such as silver, copper, tungsten, or molybdenum is used. It is formed using. Furthermore, electrode pads (upper surface wiring and lower surface wiring) connected to the end surfaces of the via conductors are respectively formed on the front surface and the back surface of the substrate.

  In the ceramic wiring board as described above, the thickness of the electrode pad cannot be neglected. That is, when the electrode pad is thin (see, for example, Patent Document 2), the electrical resistance and the heat generation amount of the electrode pad are increased, so that a large thermal stress is applied to the ceramic wiring substrate. Therefore, the electrode pad is desirably formed thick (specifically, 50 μm or more). As a specific method, for example, it is conceivable to form a thick electrode pad by plating.

JP2013-70018A (FIG. 1 etc.) JP 2002-185108 A (FIG. 1 etc.)

  By the way, a power semiconductor element using a conventional silicon device is generally used in a temperature range of 180 ° C. or lower because the durability temperature of the silicon device itself is low. On the other hand, a power semiconductor element using a silicon carbide device or the like is used in a high temperature range of about 50 ° C. to 300 ° C. because the durability temperature of the device is high. Moreover, it may become low temperature in the environment (use in a cold region) used. Therefore, a large thermal stress is repeatedly applied to the ceramic wiring substrate on which the semiconductor element used at a high temperature is mounted when the semiconductor element is turned on and off. Therefore, when the electrode pad is formed thick in such a ceramic wiring board, the electrode pad is peeled off due to internal stress (tensile stress) generated in the electrode pad or stress caused by a difference in thermal expansion between the electrode pad and the ceramic wiring board. There is a concern that this may occur.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a ceramic wiring board capable of improving reliability by suppressing occurrence of peeling of electrode pads and a method for manufacturing the same. There is to do.

  And as a means (means 1) for solving the above-mentioned problem, a substrate body formed in a plate shape having a substrate main surface using a ceramic material, and an electrode pad disposed on the substrate main surface are provided. A ceramic wiring substrate on which a power semiconductor element electrically connected to the electrode pad can be mounted on the substrate main surface side, the electrode pad comprising a thin film layer formed on the substrate main surface; A copper layer formed on the entire upper surface of the thin film layer, and copper and an inorganic material of the same kind as the ceramic material constituting the substrate body, and covers the outer peripheral portion and side surfaces of the copper layer. In addition, there is a ceramic wiring board including a covering layer connected to the main surface of the board.

  Therefore, according to the invention described in the means 1, the covering layer that constitutes the electrode pad covers the upper surface of the copper layer that also constitutes the electrode pad, and is connected to the substrate main surface of the substrate body. For this reason, even if the electrode pad is likely to be peeled off due to the stress caused by the difference in thermal expansion from the substrate body, the peeling of the electrode pad is suppressed by pressing the coating layer from the upper surface side of the copper layer. In addition, since the coating layer includes the same kind of inorganic material as the ceramic material that constitutes the substrate body, it becomes easy to become familiar with the substrate body. As a result, the coating layer is easily adhered to the substrate body, so that the electrode pad can be reliably reinforced. Therefore, the reliability of the ceramic wiring board can be improved.

  The substrate body constituting the ceramic wiring substrate is formed in a plate shape having a substrate main surface using a ceramic material. As the ceramic material constituting the substrate body, a sintered body of high-temperature fired ceramic such as aluminum oxide (alumina), aluminum nitride, boron nitride, silicon carbide, silicon nitride or the like is preferably used. Alternatively, a sintered body of low-temperature fired ceramic such as glass ceramic obtained by adding an inorganic ceramic filler such as alumina to borosilicate glass or lead borosilicate glass may be used.

  The substrate body is formed by laminating a plurality of ceramic layers provided with via conductor portions, and the via conductors are configured by connecting the plurality of via conductor portions in the stacking direction of the ceramic layers. The part may be arranged coaxially in the stacking direction of the ceramic layers. Here, the via conductor is not particularly limited, but may be a metallized conductor, for example. When the metallized conductor and the ceramic layer (substrate body) are formed by the simultaneous firing method, the metal powder in the metallized conductor needs to have a melting point higher than the firing temperature of the ceramic layer. For example, when the ceramic layer is made of a so-called high-temperature fired ceramic (eg, alumina), nickel (Ni), tungsten (W), molybdenum (Mo), manganese (Mn), or the like is used as the metal powder in the metallized conductor. The mixed system can be selected. When the ceramic layer is made of a so-called low-temperature fired ceramic (for example, glass ceramic), copper (Cu), silver (Ag), or a mixed system thereof can be selected as the metal powder in the metallized conductor.

  The power semiconductor element may be a power semiconductor element that generates heat to a temperature of 200 ° C. or higher when a current of 10 A or more flows. In a ceramic wiring board on which a power semiconductor element is mounted, thermal stress during use increases. In this ceramic wiring board, even if the internal stress generated in the electrode pad or the stress due to the thermal expansion difference between the electrode pad and the ceramic wiring board increases as the thermal stress increases, the coating layer Thus, peeling of the electrode pad can be reliably suppressed.

  A passive component electrically connected to an electrode pad disposed on the back surface of the substrate may be mounted on the back surface side of the substrate that is located on the opposite side of the main surface of the substrate. As described above, when the power semiconductor element is mounted on the substrate main surface side of the substrate body, the substrate main surface side is at a high temperature. In this case, if passive components with relatively low heat resistance (electronic components such as capacitors and resistors) are mounted on the back side of the board, the heat on the main board side is directly transferred to the back side of the board due to the heat insulating effect of the ceramic wiring board. Therefore, it is possible to suppress the performance deterioration due to the heat of the passive component.

  A ceramic package is constituted by the ceramic wiring board of means 1 and the power semiconductor element mounted on the main surface side of the ceramic wiring board. In this ceramic package, peeling of the electrode pad can be suppressed, so that product reliability can be improved.

  The electrode pads constituting the ceramic wiring substrate cover the thin film layer formed on the main surface of the substrate, the copper layer formed on the entire upper surface of the thin film layer, and the outer peripheral portion and side surfaces of the upper surface of the copper layer. And a coating layer connected to the main surface of the substrate. Here, although it does not specifically limit as a thin film layer, When a copper layer is a copper plating layer, what can function as a plating catalyst is good. As a material for forming the thin film layer, one or more metals selected from titanium (Ti), copper (Cu), molybdenum (Mo), chromium (Cr), tantalum (Ta), and palladium (Pd) are used. And the like. Further, the thickness of the thin film layer is not particularly limited, but in any case of a single layer or a multilayer, it is preferably 0.1 μm or more and 1 μm or less.

  Furthermore, although the thickness of a copper layer is not specifically limited, For example, it is good that they are 50 micrometers or more and 100 micrometers or less. If the thickness of the copper layer is less than 50 μm, the electrode pad becomes too thin, so that the electrical resistance and heat generation of the electrode pad increase, and a large thermal stress is applied to the ceramic wiring board. On the other hand, when the thickness of the copper layer is larger than 100 μm, the electrode pad becomes too thick, so that the internal stress (tensile stress) generated in the electrode pad and the stress caused by the thermal expansion difference between the electrode pad and the ceramic wiring substrate May cause peeling of the electrode pad.

  The coating layer is mainly composed of copper and an inorganic material of the same kind as the ceramic material constituting the substrate body. Here, as the same kind of inorganic material as the ceramic material constituting the substrate body, the ceramic material constituting the substrate body is a high-temperature fired ceramic such as aluminum oxide (alumina), aluminum nitride, boron nitride, silicon carbide, silicon nitride, or the like. In this case, a ceramic material classified as the above-mentioned high-temperature fired ceramic is cited. When the ceramic material constituting the substrate body is a low-temperature fired ceramic such as glass ceramic, the glass classified as the above-mentioned low-temperature fired ceramic. And other ceramic materials. The coating layer may be in close contact with the upper surface outer peripheral portion and the side surface of the copper layer. In this case, since the contact area between the coating layer and the copper layer increases, the electrode pad can be more reliably reinforced.

  As another means (means 2) for solving the above-mentioned problem, there is provided a method for manufacturing a ceramic wiring substrate according to the above means 1, wherein a thin film layer forming step of forming the thin film layer on the main surface of the substrate, A copper layer forming step of performing copper plating to form the copper layer on the thin film layer, and applying a paste containing the copper and the inorganic material on the surface of the copper layer, followed by firing, There is a method for manufacturing a ceramic wiring board including a coating layer forming step of forming a coating layer.

  Therefore, according to the invention described in the means 2, by performing the coating layer forming step, the coating layer that covers the upper surface of the copper layer and is connected to the substrate main surface of the substrate body is formed. For this reason, even if the electrode pad is likely to be peeled off due to the stress caused by the difference in thermal expansion from the substrate body, the peeling of the electrode pad is suppressed by pressing the coating layer from the upper surface side of the copper layer. Therefore, the reliability of the ceramic wiring board can be improved. In the coating layer forming step, since the coating layer is formed by applying the paste to the surface of the copper layer, a thick coating layer can be easily formed. When the thickness of the coating layer is increased, the coating layer becomes heavier, so that the force for pressing the upper surface side of the copper layer is increased by the weight of the coating layer. As a result, peeling of the electrode pad is more effectively suppressed.

  Hereinafter, a method for manufacturing a ceramic wiring board will be described.

  In the thin film layer forming step, a thin film layer is formed on the main surface of the substrate. The formation method of a thin film layer is not specifically limited, The conventionally well-known metal thin film formation method is employable. Specific examples thereof include sputtering, ion plating, and CVD.

  In the subsequent copper layer forming step, copper plating is performed to form a copper layer on the thin film layer. In the subsequent coating layer forming step, the coating layer is formed by applying a paste containing copper and an inorganic material on the surface of the copper layer and then baking the paste. Examples of the paste application method include a screen printing method. In the coating layer forming step, the coating layer may be formed by applying a paste to the upper surface outer peripheral portion and the side surface of the copper layer. In this way, the formed coating layer suppresses the movement of the electrode pad upward and in the plane direction by being in close contact with the outer peripheral portion and the side surface of the upper surface of the copper layer. It can be surely suppressed.

  In addition, a surface metal layer is formed on the upper surface of the copper layer and on the surface of the coating layer by performing any one of palladium plating, nickel-gold plating, and nickel-palladium-gold plating after the coating layer forming step. You may further implement a surface metal layer formation process.

Sectional drawing which shows schematic structure of the ceramic package in this embodiment. The principal part sectional drawing which shows a ceramic wiring board. The principal part top view which shows a ceramic wiring board. Explanatory drawing which shows a thin film layer formation process. Explanatory drawing which shows a resist formation process. Explanatory drawing which shows a copper layer formation process. Explanatory drawing which shows a resist removal process. Explanatory drawing which shows the process of removing the unnecessary part of a thin film layer. Explanatory drawing which shows a coating layer formation process. The principal part sectional view showing the ceramic wiring board in other embodiments.

  Hereinafter, an embodiment embodying the present invention will be described in detail with reference to the drawings.

  As shown in FIG. 1, a ceramic package 10 is a power module used for a power converter (for example, an inverter) in an automobile or the like, and includes a ceramic wiring board 11, a power semiconductor element 12, a passive component 13 (capacitor, resistor, etc.). Low heat-generating component), a heat radiating substrate 14, a heat radiator 15 and the like.

  The ceramic wiring substrate 11 includes a substrate body 23 formed in a plate shape having a substrate main surface 21 (lower surface in FIG. 1) and a substrate back surface 22 (upper surface in FIG. 1), and a main surface disposed on the substrate main surface 21. A side electrode pad 24, a back side electrode pad 25 disposed on the back side 22 of the substrate, and a power via array 28 including a plurality of via conductors 27 connecting the main side electrode pad 24 and the back side electrode pad 25. Prepare. The ceramic wiring board 11 has a rectangular shape in plan view of 28 mm length × 20 mm width × 1.0 mm thickness.

  On the substrate main surface 21 side of the substrate body 23, the power semiconductor element 12 that is electrically connected to the main surface side electrode pad 24, the back surface side electrode pad 25, and the plurality of via conductors 27 is mounted. Further, the passive component 13 that is electrically connected to the main surface side electrode pad 24, the back surface side electrode pad 25, and the plurality of via conductors 27 is mounted on the substrate back surface 22 side of the substrate body 23. Note that a power input / output bus bar (not shown) is also mounted on the substrate back surface 22 of the substrate body 23. The power semiconductor element 12 is, for example, a power semiconductor element (power device) such as a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or a diode (Schottky barrier diode). A large current of, for example, about 50 A flows through the power semiconductor element 12 and heat is generated at a temperature of about 250 ° C. at that time.

  As shown in FIG. 1, the heat dissipation substrate 14 includes an insulating substrate made of ceramic, and is provided on the lower surface of the ceramic wiring substrate 11 (the substrate main surface 21 of the substrate body 23) via a bonding portion made of a glass sheet. Yes. The radiator 15 is made of a metal (for example, aluminum) having excellent thermal conductivity, and is fixed to the lower surface of the heat radiating substrate 14 using a plurality of screws (not shown). The heat radiator 15 is provided with a plurality of fins (not shown) for increasing the surface area, so that the heat radiation performance of the heat radiator 15 is enhanced.

  The substrate body 23 is a sintered body formed by laminating a plurality of (two layers in this embodiment) ceramic layers 32 provided with via conductor portions 31 and conductor layers 33. The via conductor 27 is configured by connecting two via conductor portions 31 in the stacking direction of the ceramic layers 32. Each via conductor portion 31 is arranged coaxially in the stacking direction of the ceramic layers 32.

As shown in FIG. 1, each ceramic layer 32 is formed using alumina (Al ₂ O ₃ ), which is a ceramic material. The conductor layer 33 provided between the ceramic layers 32 is made of, for example, a metallized layer of tungsten, molybdenum, or an alloy thereof. The conductor layer 33 includes a control circuit wiring for transmitting a drive signal for the power semiconductor element 12. Each via conductor 27 (via conductor portion 31) is also made of a metallized layer of tungsten, molybdenum, or an alloy thereof, like the conductor layer 33.

  The ceramic wiring board 11 of the present embodiment is provided with a plurality of via arrays 28, and currents flow in different directions in the two adjacent via arrays 28, respectively. For example, in the via array 28 located on the right side in FIG. 1, current flows from the lower side (substrate main surface 21 side) to the upper side (substrate rear surface 22 side), and in the via array 28 located on the left side in FIG. A current flows through the. The plurality of via conductors 27 constituting each via array 28 are straight vias for main power that extend linearly in the thickness direction of the substrate body 23. Each via conductor 27 has a circular cross section and a diameter of 200 μm. Further, the distance between adjacent via conductors 27 is 300 μm.

  The main surface side electrode pad 24 and the back surface side electrode pad 25 shown in FIGS. 1 to 3 include a conductor layer made of copper. Each electrode pad 24, 25 has a rectangular shape in plan view. The vertical and horizontal lengths of the electrode pads 24 and 25 are about 4 mm × 7 mm, and the thicknesses of the electrode pads 24 and 25 are about 100 μm. In the present embodiment, circuit patterns and component mounting pads (not shown) are arranged as conductor layers other than the electrode pads 24 and 25 on the substrate main surface 21 and the substrate back surface 22.

  The main surface side electrode pad 24 and the back surface side electrode pad 25 include a thin film layer 41, a copper plating layer 51 (copper layer), and a coating layer 61. The thin film layer 41 has a function of improving the adhesion between the substrate body 23 (ceramic layer 32) and the copper plating layer 51 formed on the thin film layer 41. The thin film layer 41 is composed of a first thin film layer 42 (thickness 0.2 μm) made of titanium and a second thin film layer 43 (thickness 0.5 μm) made of copper, and the total thickness is 0.7 μm. (See FIG. 2). The first thin film layer 42 is formed on the substrate main surface 21, and the second thin film layer 43 is formed on the upper surface of the first thin film layer 42. The thin film layer 41 may be constituted by a first thin film layer made of titanium, a second thin film layer made of molybdenum, and a third thin film layer made of copper.

  As shown in FIGS. 1 to 3, the copper plating layer 51 is formed on the entire upper surface 44 of the thin film layer 41. In the case of this embodiment, the copper plating layer 51 is a plating layer formed by electrolytic copper plating, and the thickness thereof is set to 50 μm or more and 100 μm or less (in this embodiment, 100 μm).

  The covering layer 61 covers the outer peripheral portion of the upper surface 52 of the copper plating layer 51 and the four side surfaces 53 of the copper plating layer 51 and is connected to the substrate main surface 21. More specifically, the covering layer 61 is in close contact with the outer peripheral portion of the upper surface 52 and the side surfaces 53 of the copper plating layer 51 and in close contact with the substrate main surface 21. In the case of the present embodiment, the coating layer 61 is made of copper, which is the same material as that constituting the copper plating layer 51, and alumina, which is the same kind of inorganic material as the ceramic material constituting the substrate body 23 (ceramic layer 32). It is a layer configured as a subject.

  As shown in FIGS. 2 and 3, the covering layer 61 includes a side surface covering portion 62 and an upper surface covering portion 63. The side surface covering portion 62 has a rectangular ring shape in plan view, and the inner side surface is in close contact with the four side surfaces 53 of the copper plating layer 51 and the lower end surface is in close contact with the substrate main surface 21. Further, the side surface covering portion 62 has a shape that gradually becomes thicker from the upper end surface toward the lower end surface. The thickness of the side surface covering portion 62 at the upper end is set to 10 μm or more and 30 μm or less (20 μm in this embodiment), and the thickness of the side surface covering portion 62 at the lower end is 30 μm or more and 50 μm or less (30 μm in this embodiment). Is set to

  On the other hand, the upper surface covering portion 63 has a shape projecting from the outer peripheral edge of the upper surface 52 of the copper plating layer 51 (in other words, the upper end portion of the side surface covering portion 62) toward the center of the upper surface 52. As a result, the coating layer 61 is formed with an opening 64 that exposes the central portion of the upper surface 52 of the copper plating layer 51, and the upper end portions of the main surface side electrode pad 24 and the back surface side electrode pad 25 are entirely formed. As shown in FIG. The overhanging amount of the upper surface covering portion 63 is set to 100 μm or more and 300 μm or less (200 μm in this embodiment), and the thickness of the upper surface covering portion 63 is set to 10 μm or more and 50 μm or less (10 μm in this embodiment). ing. The opening 64 has a rectangular shape in plan view with a vertical and horizontal length of about 4 mm × 7 mm.

  As shown in FIG. 2, a surface metal layer 71 is formed on a portion exposed from the opening 64 on the upper surface 52 of the copper plating layer 51 and a portion exposed to the outside on the surface of the coating layer 61. Yes. The surface metal layer 71 is a plating layer (thickness: about 6 μm) formed by electrolytic nickel plating and electrolytic gold plating. The surface metal layer 71 may be a plating layer formed by electrolytic palladium plating.

  Next, a method for manufacturing the ceramic wiring substrate 11 will be described.

  A plurality of green sheets are formed using a ceramic material mainly composed of alumina powder. Then, laser processing is performed on the plurality of green sheets to form a plurality of through holes at predetermined positions. The through hole may be formed by punching, drilling, or the like.

  Thereafter, using a conventionally known paste printing device (not shown), the through hole of each green sheet is filled with a conductive paste (for example, tungsten paste or molybdenum paste) to form an unfired via conductor portion that becomes the via conductor 27. 31 is formed. Furthermore, the conductive paste 33 is printed using a conventionally known paste printing apparatus to form the unfired conductor layer 33.

  Then, after the conductive paste is dried, the plurality of green sheets are stacked and disposed, and a pressing force is applied in the sheet stacking direction, whereby the green sheets are pressed and integrated to form a ceramic laminate. Next, the ceramic laminate is degreased and fired at a predetermined temperature for a predetermined time. As a result, the alumina of the green sheet and the tungsten in the paste are simultaneously sintered, and the substrate body 23 having the via conductor 27 and the conductor layer 33 is formed.

  Next, the main surface side electrode pad 24 is formed on the substrate main surface 21 of the substrate body 23, and the back surface side electrode pad 25 is formed on the substrate back surface 22 of the substrate body 23. More specifically, first, a thin film layer forming step is performed to form thin film layers 41 on the substrate main surface 21 and the substrate back surface 22 (see FIG. 4). Specifically, the first thin film layer 42 made of titanium is formed on the substrate main surface 21 and the substrate back surface 22, respectively. Next, a second thin film layer 43 made of copper is formed on the upper surface of the first thin film layer 42. The first thin film layer 42 and the second thin film layer 43 are formed by sputtering.

  In the subsequent resist formation step, a plating resist 80 having an opening 81 is formed on the thin film layer 41 (see FIG. 5). Specifically, a plating film 80 having an opening 81 is formed by laminating a dry film having a thickness of 150 μm on the surface of the thin film layer 41 and exposing and developing the dry film.

  In the subsequent copper layer forming step, copper plating is performed to form a copper plating layer 51 on the thin film layer 41. Specifically, electrolytic copper plating is performed with a copper sulfate solution. As a result, the copper plating layer 51 is formed in the opening 81 (see FIG. 6).

  In the subsequent resist removal step, the plating resist 80 is removed (see FIG. 7). Specifically, the plating resist 80 is stripped using a NaOH stripping solution (3% by volume or more, 45 ° C. or more). Next, by etching the substrate main surface 21 and the substrate back surface 22 of the substrate body 23, a portion of the thin film layer 41 where the copper plating layer 51 is not formed is removed (see FIG. 8).

  In the subsequent coating layer forming step, a coating layer 61 is formed by applying a paste containing copper and alumina (inorganic material) onto the surface of the copper plating layer 51 and then baking the paste (see FIG. 9). Specifically, first, a paste for forming the coating layer 61 is applied to the outer peripheral portion and the side surface 53 of the upper surface 52 of the copper plating layer 51 using a conventionally known dispenser or screen printing apparatus. Next, the baking process heated to the predetermined | prescribed temperature (for example, 700 to 900 degreeC) which copper can sinter is performed. After this firing, the copper in the paste is sintered and the coating layer 61 is obtained.

  Thereafter, a surface metal layer forming step is performed, and electrolytic nickel plating and electrolytic gold plating are performed, so that the surface exposed from the opening 64 on the upper surface 52 of the copper plating layer 51 and the surface of the coating layer 61 are exposed to the outside. A surface metal layer 71 is formed on the portion to be formed (see FIG. 2). The ceramic wiring board 11 is manufactured through the above steps.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) In the ceramic wiring substrate 11 of the present embodiment, the coating layer 61 that constitutes the electrode pads 24 and 25 covers the upper surface 52 of the copper plating layer 51 that also constitutes the electrode pads 24 and 25, and It is connected to the substrate main surface 21 and the substrate back surface 22. For this reason, even if the electrode pads 24 and 25 are likely to be peeled off due to the stress caused by the difference in thermal expansion from the substrate main body 23, the covering layer 61 is pressed from the upper surface 52 side of the copper plating layer 51, thereby Peeling of 24 and 25 is suppressed. Therefore, the reliability of the ceramic wiring board 11 can be improved.

  (2) In the present embodiment, the power semiconductor element 12 mounted on the ceramic wiring substrate 11 is a power semiconductor element that generates heat to a temperature of 200 ° C. or higher when a current of 10 A or more flows. In the ceramic wiring substrate 11 on which such a power semiconductor element 12 is mounted, thermal stress during use becomes large, but by providing the covering layer 61 as described above, the electrode pads 24 and 25 are surely peeled off. Can be suppressed.

  (3) The electrode pads 24 and 25 of the present embodiment are connected to the ceramic wiring substrate 11 via the coating layer 61 that is in close contact with the upper surface 52 and the side surface 53 of the copper plating layer 51. And the side surface covering part 62 of the covering layer 61 has a shape that gradually becomes thicker from the upper end toward the lower end. As a result, the contact area between the coating layer 61 and the ceramic wiring board 11 is increased, and thus sufficient connection strength with the ceramic wiring board 11 can be ensured. Further, by forming the covering layer 61, it is possible to relieve the stress caused by the difference in thermal expansion between the electrode pads 24, 25 and the substrate body 23.

  (4) In the present embodiment, since the coating layer 61 constituting the electrode pads 24 and 25 contains a ceramic material (alumina), the coating layer 61 is composed of other portions of the electrode pads 24 and 25 (thin film layer 41). Or the copper plating layer 51). Therefore, in the present embodiment, the opening 64 that exposes the copper plating layer 51 is formed on the surface (upper surface) where the bumps of the power semiconductor element 12 and the passive component 13 can come into contact with the electrode pads 24 and 25 (covering layer 61). Provided. For this reason, even when the coating layer 61 having a relatively large electric resistance is provided, the path connecting the main surface side electrode pad 24 and the power semiconductor element 12 or the back side electrode pad 25 and the passive component 13 is connected. The electrical resistance of the path can be kept low. Moreover, since the coating layer 61 contains the same ceramic material (alumina) as the ceramic material constituting the substrate body 23, the difference in thermal expansion from the substrate body 23 is small. As a result, the covering layer 61 is easily adhered to the substrate body 23, so that the electrode pads 24 and 25 can be reliably reinforced. Further, since the coating layer 61 has high hardness due to containing alumina, a portion that is an edge in the coating layer 61 (specifically, a connection portion between the side surface coating portion 62 and the head portion 63) is not easily deformed. Become.

  (5) In the present embodiment, the opening 64 is formed in the covering layer 61 of the electrode pads 24 and 25. For this reason, the bumps of the power semiconductor element 12 and the passive component 13 are bonded onto the electrode pads 24 and 25 while entering the opening 64. As a result, the bumps are prevented from being displaced due to the bumps coming into contact with the surface of the surface metal layer 71 that covers the inner surface of the opening 64, so that poor connection between the electrode pads 24 and 25 and the bumps can be prevented. it can. That is, the reliability of the ceramic wiring substrate 11 can be improved by providing the electrode pads 24 and 25 suitable for connection to the bumps.

  In addition, you may change this embodiment as follows.

  In the electrode pads 24 and 25 of the above embodiment, the coating layer 61 is in close contact with the outer peripheral portion of the upper surface 52 and the side surface 53 of the copper layer 51. However, as shown in the ceramic wiring substrate 91 of FIG. 10, the electrode pad 96 may be such that the covering layer 92 is in close contact with only the outer peripheral portion of the upper surface 95 of the copper plating layer 93 (copper layer). That is, there may be a gap between the coating layer 92 and the side surface 94 of the copper plating layer 93. The covering layer 92 may have a gap between the upper surface 95 of the copper plating layer 93 in addition to the gap between the side surface 94 of the copper plating layer 93.

  -In the said embodiment, both the main surface side electrode pad 24 and the back surface side electrode pad 25 are thick (50 micrometers or more) formed the copper plating layer 51, and the upper surface 52 outer peripheral part and the side surface 53 of the copper plating layer 51. The cover layer 61 is configured to be covered and connected to the substrate main surface 21. However, only the main surface side electrode pad 24 may be configured to include the copper plating layer 51 and the coating layer 61 described above.

  In the above embodiment, the via conductor 27 is configured by connecting the two via conductor portions 31 in the stacking direction of the ceramic layers 32. However, the via conductor 27 may be a single conductor extending from the substrate main surface 21 of the substrate body 23 to the substrate back surface 22.

  Next, in addition to the technical ideas described in the claims, the technical ideas grasped by the embodiment described above are listed below.

  (1) In the above means 1, the covering layer includes an upper surface covering portion that protrudes from the outer peripheral edge of the upper surface of the copper layer toward the center of the upper surface of the copper layer, and the amount of protrusion of the upper surface covering portion is A ceramic wiring board characterized by being 100 μm or more and 300 μm or less.

  (2) In the above means 1, the covering layer includes an upper surface covering portion that projects from the outer peripheral edge of the upper surface of the copper layer toward the upper surface central portion of the copper layer, and the thickness of the upper surface covering portion is 10 μm. A ceramic wiring board having a thickness of 50 μm or less.

  (3) The ceramic wiring board according to the above means 1, wherein the coating layer has an opening for exposing a central portion of the upper surface of the copper layer, and the electrode pad has a concave cross section.

  (4) In the above means 1, the power semiconductor element is a power semiconductor element that generates heat at a temperature of 200 ° C. or higher.

  (5) In the above means 1, the power semiconductor element is a power semiconductor element in which a current of 10 A or more flows.

  (6) In the above means 1, the substrate body is formed by laminating a plurality of ceramic layers provided with via conductors, and the via conductors are arranged in the laminating direction of the ceramic layers. A ceramic wiring board comprising: a plurality of via conductor portions arranged coaxially in a stacking direction of the ceramic layers.

  (7) In the said means 2, the surface which forms a surface metal layer on the upper surface of the said copper layer, and the surface of the said coating layer by performing palladium plating or nickel-gold plating after the said coating layer formation process A method for producing a ceramic wiring board, comprising performing a metal layer forming step.

  (8) A ceramic wiring board comprising a substrate body formed in a plate shape having a substrate main surface using a ceramic material, and an electrode pad disposed on the substrate main surface, and mounted on the substrate main surface side A ceramic package comprising a power semiconductor element electrically connected to the electrode pad, wherein the electrode pad is formed on a main surface of the substrate and on a whole upper surface of the thin film layer. The copper layer is formed mainly of copper and an inorganic material of the same kind as the ceramic material constituting the substrate body, and covers the outer peripheral surface and the side surface of the upper surface of the copper layer and is connected to the main surface of the substrate. A ceramic package comprising a coating layer.

DESCRIPTION OF SYMBOLS 11,91 ... Ceramic wiring board 12 ... Power semiconductor element 21 ... Substrate main surface 23 ... Substrate body 24 ... Main surface side electrode pad 41 as electrode pad ... Thin film layer 44 ... Upper surface 51, 93 of thin film layer As copper layer Copper plating layers 52, 95 ... Copper layer upper surfaces 53, 94 ... Copper layer side surfaces 61, 92 ... Cover layer 96 ... Electrode pad

Claims (5)

A power semiconductor device comprising a substrate body formed in a plate shape having a substrate main surface using a ceramic material, and an electrode pad disposed on the substrate main surface, and electrically connected to the electrode pad. A ceramic wiring board that can be mounted on the substrate main surface side,
The electrode pad is
A thin film layer formed on the substrate main surface;
A copper layer formed over the entire top surface of the thin film layer;
It is composed mainly of copper and an inorganic material of the same type as the ceramic material constituting the substrate body, and includes a coating layer that covers the upper surface outer peripheral portion and the side surface of the copper layer and is connected to the substrate main surface. A ceramic wiring board characterized by the above.   The thickness of the said copper layer is 50 micrometers or more and 100 micrometers or less, The ceramic wiring board of Claim 1 characterized by the above-mentioned.   3. The ceramic wiring board according to claim 1, wherein the coating layer is in close contact with an outer peripheral portion and a side surface of the upper surface of the copper layer. A method for manufacturing a ceramic wiring board according to any one of claims 1 to 3,
A thin film layer forming step of forming the thin film layer on the substrate main surface;
A copper layer forming step of performing copper plating to form the copper layer on the thin film layer;
And a coating layer forming step of forming the coating layer by baking the paste containing the copper and the inorganic material on the surface of the copper layer and then baking the paste. .   5. The method for manufacturing a ceramic wiring board according to claim 4, wherein, in the coating layer forming step, the coating layer is formed by applying the paste to an outer peripheral portion and a side surface of an upper surface of the copper layer.

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