JP6275990B2 - Ceramic wiring board - Google Patents

Description

  The present invention relates to a ceramic wiring board provided with a via conductor group composed of a plurality of via conductors connecting electrode pads on both sides of a board.

  In power conversion devices (inverters and DC-DC converters) such as devices that pass large currents, power semiconductor elements for power are used, and the power semiconductor elements are used in a state of being mounted on a ceramic wiring board. (For example, refer to Patent Document 1). In the ceramic wiring board of Patent Document 1, a conductor layer (circuit pattern) and a via conductor (main power straight via) for flowing an input current and an output current of a semiconductor element are formed. The via conductor described in Patent Document 1 is a through conductor extending in the thickness direction of the substrate so that the front surface side on which the semiconductor element is mounted and the back surface side thereof are electrically connected, and silver, copper, tungsten, molybdenum It is formed using a conductive material.

  In the ceramic wiring board, the thermal expansion coefficient differs between the ceramic layer and the via conductor. Further, when a large current flows through the via conductor, heat is generated by Joule heat. For this reason, there is a concern that cracks may occur due to stress caused by the difference in thermal expansion at the boundary between the via conductor and the ceramic layer. In addition, there is a ceramic wiring board configured to allow a current to flow through a via array (via conductor group) including a plurality of via conductors. In this ceramic wiring board, since the ceramic layer is interposed between the plurality of via conductors, it is possible to disperse the stress caused by the difference in thermal expansion.

JP 2013-70018 A

  A power semiconductor element using a conventional silicon device is generally used in a temperature range of 180 ° C. or lower because the durability temperature of the silicon device itself is low. On the other hand, a power semiconductor element using a silicon carbide device or the like is used in a high temperature range of about 50 ° C. to 300 ° C. because the durability temperature of the device is high. Moreover, it may become low temperature in the environment (use in a cold region) used. Therefore, a large thermal stress is repeatedly applied to the ceramic wiring board on which the semiconductor element used at a high temperature is mounted when the semiconductor element is turned on and off. In such a ceramic wiring board, even if the current is passed through a plurality of via conductors (via array), the stress is not sufficiently distributed, so that a crack is generated in the ceramic layer between the via conductors. There is a concern that the occurrence of such cracks may lead to poor connection between the conductor layer (circuit pattern) on the substrate surface and the via conductor, or damage to the circuit pattern itself.

  If the area ratio occupied by the via conductor is reduced in the via array formation region, the generated stress can be reduced, but in that case, the electrical resistance of the via conductor is increased. For this reason, in order to reduce the area ratio of the via conductors while keeping the electrical resistance of the entire via array small, it is necessary to increase the formation area of the via array in the ceramic wiring substrate. However, when downsizing of the ceramic wiring board is required, there is a problem that the formation area of the via array cannot be increased.

  The present invention has been made in view of the above problems, and an object thereof is to provide a ceramic wiring board having high product reliability by suppressing the occurrence of cracks between via conductors constituting a via conductor group. is there.

  As means (means 1) for solving the above-mentioned problems, a substrate body formed in a plate shape having a first surface and a second surface using a ceramic material, and a first body disposed on the first surface are used. Vias comprising a first surface side electrode pad, a second surface side electrode pad disposed on the second surface, and a plurality of via conductors connecting the first surface side electrode pad and the second surface side electrode pad A ceramic wiring having a conductor group and on which the power semiconductor element electrically connected to the first surface side electrode pad, the second surface side electrode pad, and the plurality of via conductors can be mounted on the first surface side The via conductor group includes a plurality of outer via conductors arranged on an outermost periphery and a plurality of inner via conductors surrounded by the plurality of outer via conductors. The plurality of via conductors constituting the group, There is a ceramic wiring substrate, wherein the thermal expansion coefficient difference between the substrate main body as is the periphery of the via conductor is small.

  Therefore, according to the first aspect of the invention, when driving the power semiconductor element, the plurality of via conductors constituting the via conductor group are connected to the first surface side electrode pads and the second surface side electrode pads. Current flows in the same direction, generating Joule heat. In addition, a current also flows through the power semiconductor element mounted on the first surface of the substrate body, and the semiconductor element generates heat. At this time, stress is generated in the via conductor group due to a difference in thermal expansion coefficient between the via conductor and the ceramic. Note that the stress is more remarkably generated in the outer peripheral portion than in the central portion of the via conductor group. In the ceramic wiring board of the present invention, in the same via conductor group, the thermal expansion coefficient difference from the board body is reduced as the via conductor on the outer peripheral side. In this way, since the stress generated in the region between the via conductors in the substrate body can be made uniform on the outer peripheral side and the inner peripheral side of the via conductor group, the stress applied to the entire via conductor group can be reduced. it can. As a result, in the ceramic wiring board, the frequency at which thermal stress is applied can be suppressed, and the occurrence of cracks between via conductors can be suppressed.

  Here, the via conductor group only needs to be provided so that a plurality of outer via conductors surround the plurality of inner via conductors. For example, each via conductor may be provided in a lattice shape or a staggered shape. Alternatively, each via conductor may be provided in an irregular arrangement state. As a specific example, the via conductor group may be a via array arranged in a lattice shape of 3 rows or more × 3 columns or more. By configuring the via array in this way, the generated stress due to the difference in thermal expansion coefficient between the via conductor and the ceramic can be reliably dispersed.

  In the same via conductor group, the thermal expansion coefficient of the outer via conductor may be larger than the thermal expansion coefficient of the inner via conductor, and the thermal expansion coefficient of the board body may be larger than the thermal expansion coefficient of the outer via conductor. The thermal expansion coefficient of the outer via conductor may be smaller than the thermal expansion coefficient of the inner via conductor, and the thermal expansion coefficient of the substrate body may be smaller than the thermal expansion coefficient of the outer via conductor. According to the above, in the same via conductor group, the difference in thermal expansion coefficient between the outer via conductor and the substrate body becomes smaller than the difference in thermal expansion coefficient between the inner via conductor and the substrate body. That is, as the via conductor on the outer peripheral side is, the difference in thermal expansion coefficient from the substrate body is surely reduced, and the stress generated in the area between the via conductors is surely uniform between the outer peripheral side and the inner peripheral side of the via conductor group. Therefore, the stress applied to the entire via conductor group can be surely alleviated.

  The power semiconductor element may be a power semiconductor element that generates heat to a temperature of 200 ° C. or higher when a current of 10 A or more flows. In a ceramic wiring board on which a power semiconductor element is mounted, thermal stress during use increases. In this ceramic wiring board, as the via conductor on the outer peripheral side as described above, the difference in thermal expansion coefficient from the board body is reduced and the stress generated in the entire via conductor group is reduced, thereby reducing cracks between the via conductors. Occurrence can be reliably prevented.

  The ceramic wiring board may include a plurality of via conductor groups having different current flowing directions. In this case, if a crack occurs so as to connect the via conductor groups, creeping discharge is likely to occur. On the other hand, the crack to the outer side of a via conductor group can be suppressed by relieving the generated stress in a via conductor group like this invention. For this reason, creeping discharge between a plurality of via conductor groups can be reliably avoided.

  In the ceramic wiring board, a passive component electrically connected to the first surface side electrode pad, the second surface side electrode pad, and the plurality of via conductors may be mounted on the second surface side of the substrate body. . As described above, when the power semiconductor element is mounted on the first surface of the substrate body, the first surface side is at a high temperature. In this case, when passive components (electronic components such as capacitors and resistors) having relatively low heat resistance are mounted on the second surface side, the heat on the first surface side is directly applied to the second surface side due to the heat insulating effect of the ceramic wiring board. Since it is not transmitted, the performance degradation due to the heat of the passive component can be kept low.

  The substrate body of the ceramic wiring board is formed by laminating a plurality of ceramic layers provided with via conductor portions, and the via conductor is configured by connecting the plurality of via conductor portions in the laminating direction of the ceramic layers. The via conductor portions may be arranged coaxially in the stacking direction of the ceramic layers.

  As the ceramic layer constituting the substrate body, a sintered body of high-temperature fired ceramic such as aluminum oxide (alumina), aluminum nitride, boron nitride, silicon carbide, silicon nitride or the like is preferably used. Alternatively, a sintered body of low-temperature fired ceramic such as glass ceramic obtained by adding an inorganic ceramic filler such as alumina to borosilicate glass or lead borosilicate glass may be used.

  Although it does not specifically limit as a via conductor and electrode pad which comprise a via conductor group, For example, a metallized conductor may be sufficient. When the metallized conductor and the ceramic layer are formed by the simultaneous firing method, the metal powder in the metallized conductor needs to have a melting point higher than the firing temperature of the ceramic layer. For example, when the ceramic layer is made of a so-called high-temperature fired ceramic (for example, alumina), nickel (Ni), tungsten (W), molybdenum (Mo), manganese (Mn), tantalum (metal powder in the metallized conductor) Ta), titanium (Ti), niobium (Nb), etc., or a mixed system thereof can be selected. When the ceramic layer is made of a so-called low-temperature fired ceramic (for example, glass ceramic), copper (Cu), silver (Ag), or a mixed system thereof can be selected as the metal powder in the metallized conductor.

  Each of the plurality of via conductors constituting the same via conductor group includes, as a metal material, two or more kinds of single metals, alloys or metal compounds having different thermal expansion coefficients, and the outer via conductors include two or more kinds of outer via conductors. The metal material having the largest thermal expansion coefficient among the metal materials may have the largest content, and the inner via conductor may have the largest content of the metal material having the smallest thermal expansion coefficient among the two or more types of metal materials. In this way, since the thermal expansion coefficient of the outer via conductor can be made larger than the thermal expansion coefficient of the inner via conductor, the thermal expansion coefficient of the substrate body is larger than the thermal expansion coefficient of the outer via conductor. The difference in the thermal expansion coefficient from the substrate body can be reduced as the via conductor on the outer peripheral side is located. Therefore, since the stress generated in the region between the via conductors can be made uniform on the outer peripheral side and the inner peripheral side of the via conductor group, the stress applied to the entire via conductor group can be surely reduced. Here, specific examples of the metal material include tungsten (thermal expansion coefficient: 4.6 ppm / K), molybdenum (thermal expansion coefficient: 5.7 ppm / K), tantalum (thermal expansion coefficient: 6.3 ppm / K), Examples thereof include two simple metals selected from titanium (thermal expansion coefficient: 8.5 ppm / K) and niobium (thermal expansion coefficient: 7.0 ppm / K).

  Furthermore, the plurality of via conductors constituting the same via conductor group include an inorganic filler having insulating properties, and the content of the inorganic filler in the outer via conductor and the content of the inorganic filler in the inner via conductor are different from each other. Also good. In this way, by changing the content of the inorganic filler between the outer via conductor and the inner via conductor, the thermal expansion coefficient of the outer via conductor and the thermal expansion coefficient of the inner via conductor can be made different, and thus The stress generated in the central portion (inner peripheral portion) and outer peripheral portion of the via conductor group can be adjusted. Further, the content of the inorganic filler in the outer via conductor may be larger than the content of the inorganic filler in the inner via conductor. In this way, since the thermal expansion coefficient of the outer via conductor can be made larger than the thermal expansion coefficient of the inner via conductor, the thermal expansion coefficient of the substrate body is larger than the thermal expansion coefficient of the outer via conductor. The difference in the thermal expansion coefficient from the substrate body can be reduced as the via conductor on the outer peripheral side is located. Therefore, since the stress generated in the region between the via conductors can be made uniform on the outer peripheral side and the inner peripheral side of the via conductor group, the stress applied to the entire via conductor group can be surely reduced.

  Here, although it does not specifically limit as an inorganic filler, For example, a ceramic filler (alumina etc.), a silica filler, a metal filler, a glass filler etc. are mentioned. The plurality of via conductors may include an inorganic filler made of the same material as the ceramic material constituting the substrate body. In this case, since the thermal expansion coefficient of the via conductor is easily brought close to the thermal expansion coefficient of the substrate body, the stress generated at the boundary portion between the via conductor and the substrate body can be surely relieved, and the via conductor caused by the stress The generation of cracks between them can be more reliably suppressed.

  A ceramic package is constituted by the ceramic wiring board of means 1 and the power semiconductor element mounted on the first surface side of the ceramic wiring board. In this ceramic package, since the generation of cracks in the ceramic wiring substrate can be suppressed, product reliability can be improved.

Sectional drawing which shows schematic structure of the ceramic package in this Embodiment. Sectional drawing in the AA in FIG. The expanded sectional view which shows a via array. Explanatory drawing which shows the via arrangement | positioning of the base model which is a prior art example. Explanatory drawing which shows the via arrangement | positioning of the model after a countermeasure. Explanatory drawing which shows the simulation result of the base model which is a prior art example. Explanatory drawing which shows the simulation result of the model after a countermeasure. The expanded sectional view which shows the via array in another embodiment which has arrange | positioned the via conductor in zigzag form.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a cross-sectional view showing a schematic configuration of a ceramic package 10 of the present embodiment, and FIG. 2 is a cross-sectional view taken along line AA in FIG.

  As shown in FIG. 1, a ceramic package 10 is a power module used for a power converter (for example, an inverter) in an automobile or the like, and includes a ceramic wiring board 11, a power semiconductor element 12, a passive component 13 (capacitor, resistor, etc.). Low heat-generating component), a heat radiating substrate 14, a heat radiator 15 and the like.

  The ceramic wiring board 11 includes a board body 23 formed in a plate shape having a first surface 21 (lower surface in FIG. 1) and a second surface 22 (upper surface in FIG. 1), and a first body 21 disposed on the first surface 21. The first surface side electrode pad 24, the second surface side electrode pad 25 disposed on the second surface 22, and a plurality of via conductors 27 connecting the first surface side electrode pad 24 and the second surface side electrode pad 25. Power via array 28 (via conductor group). The ceramic wiring board 11 has a rectangular shape in plan view of 28 mm length × 20 mm width × 1.0 mm thickness.

  In the ceramic wiring substrate 11, a power semiconductor element electrically connected to the first surface side electrode pad 24, the second surface side electrode pad 25, and the plurality of via conductors 27 on the first surface 21 side of the substrate body 23. 12 is mounted. Further, the passive component 13 that is electrically connected to the first surface side electrode pad 24, the second surface side electrode pad 25, and the plurality of via conductors 27 is mounted on the second surface 22 side of the substrate body 23. . In addition, a bus bar (not shown) for power input / output is also mounted on the second surface 22 of the substrate body 23. The power semiconductor element 12 is, for example, a power semiconductor element (power device) such as a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or a diode (Schottky barrier diode). A large current of, for example, about 50 A flows through the power semiconductor element 12 and heat is generated at a temperature of about 250 ° C. at that time.

  The heat dissipation substrate 14 includes an insulating substrate made of ceramic, and is provided on the lower surface of the ceramic wiring substrate 11 (the first surface 21 of the substrate body 23) via a joint portion made of a glass sheet. The radiator 15 is made of a metal (for example, aluminum) having excellent thermal conductivity, and is fixed to the lower surface of the heat radiating substrate 14 using a plurality of screws (not shown). The heat radiator 15 is provided with a plurality of fins (not shown) for increasing the surface area, so that the heat radiation performance of the heat radiator 15 is enhanced.

  The substrate body 23 of the ceramic wiring substrate 11 is a sintered body formed by laminating a plurality of (two layers in this embodiment) ceramic layers 32 provided with via conductor portions 31 and conductor layers 33. The via conductor 27 is configured by connecting two via conductor portions 31 in the stacking direction of the ceramic layers 32. Each via conductor portion 31 is arranged coaxially in the stacking direction of the ceramic layers 32.

Each ceramic layer 32 is formed using alumina (Al ₂ O ₃ ) as a ceramic material. The ceramic layer 32 has a thermal expansion coefficient of 7.6 ppm / K in the plane direction (XY direction). The thermal expansion coefficient of the ceramic layer 32 is a value obtained by converting the expansion amount when the temperature is increased from 0 ° C. to 400 ° C. into the expansion amount per unit temperature (thermal expansion coefficient = 0 when the temperature is increased from 0 ° C. to 400 ° C. Of the ceramic layer 32/400 ° C.). The conductor layer 33 provided between the ceramic layers 32 is made of, for example, a metallized layer of tungsten, molybdenum, or an alloy thereof. The conductor layer 33 includes control circuit wiring for transmitting a drive signal for the power semiconductor element 12. Each via conductor 27 (via conductor portion 31) is also made of a metallized layer of tungsten, molybdenum, or an alloy thereof, like the conductor layer 33. The first surface side electrode pad 24 and the second surface side electrode pad 25 formed on the first surface 21 and the second surface 22 of the substrate body 23 are conductor layers made of copper. Furthermore, the conductor layers formed on the first surface 21 and the second surface 22 of the substrate body 23 include circuit patterns and component mounting pads (not shown) in addition to the electrode pads 24 and 25.

  The first surface side electrode pad 24 on which the power semiconductor element 12 is mounted and the second surface side electrode pad 25 on which the passive component 13 is mounted are viewed from the substrate thickness direction (vertical direction in FIG. 1). Are arranged opposite to each other so that most of them overlap (that is, they face each other so that some do not overlap). On the other hand, the first surface side electrode pad 24 on which the power semiconductor element 12 is not mounted and the second surface side electrode pad 25 on which the passive component 13 is mounted completely overlap when viewed from the substrate thickness direction. So as to face each other. In the present embodiment, the planar shape of each electrode pad 24, 25 is rectangular. The vertical and horizontal lengths of the electrode pads 24 and 25 are about 4 mm × 7 mm, and the thicknesses of the electrode pads 24 and 25 are about 100 μm.

  As shown in FIGS. 1 and 2, the plurality of via conductors 27 constituting the via array 28 are connected to the common first surface side electrode pad 24 and second surface side electrode pad 25. That is, the plurality of via conductors 27 constituting the via array 28 are connected in parallel to the first surface side electrode pad 24 and the second surface side electrode pad 25. Further, when viewed from the thickness direction of the substrate, each via conductor 27 constituting the via array 28 is disposed in a region inside each electrode pad 24, 25.

  The ceramic wiring substrate 11 is provided with a plurality of (three in this embodiment) via arrays 28, and currents flow in different directions in the two adjacent via arrays 28. Specifically, for example, current flows from the lower side (first surface 21 side) to the upper side (second surface 22 side) in the right via array 28 (each via conductor 27) in FIG. A current flows through the via conductor 27) from the upper side to the lower side. The plurality of via conductors 27 constituting the via array 28 are straight vias for main power extended linearly in the thickness direction of the substrate body 23.

  As shown in FIG. 3, the via array 28 of the present embodiment has a plurality of via conductors 27 arranged so as to form a grid of 5 rows × 7 columns as a whole. One via array 28 includes a plurality of outer via conductors 27a arranged on the outermost periphery and a plurality of inner via conductors 27b surrounded by the outer via conductors 27a. In FIG. 3, for convenience of explanation, five via conductors 27a and 27b are arranged in the vertical direction (vertical direction in FIG. 3), and seven via conductors 27a and 27b are arranged in the horizontal direction (horizontal direction in FIG. 3). Although the via array 28 in which is arranged is illustrated, more via conductors 27a and 27b actually exist.

  In the present embodiment, each outer via conductor 27a and each inner via conductor 27b have a circular cross section, and the outer via conductor 27a and the inner via conductor 27b have the same diameter. Specifically, the via conductors 27a and 27b have a diameter of 200 μm. The via conductors 27a and 27b have a pitch (center distance) of 300 μm.

  In addition, each outer via conductor 27a and each inner via conductor 27b include two kinds of single metals (tungsten and molybdenum in the present embodiment) having different thermal expansion coefficients as metal materials. Here, the thermal expansion coefficient of tungsten is 4.6 ppm / K, and the thermal expansion coefficient of molybdenum is 5.7 ppm / K. The thermal expansion coefficient of tungsten and molybdenum is a value obtained by converting the expansion amount when the temperature is increased from 0 ° C. to 400 ° C. into the expansion amount per unit temperature (thermal expansion coefficient = 0 when the temperature is increased from 0 ° C. to 400 ° C. Of tungsten or molybdenum / 400 ° C.). The outer via conductor 27a has the highest content of the metal material (molybdenum) having the larger thermal expansion coefficient of the two types of metal materials. In the present embodiment, the tungsten content in the outer via conductor 27a is 18.9% by volume, and the molybdenum content in the outer via conductor 27a is 22.8% by volume. On the other hand, the inner via conductor 27b has the highest content of the metal material (tungsten) having the smaller thermal expansion coefficient of the two types of metal materials. In the present embodiment, the content of tungsten in the inner via conductor 27b is 52.2% by volume, and the content of molybdenum in the inner via conductor 27b is 22.8% by volume.

  Furthermore, the via conductors 27a and 27b according to the present embodiment contain a ceramic filler (alumina) as an insulating inorganic filler. That is, the via conductors 27 a and 27 b include a ceramic filler made of the same material as the ceramic material constituting the ceramic layer 32. Here, the thermal expansion coefficient of alumina is 7 to 8 ppm / K. The thermal expansion coefficient of alumina is a value obtained by converting the expansion amount when the temperature is raised from 0 ° C. to 400 ° C. into an expansion amount per unit temperature (thermal expansion coefficient = 0 alumina when the temperature is raised from 0 ° C. to 400 ° C. Expansion amount / 400 ° C.). Further, the content of the ceramic filler in the outer via conductor 27a is 58.3% by volume, and the content of the ceramic filler in the inner via conductor 27b is 25.0% by volume. That is, the content of the ceramic filler in the outer via conductor 27a and the content of the ceramic filler in the inner via conductor 27b are different from each other, and the content of the ceramic filler in the outer via conductor 27a is different from the ceramic in the inner via conductor 27b. It is larger than the filler content. The thermal expansion coefficient of the entire outer via conductor 27a is 6.6 ppm / K, and the thermal expansion coefficient of the entire inner via conductor 27b is 5.6 ppm / K. The thermal expansion coefficients of the via conductors 27a and 27b are values obtained by converting the expansion amount when the temperature is increased from 0 ° C. to 400 ° C. into the expansion amount per unit temperature (thermal expansion coefficient = 0 ° C. to 400 ° C. (Expansion amount of via conductors 27a, 27b / 400 ° C.).

  A plurality of via conductors 27 constituting the same via array 28 have a smaller difference in thermal expansion coefficient with the substrate body 23 as the via conductors 27 on the outer peripheral side. For example, in the via array 28 shown in FIG. 3, the thermal expansion coefficient (6.6 ppm / K) of the outer via conductor 27a is larger than the thermal expansion coefficient (5.6 ppm / K) of the inner via conductor 27b. Further, the thermal expansion coefficient (7.6 ppm / K) of the ceramic layer 32 of the substrate body 23 is larger than the thermal expansion coefficient of the outer via conductor 27a.

  Next, a method for manufacturing the ceramic wiring substrate 11 in the present embodiment will be described.

  First, a plurality of green sheets are formed using a ceramic material mainly composed of alumina powder. More specifically, the alumina powder and the thermally decomposable organic binder are kneaded using a solvent such as an organic solvent or water to prepare a raw material slurry. Next, by using this raw material slurry, sheet forming by sheet casting by the doctor blade method, sheet forming by extrusion molding or the like is performed to form a plurality of green sheets having a predetermined thickness. Then, laser processing is performed on the plurality of green sheets to form a plurality of through holes at predetermined positions. The through hole may be formed by punching, drilling, or the like.

  Thereafter, using a conventionally known paste printing apparatus (not shown), an arbitrary conductive paste (specifically, a material for forming the via conductor 27 such as tungsten or molybdenum, and a thermally decomposable material in the through hole of each green sheet is used. The organic binder is filled with a paste (kneaded using an organic solvent or a solvent such as water) to form an unfired via conductor portion 31 to be the via conductor 27. In the present embodiment, the first filling step of filling the through-hole that can be the center of the via array 28 with a conductive paste having a relatively small ceramic filler content, and the outer periphery of the via array 28 can be achieved. A second filling step of filling the through-hole with a conductive paste having a relatively high ceramic filler content is performed separately. Furthermore, the conductive paste 33 is printed using a conventionally known paste printing apparatus to form the unfired conductor layer 33. The order of filling and printing of the conductive paste may be reversed.

  Then, after the conductive paste is dried, the plurality of green sheets are stacked and disposed, and a pressing force is applied in the sheet stacking direction, whereby the green sheets are pressed and integrated to form a ceramic laminate. Next, the ceramic laminate is degreased and fired at a predetermined temperature for a predetermined time. As a result, the alumina of the green sheet and the tungsten in the paste are simultaneously sintered, and the substrate body 23 having the via conductor 27 and the conductor layer 33 is formed. Further, the first surface side electrode pad 24 and the second surface side electrode pad 25 are formed on the first surface 21 and the second surface 22 of the substrate body 23 by printing using a copper paste. In addition, you may form each electrode pad 24 and 25 by copper plating etc. besides printing of a copper paste. Similarly to the conductor layer 33, the electrode pads 24 and 25 may be formed by simultaneously sintering with a green sheet after printing the conductive paste. The ceramic wiring board 11 is manufactured through the above steps.

  In the ceramic package 10 of the present embodiment, thermal stress is applied to the ceramic wiring substrate 11 by turning on and off the power semiconductor element 12. At this time, in each via array 28 of the ceramic wiring substrate 11, the stress generated between the via conductors 27a and 27b is relieved, so that the generation of cracks is suppressed.

  The present inventors have confirmed by simulation analysis that stress generated in the ceramic layer 32 is relieved in the outer via conductor 27a arranged on the outermost periphery among the plurality of via conductors 27 constituting the via array 28. . Here, an outer via conductor 27a and an inner via conductor 27b formed of the same material are used as a base model before countermeasures (see FIG. 4). In addition, a model after taking countermeasures in which the outer via conductor 27a and the inner via conductor 27b are formed of different materials so that the thermal expansion coefficient of the outer via conductor 27a is larger than the thermal expansion coefficient of the inner via conductor 27b (see FIG. 5). In each model, the stress acting on the periphery of the outer via conductor 27a and the periphery of the inner via conductor 27b when the temperature was changed from high temperature to low temperature was confirmed. In the base model, the thermal expansion coefficient of the ceramic layer 32 (alumina) is 7.6 ppm / K, the thermal expansion coefficients of the via conductors 27a and 27b are 5.6 ppm / K, and the temperature change is from the firing temperature of 1540 ° C. − The simulation was performed using 50 ° C. (minimum thermal cycle temperature) as a calculation condition. On the other hand, in the model after the countermeasure, the thermal expansion coefficient of the ceramic layer 32 is 7.6 ppm / K, the thermal expansion coefficient of the outer via conductor 27a is 6.6 ppm / K, and the thermal expansion coefficient of the inner via conductor 27b is 5.6 ppm / K. The simulation was performed with K and temperature change from 1540 ° C. to −50 ° C. (minimum temperature of thermal cycle) as a calculation condition.

  As a result, in the base model, it was confirmed that a maximum stress of 986 MPa was applied around the outer via conductor 27a and a maximum stress of 914 MPa was applied around the inner via conductor 27b (see FIG. 6). On the other hand, in the model after the countermeasure, it was confirmed that the maximum stress applied to the periphery of the outer via conductor 27a was 967 MPa and the maximum stress applied to the periphery of the inner via conductor 27b was 483 MPa. (See FIG. 7).

  Further, the present inventors repeatedly perform a thermal shock test at −50 ° C. to 240 ° C. for the ceramic wiring board 11 manufactured as described above, and the occurrence of cracks in the ceramic layer 32 between the via conductors 27 is suppressed. I was sure that.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) In the ceramic wiring substrate 11 of the present embodiment, when the power semiconductor element 12 is driven, the plurality of via conductors 27 constituting the via array 28 include the first surface side electrode pad 24 and the second surface side. A current flows in the same direction through the electrode pad 25 and Joule heat is generated. Further, a current also flows through the power semiconductor element 12 mounted on the first surface 21 of the substrate body 23, and the power semiconductor element 12 generates heat. At this time, stress is generated in the via array 28 due to a difference in thermal expansion coefficient between the via conductor 27 and the ceramic. Note that the stress is remarkably generated in the outer peripheral portion rather than the central portion of the via array 28. Therefore, in the present embodiment, in the same via array 28, the thermal expansion coefficient difference from the substrate body 23 is reduced as the outer peripheral via conductor 27. In this way, the stress generated in the region between the via conductors 27 in the substrate body 23 can be made uniform between the outer peripheral side and the inner peripheral side of the via array 28, so that the stress applied to the entire via array 28 can be relaxed. it can. As a result, in the ceramic wiring substrate 11, it is possible to suppress the frequency with which thermal stress is applied, and to suppress the occurrence of cracks between the via conductors 27.

  (2) In the present embodiment, the power semiconductor element 12 mounted on the ceramic wiring substrate 11 is a power semiconductor element that generates heat at a temperature of 200 ° C. or more when a current of 10 A or more flows. In the ceramic wiring substrate 11 on which such a power semiconductor element 12 is mounted, thermal stress during use increases, but cracks can be prevented by suppressing the generated stress between the via conductors 27 in the via array 28 as described above. Occurrence can be reliably prevented.

  (3) The ceramic wiring substrate 11 according to the present embodiment includes a plurality of via arrays 28 having different current flowing directions. In this ceramic wiring board 11, since the generation of cracks between the via arrays 28 can be suppressed, two via arrays 28 in which current flows in different directions can be provided close to each other, and the ceramic wiring board 11 can be downsized. Become.

  In addition, you may change embodiment of this invention as follows.

  In the above embodiment, in the same via array 28, the molybdenum conductor content and the ceramic filler content increase as the via conductor 27 on the outer peripheral side increases. However, the content of the ceramic filler may be the same in all the via conductors 27, and the molybdenum content may be increased as the via conductors 27 on the outer peripheral side. Conversely, the content of molybdenum in all the via conductors 27 may be the same, and the content of the ceramic filler may be increased as the via conductors 27 on the outer peripheral side. Further, the content of the ceramic filler and molybdenum may be the same in all the via conductors 27, and the density of the via conductors 27 may be reduced as the via conductors 27 on the outer peripheral side.

  In the above embodiment, in the via array 28, the thermal expansion coefficient of the outer via conductor 27a and the thermal expansion coefficient of the inner via conductor 27b are changed in two stages, but the heat of the via conductor 27 is divided into three or more stages. The expansion coefficient may be changed. For example, the plurality of inner via conductors 27b may have a stepwise decrease in thermal expansion coefficient toward the outer peripheral side. In this way, since the stress generated in the ceramic layer 32 between the via conductors 27 in the via array 28 can be sufficiently relaxed, the generation of cracks can be reliably prevented.

  In the ceramic wiring substrate 11 of the above embodiment, the via array 28 has a plurality of via conductors 27 (outer via conductors 27a and inner via conductors 27b) arranged in a lattice pattern, but is not limited thereto. . For example, a plurality of via conductors 42 (outer via conductors 42a and inner via conductors 42b) may be arranged in a staggered manner as in the via array 41 shown in FIG.

  The ceramic wiring substrate 11 of the above embodiment includes a plurality of via arrays 28 having different current flowing directions. However, current may flow through the plurality of via conductors 27 constituting the via array 28 in the same direction.

  In the above embodiment, the cross-sectional shape of the via conductors 27 constituting the via array 28 is circular, but the present invention is not limited to this. For example, the via array may be formed by a plurality of via conductors having a cross-sectional shape such as an ellipse, a triangle, and a quadrangle.

  In the above embodiment, the via conductor 27 is configured by connecting the two via conductor portions 31 in the stacking direction of the ceramic layers 32. However, the via conductor 27 may be a single conductor extending from the first surface 21 of the substrate body 23 to the second surface 22.

  Next, in addition to the technical ideas described in the claims, the technical ideas grasped by the embodiments described above are listed below.

  (1) The ceramic wiring substrate according to means 1, wherein the plurality of via conductors constituting the same via conductor group has a higher density as the outer via conductors are arranged.

  (2) In the means 1, each of the plurality of via conductors constituting the same via conductor group includes a single metal having a different thermal expansion coefficient as a metal material, and the metal material includes tungsten, molybdenum, tantalum, titanium. A ceramic wiring board comprising two simple metals selected from niobium, copper, and silver.

  (3) The ceramic wiring board according to means 1, wherein the via conductor group is a via array arranged so as to have a grid shape of 3 rows or more and 3 columns or more.

  (4) The ceramic wiring board according to means 1, wherein the via conductor has a circular cross section.

  (5) The ceramic wiring board according to means 1, wherein the power semiconductor element is a power semiconductor element that generates heat at a temperature of 200 ° C. or higher.

  (6) The ceramic wiring board according to means 1, wherein the power semiconductor element is a power semiconductor element in which a current of 10 A or more flows.

  (7) The ceramic wiring board according to means 1, wherein current flows in the same direction through the plurality of via conductors constituting the same via conductor group.

  (8) The ceramic wiring board characterized in that the means 1 includes a plurality of the via conductor groups having different current flowing directions.

  (9) In the means 1, on the second surface side, passive components that are electrically connected to the first surface side electrode pad, the second surface side electrode pad, and the plurality of via conductors can be mounted. A ceramic wiring board characterized by that.

  (10) In means 1, the substrate body is formed by laminating a plurality of ceramic layers provided with via conductor portions, and the via conductors connect the plurality of via conductor portions in the laminating direction of the ceramic layers. The plurality of via conductor portions are arranged coaxially in the stacking direction of the ceramic layers.

  (11) A substrate body formed in a plate shape having a first surface and a second surface using a ceramic material, a first surface-side electrode pad disposed on the first surface, and on the second surface A ceramic wiring board comprising: a second surface side electrode pad disposed; and a via conductor group including a plurality of via conductors connecting the first surface side electrode pad and the second surface side electrode pad; and A ceramic package comprising a power semiconductor element mounted on one surface side and electrically connected to the first surface side electrode pad, the second surface side electrode pad, and the plurality of via conductors, the via conductor The group is composed of a plurality of outer via conductors arranged on the outermost periphery and a plurality of inner via conductors surrounded by the plurality of outer via conductors, and the plurality of vias constituting the same via conductor group Conductor is the outer via Ceramic package, characterized in that the thermal expansion coefficient difference between the substrate body The more the body is smaller.

DESCRIPTION OF SYMBOLS 11 ... Ceramic wiring board 12 ... Power semiconductor element 21 ... 1st surface 22 ... 2nd surface 23 ... Substrate body 24 ... 1st surface side electrode pad 25 ... 2nd surface side electrode pad 27, 42 ... Via conductor 27a, 42a ... Outer via conductors 27b and 42b as via conductors ... Inner via conductors 28 and 41 as via conductors ... Via array as a via conductor group

Claims (6)

A substrate body formed in a plate shape having a first surface and a second surface using a ceramic material, a first surface side electrode pad disposed on the first surface, and disposed on the second surface. A second surface side electrode pad; and a via conductor group composed of a plurality of via conductors connecting the first surface side electrode pad and the second surface side electrode pad, the first surface side electrode pad, A ceramic wiring board capable of mounting on the first surface side a power semiconductor element electrically connected to the second surface side electrode pad and the plurality of via conductors,
The via conductor group is composed of a plurality of outer via conductors arranged on the outermost periphery and a plurality of inner via conductors surrounded by the plurality of outer via conductors,
The ceramic wiring board, wherein the plurality of via conductors constituting the same via conductor group has a smaller difference in thermal expansion coefficient from the substrate body as the outer via conductors.   In the same via conductor group, the thermal expansion coefficient of the outer via conductor is larger than the thermal expansion coefficient of the inner via conductor, and the thermal expansion coefficient of the substrate body is larger than the thermal expansion coefficient of the outer via conductor. The ceramic wiring board according to claim 1. The plurality of via conductors constituting the same via conductor group includes an inorganic filler having insulating properties,
3. The ceramic wiring board according to claim 1, wherein a content of the inorganic filler in the outer via conductor and a content of the inorganic filler in the inner via conductor are different from each other.   4. The ceramic wiring board according to claim 3, wherein a content of the inorganic filler in the outer via conductor is larger than a content of the inorganic filler in the inner via conductor.   5. The ceramic wiring board according to claim 3, wherein the plurality of via conductors include the inorganic filler made of the same material as a ceramic material constituting the substrate body. Each of the plurality of via conductors constituting the same via conductor group includes, as a metal material, two or more kinds of simple metals, alloys or metal compounds having different thermal expansion coefficients,
The outer via conductor has the largest content of the metal material having the largest coefficient of thermal expansion among the two or more types of metal materials,
6. The ceramic wiring according to claim 1, wherein the inner via conductor has the largest content of the metal material having the smallest thermal expansion coefficient among the two or more kinds of the metal materials. substrate.

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