JP2015115382A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a molded semiconductor device which corresponds to a high temperature and has high reliability.SOLUTION: A semiconductor device comprises: a semiconductor element 5 which has an electrode formed on a principal surface 5a and a rear face bonded to a circuit surface 6f of a heat spreader 6; a lead frame 3 bonded to the electrode; a coating body 2 which covers the circuit surface 6f so as to surround the semiconductor element 5; and an encapsulation body 1 for encapsulating and wrapping a part of the lead frame, which is bonded to the electrode on the principal surface 5a and the semiconductor element 5 and the coating body 2. The coating body 2 is formed by a material having an elastic modulus lower than that of the encapsulation body 1 and formed at a distance from the semiconductor element 5 in an extension direction of the circuit surface 6f and formed to have a height equal to or higher than a height of the principal surface 5a of the semiconductor element in a height direction from the circuit surface 6f so as not to reach a surface 1f of the encapsulation body 1.

Description

  The present invention relates to a semiconductor device in which a circuit member including a power semiconductor element is sealed with a resin.

  2. Description of the Related Art A semiconductor device using a power semiconductor element uses a mold type in which a semiconductor element is sealed with a thermosetting resin such as an epoxy resin, and a gel sealing type in which a semiconductor element is sealed with a gel-like resin. In particular, mold-type semiconductor devices are small and excellent in reliability, and are easy to handle, and thus are widely used for control of air-conditioning equipment. In recent years, it is also used for power control of automobiles that perform motor control.

  On the other hand, semiconductor devices use metal or ceramics with excellent thermal conductivity as a substrate to improve heat dissipation for the purpose of miniaturization and large capacity, and adopt a method of diffusing heat generated by semiconductor elements. . For example, there is a structure in which an insulating substrate made of high thermal conductivity ceramic is joined by solder (for example, see Patent Document 1), or a mold type semiconductor device in which a semiconductor element is joined by solder or the like on a copper heat spreader (for example, (See Patent Document 2).

JP 2007-184315 A (paragraphs 0014 to 0018, FIG. 1) JP-A-1-280336 (page 4, lower left column to page 5, upper left column, FIG. 1)

  However, in such a semiconductor device, it is necessary to use a larger and thicker substrate in order to improve heat dissipation. As the area of the substrate increases, the influence of thermal stress generated by the difference in the linear expansion coefficient between the sealing resin and the substrate increases.

  On the other hand, as a compound semiconductor element capable of operating at a low loss, high withstand voltage, and high temperature as compared with a conventional silicon (Si) semiconductor element, application of, for example, a silicon carbide (SiC) semiconductor element to a semiconductor device has been promoted. Yes. SiC semiconductor elements are expected to have higher elastic modulus than Si semiconductor elements and operate under more severe temperature environments than ever, and the stress on the semiconductor elements tends to increase. is there. In a mold type semiconductor device, the stress applied to the interface between the semiconductor element and the sealing body is higher than ever, and as a result, peeling occurs at the interface between the semiconductor element and the sealing body, In some cases, cracks may occur in the nearby sealing body, leading to a decrease in insulation reliability of the semiconductor device.

  The present invention has been made to solve the above-described problems, and an object thereof is to obtain a highly reliable semiconductor device corresponding to a high temperature.

  A semiconductor device according to the present invention includes a circuit board, a semiconductor element having an electrode formed on a main surface, and a back surface bonded to the circuit surface of the circuit board, a wiring member bonded to the electrode, and the semiconductor element. A covering that covers the circuit surface, a portion that is joined to the electrode of the wiring member, and a sealing body that seals the semiconductor element and the covering so as to surround the covering, And formed of a material having a lower elastic modulus than the sealing body, and spaced from the semiconductor element in the extending direction of the circuit surface, and in the height direction from the circuit surface, It is characterized by being formed so as to have a height not less than the height of the main surface and not reaching the surface of the sealing body.

  According to the present invention, the covering disposed on the circuit surface so as to surround the semiconductor element reduces the thermal stress generated at the interface between the semiconductor element and the sealing body, and causes peeling or cracking that occurs near the edge of the semiconductor element. Thus, a semiconductor device with high insulation reliability can be obtained.

It is a cross-sectional schematic diagram for demonstrating the structure of the semiconductor device concerning Embodiment 1 of this invention. 2A and 2B are a partial plan view and a partial cross-sectional view, excluding a sealing body, for explaining a configuration of a semiconductor element peripheral portion of the semiconductor device according to the first exemplary embodiment of the present invention; It is a fragmentary sectional view for demonstrating arrangement | positioning of the covering which comprises the semiconductor device concerning Embodiment 1 of this invention. It is a plane schematic diagram for demonstrating arrangement | positioning of the covering which comprises the semiconductor device concerning Embodiment 1 of this invention. It is a fragmentary top view for demonstrating the structure of the semiconductor device concerning the modification of Embodiment 1 of this invention. It is a cross-sectional schematic diagram for demonstrating the structure of the semiconductor device concerning Embodiment 2 of this invention. It is a cross-sectional schematic diagram for demonstrating the structure of the semiconductor device concerning Embodiment 3 of this invention.

Embodiment 1 FIG.
1 to 4 are diagrams for explaining a semiconductor device according to a first embodiment of the present invention, and FIG. 1 is a schematic cross-sectional view of the semiconductor device. FIG. 2 is a view for explaining the configuration of the peripheral portion of the semiconductor element in a state in which the sealing body and the wiring member are removed from the semiconductor device. FIG. 3 is a partial cross-sectional view for explaining the arrangement of the covering constituting the semiconductor device, and FIG. 4 is a schematic plan view for explaining the arrangement of the covering. FIGS. 5A and 5B are partial planes for explaining the arrangement of the cover when a plurality of semiconductor elements are arranged adjacent to each other as a modification of the first embodiment of the present invention. FIG. 2 and FIG. 5 are not cross-sectional views, but for convenience, the installation area of the covering is indicated by hatching. Details will be described below.

  As shown in FIG. 1, the semiconductor device 100 according to the first embodiment of the present invention has one surface of a metal heat transfer plate (heat spreader 6) that has excellent thermal conductivity and aims to diffuse heat generation. A semiconductor element 5 for controlling electric power is mounted (bonded) on the (circuit surface 6f) by a bonding material 4 such as solder or a silver bonding material. The lead frame 3 is joined and wired to the electrode formed on the main surface 5a of the semiconductor element 5 by direct lead joining. Further, the lead frame 3 is also joined to the circuit surface 6f of the heat spreader 6 joined to the back electrode of the semiconductor element 5, so that both main power poles of the semiconductor element 5 can be connected to the outside. The heat spreader 6 is intended to reduce the thermal resistance against the heat generated by the semiconductor element 5. When the heat spreader 6 is not required, the semiconductor element 5 is directly mounted on the pattern of the lead frame 3. May be. Further, the wiring member is not limited to the lead frame 3 described above, and a bonding wire or the like (not shown) may be used.

  The semiconductor element 5 is an element for controlling electric power, and is also referred to as a power semiconductor element or a power semiconductor element. Specifically, for example, a switching element such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor) or a rectifying element such as a freewheeling diode is used. The semiconductor element 5 uses a wide band gap semiconductor such as silicon carbide (SiC) in the first embodiment and the following embodiments. Examples of a material (semiconductor material) constituting the wide band gap semiconductor include silicon carbide (SiC), a gallium nitride-based material, and diamond. When a wide bandgap semiconductor is used, the allowable current density is high and the power loss is low, so that a device using a semiconductor element can be downsized. Moreover, not only a wide band gap semiconductor but also a Si semiconductor may be mixed.

  An insulating layer 7 and a metal foil 8 are provided on the surface of the heat spreader 6 opposite to the circuit surface 6f on which the lead frame 3 and the semiconductor element 5 are mounted. An insulating sheet can be used for the insulating layer 7. In the insulating sheet, an epoxy resin is filled with at least one inorganic powder such as silica, alumina, boron nitride, and aluminum nitride that has excellent thermal conductivity. These inorganic powders may be used alone or in combination. Further, the metal foil 8 is exposed to the outside without being sealed by the sealing body 1 to be described later, so that not only the heat dissipation is ensured but also the insulating layer 7 is not damaged by contact from the outside. It also serves as a protective layer. A metal foil such as copper or aluminum or a thick copper plate may be used as long as it satisfies this purpose.

  Then, the entire circuit member is sealed from the side portion of the metal foil 8 so as to enclose a part of the lead frame 3 and a member (circuit member) on the circuit surface 6 f side including at least the main surface 5 a of the semiconductor element 5. The sealing body 1 is formed by transfer molding. Thereby, a semiconductor device generally called a module is completed.

  In the sealing body 1, an epoxy resin is filled with inorganic powder such as fused silica having a small thermal expansion coefficient, alumina having excellent thermal conductivity, or the like. The epoxy resin is not particularly limited, such as a general ortho-cresol novolac type or a dicyclopentadiene type, although it depends on the heat dissipation of the power semiconductor device, the amount of heat generated during operation, and the operating temperature. For example, by increasing the operating temperature of the semiconductor element 5 using SiC or the like, a resin having higher heat resistance such as naphthalene type or polyfunctional type can be used.

  In addition, assuming a thermal stress generated in a reliability test such as a temperature cycle, if a temperature difference occurs due to a difference in thermal expansion coefficient, a difference in strain occurs on the contact surface, and stress is generated. When a wide bandgap semiconductor is used, the thermal expansion coefficient of the encapsulant 1 is the line of the wide bandgap semiconductor in order to assume a higher elastic modulus than that of the Si semiconductor and to operate in a more severe environment. It is desirable that the coefficient of expansion is as close as possible. In the case of the present embodiment, since the thermal stress at the interface between the sealing body 1 and the semiconductor element 5 is relaxed by providing the covering 2 described later, a resin having a larger linear expansion coefficient than the conventional one is applied. can do. Therefore, it is desirable to apply a resin in a range between the heat spreader 6 and the thermal expansion coefficient of the semiconductor element 5 to the sealing body 1.

  As a feature of the semiconductor device 100 according to the first embodiment, the covering 2 that covers the circuit surface 6f is disposed so as to surround the semiconductor element 5. As shown in FIG. 2, the covering 2 is disposed so as to cover the semiconductor element 5 and the bonding material 4 for bonding the semiconductor element 5 to the heat spreader 6 and cover the end of the heat spreader 6. Has been. In addition, when there exists an electrode or a wire on the heat spreader 6, you may arrange | position the covering body 2 avoiding these.

  The material used for the covering 2 is a material having a lower elastic modulus than the material constituting the sealing body 1, for example, epoxy resin, silicone gel, silicone rubber, melamine resin, phenol resin, polyamide, polyimide, Examples include polybutylene terephthalate, polyether ether ketone, polyether imide, polyether sulfone, and polyphenylene sulfide. These materials may contain a filler of inorganic powder such as silica, alumina, boron nitride, aluminum nitride.

  As shown in FIGS. 3 and 4, the semiconductor element 5 and the covering 2 are spaced apart from the side surface 5s of the semiconductor element 5 by a certain range D in the direction parallel to the circuit surface 6f. It is set to have a thickness t2. The interval D is an interval between the side surface 5s of the semiconductor element 5 and the inner side surface 2s of the opening surrounding the semiconductor element 5 of the covering 2 and is larger than 0 so as not to contact the semiconductor element 5 and the bonding material 4. In addition, when the length of one side of the semiconductor element 5 is L, it is set within 0.2L. That is, as shown in FIG. 4, the inner side surface 2s is set so as to fall within a range surrounded by a line Px separated from the side surface 5s by 0.2L from the line Pi having a minimum distance away from the side surface 5s and the bonding material 4. doing. On the other hand, the outer side is set so as to cover up to the end of the heat spreader 6. In addition, when the range of the distance D is expressed by an equation, “0 <D ≦ 0.2L”, which is that the thickness of the portion of the sealing body 1 that contacts the side surface 5s of the semiconductor element 5 is greater than 0. And it shows that it becomes 0.2L or less.

  For example, when the cover 2 is disposed so that the inner surface 2s is outside Px so that the distance from the semiconductor element 5 is excessively set so that D> 0.2L, the corners of the semiconductor element 5 ( For example, the thermal stress applied to the corners of the main surface 5a and the side surface 5s may not be sufficiently relaxed. Further, when the covering body 2 is arranged so that the inner side surface 2 s is inside the Pi, and the covering body 2 is in contact with or covers the semiconductor element 5 or the bonding material 4, the semiconductor element 5 by the sealing body 1. In addition, the effect of firmly fixing and constraining the bonding material 4 is weakened, leading to a decrease in the reliability of bonding between the semiconductor element 5 and the circuit surface 6f.

  This setting is the same when a plurality of semiconductor elements 5 are arranged at a short distance as shown in FIG. That is, when the interval between the side surfaces 5s of the semiconductor element 5 is larger than 0.2L, the opening is divided so that the interval D is 0.2L or less. On the other hand, if the distance between the side surfaces 5s of the semiconductor element 5 is 0.2L or less, the covering 2 may be divided if it does not contact any of the semiconductor elements 5 or the bonding material 4. However, dividing the opening often increases the number of processes, and basically, the openings are arranged in one opening.

  The thickness t2 of the cover 2 is larger than the thickness of the semiconductor element 5, and the distance from the circuit surface 6f of the heat spreader 6 to the surface 1f of the sealing body 1, that is, the sealing body 1 directly covers the circuit surface 6f. Is set to be 3/4 or less of the original thickness t1. Strictly speaking, the lower limit value of t2 is the mounting height including the bonding material 4, that is, the height from the circuit surface 6f of the heat spreader 6 to the main surface 5a of the semiconductor element 5. The lower limit value of the thickness 2 is that the height of the covering 2 from the circuit surface 6f is lower than the height of the main surface of the semiconductor element 5, and the covering 2 cannot fully absorb the warp. It is set so as not to exhibit. On the other hand, as for the upper limit value, when the thickness t2 exceeds 3/4 of the original thickness t1 of the sealing body 1, the thickness of the sealing body 1 at that portion is thin (less than 1/4 of the original thickness t1). Thus, the module is set to prevent the strength of the module from being reduced and the sealing body 1 from being cracked.

  Thereby, the covering body 2 having lower elasticity than the sealing body 1 absorbs the warp of the entire module, reduces the thermal stress generated at the interface between the sealing body 1 and the semiconductor element 5, and peels off the sealing body 1. And the generation of cracks can be prevented. Further, since the covering 2 is not in contact with the semiconductor element 5 and the bonding material 4, the bonding material 4 such as solder or aluminum wire bonded to the semiconductor element 5 is firmly sealed by the sealing body 1. The reliability in the temperature cycle test and the power cycle test can be kept high.

  Next, in order to verify the effect of the semiconductor device 100 according to the first embodiment, a reliability test by a temperature cycle test was performed using the physical properties, distance D, thickness t2 and the like of the covering 2 as parameters.

  The temperature cycle test was carried out by putting the semiconductor device 100 in a thermostat capable of temperature control and repeatedly reciprocating the temperature in the thermostat between −60 ° C. and 180 ° C. The criterion for reliability was that there was no peeling after 1000 cycles of the temperature cycle test. Judgment of the presence or absence of peeling was carried out by observing with an ultrasonic imaging apparatus (FineSAT manufactured by Hitachi Engineering & Service). The configuration and test results of the test sample (example) of the semiconductor device 100 according to the first embodiment used in the test and the test sample (comparative example) of the semiconductor device to be compared will be described below.

<Common conditions>
In each test sample, the semiconductor element 5 is bonded to the circuit surface 6f, the lead frame 3 is bonded to the heat spreader 6 provided with the insulating layer 7 and the metal foil 8 on the other surface, and the whole is sealed with the sealing body 1. The molded type semiconductor device was used. The semiconductor element 5 was a SiC semiconductor element of 10 mm × 10 mm × 0.3 mm, and the heat spreader 6 was 20 mm × 40 mm × 3.0 mm. The heat spreader 6, the lead frame 3, and the metal foil 8 were made of copper in consideration of heat dissipation. On the heat spreader 6, two types of semiconductor elements 5 of MOSFET and SBD (Schottky Barrier Diode) are mounted. An insulating sheet made of epoxy was used for the insulating layer 7.

  As the sealing body 1, an epoxy resin having a glass transition point (Tg) of about 190 ° C. filled with 82% by weight of silica, a thermal expansion coefficient α of 12 ppm / K, and an elastic modulus E of 12 GPa was used. The test sample is prepared by bonding the semiconductor element 5 on the heat spreader 6, placing the covering 2, and combining the lead frame 3, the insulating layer 7, and the metal foil 8 with resin molding by transfer molding. went.

  Molding was performed at about 180 ° C. for 120 seconds, and after mold removal, post mold curing (PMC) at 180 ° C. for 4 hours was performed in an oven. After PMC, as a temperature cycle test, a thermal shock tester (TSP-100 manufactured by ESPEC) was used to repeatedly reciprocate between −60 ° C. and 180 ° C. Performed in the apparatus. The criteria for determining moldability were determined based on the appearance and the absence of cracks inside the module after molding. In addition, the reliability test is not implemented when it evaluates as a disqualification (x) at the time of a moldability.

<Example 1>
An epoxy resin having a Tg of about 170 ° C. was used as a main material constituting the covering 2. As the covering 2, a silica filler having a silica filler content of 5% was used, a thermal expansion coefficient α of 50 ppm / K, and an elastic modulus E of 2 GPa. The covering 2 is compression-molded into an arbitrary shape in advance, and D = 0.2 mm so as not to contact the semiconductor element 5 and its bonding material 4, and t2 = 0.8 mm on the heat spreader 6. Uniformly installed and formed. When each determination was performed on the test sample of Example 1, the semiconductor device 100 having high reliability and temperature cycleability and moldability was obtained.

<Example 2>
Example 2 was carried out in the same manner as Example 1 except that the amount of silica filler added was adjusted and the physical properties of the covering 2 were changed. The physical properties of the coated body 2 were a linear expansion coefficient α of 13 ppm / K and an elastic modulus E of 10 GPa. When each determination was performed on the test sample of Example 2, the semiconductor device 100 having high temperature cycle and moldability and having high reliability was obtained.

<Example 3>
In this Example 3, it implemented similarly to Example 1 except having used the silicone gel as the coating body 2. FIG. The physical properties of the coated body 2 were a linear expansion coefficient α of 600 ppm / K and an elastic modulus E of 3.0 × 10 ⁻⁶ GPa. The silicone gel was applied in an arbitrary shape using a dispenser, post-cured at 120 ° C. for 10 minutes, and then resin-sealed by transfer molding. When each determination was performed on the test sample of Example 3, the semiconductor device 100 having high reliability and temperature cycleability and moldability was obtained.

<Example 4>
In the present Example 4, it implemented similarly except having changed the space | interval D of the semiconductor element 5 and the covering body 2 with respect to Example 1. FIG. The distance D between the semiconductor element 5 and the covering 2 was set to 2.0 mm. When each determination was performed on the test sample of Example 4, the semiconductor device 100 having high temperature cycleability and moldability and having high reliability was obtained.

<Example 5>
In this Example 5, it implemented similarly except having changed thickness t2 of the covering 2 with respect to Example 1. FIG. The thickness t2 of the covering 2 was set to 0.4 mm. When each determination was performed on the test sample of Example 5, the semiconductor device 100 having high reliability and temperature cycleability and moldability was obtained.

<Example 6>
In the present Example 6, it implemented similarly except having changed the covering 2 thickness t2 with respect to Example 1. FIG. The thickness t2 of the covering 2 was set to 3.0 mm. When each determination was performed on the test sample of Example 6, the semiconductor device 100 having high temperature cycleability and moldability and having high reliability was obtained.

<Comparative Example 1>
In this comparative example 1, a test sample was prepared without using the covering 2 with respect to the example 1. When each determination was performed on the test sample of Comparative Example 1, the moldability was satisfactory, but peeling and cracking occurred at the interface between the semiconductor element 5 and the sealing body 1 in the temperature cycle test. The cycle property was evaluated as x.

<Comparative Example 2>
In this comparative example 2, it carried out similarly to the example 1 except having adjusted the addition amount of the silica filler and changing the physical property of the coating 2. The physical properties of the covering 2 were a linear expansion coefficient α of 10 ppm / K and an elastic modulus E of 12 GPa. When each determination was made on the test sample of Comparative Example 2, the moldability was satisfactory, but the effect of stress relaxation applied to the semiconductor element 5 in the temperature cycle test was small, and the semiconductor element 5 and the sealing body 1 Since peeling and cracks occurred at the interface, the temperature cycle property was judged as x.

<Comparative Example 3>
In this comparative example 2, it implemented similarly to Example 1 except having used the polypropylene as the coating body 2. FIG. The physical properties of the coated body 2 were a linear expansion coefficient α of 100 ppm / K and an elastic modulus E of 1.5 × 10 ⁻³ GPa. Polypropylene was molded into an arbitrary shape by compression molding, and then placed on the heat spreader 6, and the resin was sealed by transfer molding together with the lead frame 3, the insulating layer 7 and the metal foil 8. When each determination was performed on the test sample of Comparative Example 3, a crack occurred in the sealing body 1 immediately after molding. Polypropylene has a melting point of about 130 ° C., and it is thought that cracks occurred due to a sudden volume change when the phase changed from a liquid state to a solid state. Therefore, the moldability was judged as x.

<Comparative Example 4>
In this comparative example, it implemented similarly except having changed the space | interval D of the semiconductor element 5 and the covering 2 with respect to Example 1. FIG. The covering 2 covered a part of the bonding material 4 for bonding the semiconductor element 5 and the heat spreader 6. That is, the inner side surface 2s is set to be inside the line Pi in FIG. When each determination was performed on the test sample of the present comparative example 4, the moldability was satisfactory, but cracks occurred in the bonding material 4 for bonding the semiconductor element 5 and the heat spreader 6 in the temperature cycle test. The sex judgment was x.

<Comparative Example 5>
In this comparative example, it implemented similarly except having changed the space | interval D of the semiconductor element 5 and a covering body with respect to Example 1. FIG. The distance D between the semiconductor element 5 and the covering 2 was set to 2.5 mm. That is, the interval D exceeds 0.2L and is outside the line Px in FIG. When each determination was performed on the test sample of Comparative Example 4, the moldability was satisfactory, but the effect of stress relaxation applied to the semiconductor element 5 in the temperature cycle test was small, and the semiconductor element 5 and the sealing body 1 Since the peeling occurred at the interface, the temperature cycle property was judged as x.

<Comparative Example 6>
In this comparative example 6, it implemented similarly except having changed thickness t2 of the covering 2 with respect to Example 1. FIG. The thickness t2 of the covering 2 was set to 0.3 mm. That is, when the thickness of the bonding material 4 is taken into account, the height of the covering 2 is made lower than the main surface 5a. When each determination was performed on the test sample of Comparative Example 6, the moldability was satisfactory, but peeling and cracking occurred at the interface between the semiconductor element 5 and the sealing body 1 in the temperature cycle test. The cycle property was evaluated as x.

<Comparative Example 7>
In this comparative example 7, it implemented similarly except having changed thickness t2 of the covering 2 with respect to Example 1. FIG. The thickness t2 of the covering 2 was set to 3.5 mm. Note that 3.5 mm is a value larger than the distance from the circuit surface 6f to the surface 1f of the sealing body 1, that is, 3/4 of the original thickness t1 of the sealing body 1. When each determination was performed on the test sample of Comparative Example 7, the determination of moldability was x. This is because the height of the covering body 2 exceeds 3/4 of the original thickness t1 of the sealing body 1, and the thickness of the sealing body 1 on the upper portion of the covering body 2 is reduced. This is thought to have led to a crack.

  Among the test results, the moldability and reliability results of Examples 1 to 6 are shown in Table 1, and the moldability and reliability results of Comparative Examples 1 to 7 are shown in Table 2.

  In the first to sixth embodiments, the thermal stress generated at the interface between the semiconductor element 5 and the sealing body 1 is reduced, peeling and cracking in the vicinity of the end of the semiconductor element 5 can be prevented, and insulation reliability can be prevented. A highly reliable semiconductor device 100 was obtained. In addition, the stress reduction structure suggests that the allowable range of required characteristic values such as the elastic modulus E, linear expansion coefficient α, and resin strength required for the sealing body 1 has increased. In the semiconductor device 100 according to the first embodiment of the present invention, the covering body 2 having a lower elastic modulus than the sealing body 1 is surrounded so as not to contact the semiconductor element 5 and the bonding material 4 thereof. As a result, the bonding material 4 such as solder or aluminum wire bonded to the semiconductor element 5 is firmly sealed by the sealing body 1, which reduces the stress in the temperature cycle test and the power cycle test and reduces the bonding material. It was found that both reliability could be achieved.

  In the reliability test, the sealed body 1 has the same physical property values (elastic modulus E = 12 (unit: GPa), linear expansion coefficient α = 12 (unit: ppm / K) as shown in Table 3. ) Was used. However, the physical properties of the sealing body 1 are different if the relationship between the elastic modulus of the sealing body 1 and the covering body 2 and the standard of the distance D between the thickness t2 of the covering body 2 and the semiconductor element 5 are satisfied. Has confirmed separately that the same effect can be obtained. For example, it is about the case where the elastic modulus E of the sealing body 1 is higher or lower than 12 GPa.

Therefore, why the stress reduction and the reliability of the bonding material can be achieved at the same time when the above conditions are satisfied was examined as follows.
The sealing resin for transfer mold, which is a material of the sealing body 1, can change E and α by changing the amount of the filler. However, E and α are in a trade-off relationship, and it is empirically known that the value of E × α changes so as to be constant. Therefore, when the elastic modulus E is lowered, the linear expansion coefficient α increases. For example, when the amount of filler is changed so that E = 12 GPa, α = 12 ppm / K, and E = 10 GPa, α = It becomes 14.4 ppm / K.

  On the other hand, it is considered that the reliability of the semiconductor device is greatly influenced by thermal stress at the interface between the semiconductor element 5 and the sealing body 1. The thermal stress σ is generated from the difference in coefficient of linear expansion between the sealing body 1 and the semiconductor element 5 in the temperature change accompanying the start and stop, and can be expressed by Expression (1).

In the formula (1), subscript r indicates the physical properties of the sealing body 1, and s indicates the physical properties of the semiconductor element 5. In the case where the semiconductor element 5 is SiC, which is a wide band gap semiconductor, the linear expansion coefficient α _s is about 3 ppm / K, which is a value smaller than the linear expansion coefficient α _{r of} the sealing body 1. It can be said that the smaller the coefficient α _r and the elastic modulus _Er , the smaller the thermal stress σ. However, the sealing body 1 also constrains a metal member such as the lead frame 3, and the linear expansion coefficient α _r cannot be matched only with the linear expansion coefficient α _s of the semiconductor element 5. Therefore, the linear expansion coefficient α _r of the sealing body 1 can be adjusted only within a narrow range between the physical properties of the metal member and the semiconductor element 5. As a result, the linear expansion coefficient α _s of the semiconductor element 5 becomes negligible in the portion in parentheses in the expression (1), and the thermal stress σ is proportional to the product of E _r and α _r of the sealing body 1. become. That is, considering an empirical rule in which the product of E and α is constant, it is considered that there is no significant change in thermal stress only by changing the amount of filler. Actually, in the currently developed sealing resin, it is close to the limit to reduce the product of E and α, and the physical properties of the sealing body 1 shown in Table 3 are because the thermal stress σ is small. The value close to the limit is used.

  On the other hand, since the covering 2 is not in contact with the semiconductor element 5, the stress analysis reveals that the influence of the linear expansion coefficient α is not as great as that of the sealing body 1. Therefore, even when the linear expansion coefficient α is increased by reducing the elastic modulus E, the covering 2 absorbs warpage due to low elasticity (soft), and the semiconductor element 5 and the sealing body 1 It becomes possible to reduce the thermal stress generated at the interface. Furthermore, since the covering body 2 is not formed by transfer molding, the resin design has a wider range of heat resistance and electrical characteristics than the sealing body 1, and the physical properties are adjusted specifically for the action of absorbing warpage. be able to.

  When this is explained using numerical values in a simple system, the product of α and E due to the physical properties of the sealing body 1 becomes 144 when E = 12 GPa and α = 12 ppm / K, and the filling amount is adjusted to obtain E = 10 GPa and α = 14.4 ppm / K, it becomes 144, and the thermal stress σ has the same value. On the other hand, when the cover 2 is used and the physical property of the cover 2 is set to 10 GPa as in the first embodiment, the linear expansion coefficient α of the cover 2 does not greatly affect the thermal stress, and the sealing body 1 The lower elastic covering 2 has the effect of absorbing the warp and the stress is reduced, and the thermal stress is reduced as compared with the case where only the sealing body 1 is used.

  That is, if the covering 2 is formed on the circuit surface 6f so as to satisfy the above-described conditions, the thermal stress generated at the interface between the semiconductor element 5 and the sealing body 1 is reduced, and near the end of the semiconductor element 5. Separation and cracks that occur can be prevented, and the semiconductor device 100 with high insulation reliability can be obtained. Further, when the semiconductor device 100 according to the first embodiment is attached to a heat sink or the like (not shown), the covering 2 absorbs the warp, so that the warp of the entire semiconductor device 100 is reduced and the attachment is facilitated. . In addition, since it has a stress reduction structure, the allowable range of required characteristic values such as elastic modulus E, linear expansion coefficient α, and resin strength required for the sealing body 1 is widened, and the productivity of the semiconductor device 100 is improved. , Leading to lower costs. Further, since the covering 2 which is a feature of this structure is not in contact with the semiconductor element 5 and its bonding material 4, the bonding material 4 such as solder or aluminum wire bonded to the semiconductor element 5 is removed by the sealing body 1. It is tightly sealed and can maintain high reliability in temperature cycle tests and power cycle tests.

  As described above, according to the semiconductor device 100 according to the first embodiment of the present invention, the circuit board (heat spreader 6) and the electrodes are formed on the main surface 5a, and the back surface is formed on the circuit surface 6f of the circuit board (heat spreader 6). Of the semiconductor element 5 bonded to each other, the wiring member (lead frame 3) bonded to the electrode, the covering 2 covering the circuit surface 6f so as to surround the semiconductor element 5, and the main members of the wiring member (lead frame 3). A portion bonded to the electrode of the surface 5a and a sealing body 1 for sealing so as to enclose the semiconductor element 5 and the covering body 2. The covering body 2 is formed of a material having a lower elastic modulus than that of the sealing body 1. In addition, the sealing body 1 is spaced apart from the semiconductor element 5 in the extending direction of the circuit surface 6f, and at least the height of the main surface 5a of the semiconductor element 5 in the height direction from the circuit surface 6f. Does not reach the surface 1f As a result, the thermal stress generated at the interface between the semiconductor element 5 and the sealing body 1 is reduced, and peeling and cracks that occur near the edge of the semiconductor element 5 are prevented. In addition, the semiconductor device 100 with high insulation reliability can be obtained.

  In addition, since the covering 2 is formed so as not to contact the bonding material 4 for bonding the semiconductor element 5 and the circuit surface 6f, the bonding material 4 is firmly restrained by the sealing body 1, and the bonding reliability is improved. Kept.

  Since the height t2 of the cover 2 is configured to be 3/4 or less of the height t1 from the circuit surface 6f to the surface 1f of the sealing body 1, the strength of the module (semiconductor device 100) is maintained. There is no occurrence of cracks in the sealing body 1.

  Since the distance D between the semiconductor element 5 and the cover 2 is set to be 0.2 times or less the side length L of the semiconductor element 5, the cover 2 has a thermal stress applied to the semiconductor element 5. The function as a cushioning material that relaxes can be reliably exhibited.

  The covering 2 is at least any one of an epoxy resin, silicone gel, silicone rubber, melamine resin, phenol resin, polyamide, polyimide, polybutylene terephthalate, polyether ether ketone, polyether imide, polyether sulfone, and polyphenylene sulfide. Therefore, the covering body 2 that functions as a buffer material can be easily formed.

Embodiment 2. FIG.
In the semiconductor device according to the second embodiment, an insulating substrate is used instead of the heat spreader as compared with the semiconductor device according to the first embodiment. FIG. 6 is a schematic cross-sectional view for explaining the configuration of the semiconductor device according to the second embodiment of the present invention. In the figure, the same components as those in the first embodiment are denoted by the same reference numerals and detailed description thereof is omitted.

As shown in FIG. 6, in the semiconductor device 100 according to the second embodiment, a ceramic substrate such as DBC (Direct Bonding Copper) is used instead of the heat spreader 6 for heat diffusion as in the first embodiment. The insulating substrate 10 in which conductive layers 10a and 10c are formed on both surfaces of the material 10b is used. If the thermal conductivity of the insulating substrate 10 is sufficiently high and the thermal resistance is small, the heat spreader 6 may not be used. In FIG. 6, the two semiconductor elements 5 are bonded to a predetermined position of the conductive layer 10 a on the circuit surface 10 f side of the insulating substrate 10 using a bonding material 4 such as solder. Then, under the same conditions as in the first embodiment, the covering 2 is disposed so that the inner surface surrounds the semiconductor element 5 without being in contact with the two semiconductor elements 5 and the bonding material 4, and the outer side covers the end of the conductive layer 10a. Then, the sealing body 1 is formed by transfer molding from above.

  In the second embodiment, the lead frame 3 is not directly bonded to the semiconductor element 5 or the conductive layer 10 a but is electrically connected via the bonding wire 9. For example, the bonding wires 9 that connect the semiconductor elements 5 are wired so as to straddle the covering 2 between them.

  Also in the second embodiment, the same effect as in the first embodiment is obtained, and the highly reliable semiconductor device 100 is obtained. Further, since the insulating substrate 10 has a smaller linear expansion coefficient α than the metal substrate such as the heat spreader 6, the warping of the entire module tends to increase, but in the present embodiment, the covering 2 absorbs the warping. Therefore, warpage can be suppressed.

  As described above, according to the semiconductor device 100 according to the second embodiment, even if the circuit board is the insulating substrate 10 in which the conductive layer 10a is formed on at least one surface of the ceramic base material 10b, Similar to Embodiment 1, the thermal stress generated at the interface between the semiconductor element 5 and the sealing body 1 is reduced, and peeling and cracks generated near the end of the semiconductor element 5 can be prevented, and the semiconductor device having high insulation reliability 100 can be obtained.

Embodiment 3 FIG.
In the first or second embodiment, the sealing body is formed by molding using a molding die such as transfer molding, and the sealing body also serves as the housing of the semiconductor device. However, in the semiconductor device according to the third embodiment, a case serving as a housing is separately manufactured, and a sealing body is formed in the case by potting. FIG. 7 is a schematic cross-sectional view for explaining the configuration of the semiconductor device according to the third embodiment of the present invention. In the figure, the same components as those in the first or second embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIG. 7, in the semiconductor device 100 according to the third embodiment, for example, a case 12 using polyphenylene sulfide (PPS) is used for the housing of the semiconductor device 100. The case 12 may be other than PPS as long as it is a flame retardant resin, and may be filler reinforced or alloy reinforced. After mounting the insulating substrate 10 and the semiconductor element 5 described in the second embodiment on the upper part of the metal heat sink 13 housed in the case 12, the covering body 2 is arranged, potted with the sealing body 1 and sealed. Stopped. Thereafter, curing was performed at 150 ° C. for 3 hours. For the sealing body 1, for example, an epoxy resin can be used, and an inorganic filler such as silica or alumina may be contained.

  In the third embodiment, the lead terminal 11 is fixed to the case 12, and electrical connection with the semiconductor element 5 and the conductive layer 10 a is performed via the bonding wire 9. As in the second embodiment, for example, the bonding wires 9 that connect the semiconductor elements 5 are wired so as to straddle the covering 2 between them.

  Also in the third embodiment, if the covering 2 is arranged under the same conditions as described in the first or second embodiment, the same effect can be obtained and the highly reliable semiconductor device 100 can be obtained. .

  As described above, according to the semiconductor device 100 according to the third embodiment, the case 12 serving as the outer frame of the semiconductor device 100 is provided, and the sealing body 1 is formed by potting resin into the case 12. Even if this is done, as in the first or second embodiment, the thermal stress generated at the interface between the semiconductor element 5 and the sealing body 1 is reduced, and peeling occurs near the end of the semiconductor element 5. Thus, the semiconductor device 100 with high insulation reliability can be obtained.

  In the first to third embodiments, it is assumed that SiC, which is a wide band gap semiconductor material, is applied to the semiconductor element 5, but silicon that is generally used may be used. Needless to say. However, when using silicon carbide that can form a so-called wide gap semiconductor with a large band gap, gallium nitride-based material or diamond or gallium oxide-based material, high withstand voltage and high temperature resistant operation are required. The effect of the present invention is noticeable. That is, by exhibiting the effect of the present invention, the characteristics of the wide band gap semiconductor can be utilized.

1: Sealed body, 1f: Sealed body surface, 2: Covered body, 2s: Inner side surface, 3: Lead frame (wiring member), 4: Bonding material, 5: Semiconductor element, 6: Heat spreader (circuit board), 6f: circuit surface, 7: insulating sheet (insulating layer), 8: metal foil, 9: bonding wire (wiring member), 10: insulating substrate (circuit board), 10a, 10c: conductive layer, 10b: ceramic substrate ( Insulating layer), 10f: circuit surface, 11: lead terminal, 12: case, 13: heat sink, 100: semiconductor device,
D: Distance between cover (inside surface) and semiconductor element (side surface), t1: original thickness of sealing body on circuit surface (height from circuit surface), t2: thickness of cover (circuit) Height from the surface), L: length of the side of the semiconductor element.

Claims (11)

A circuit board;
A semiconductor element having an electrode formed on a main surface and a back surface bonded to a circuit surface of the circuit board;
A wiring member joined to the electrode;
A covering covering the circuit surface so as to surround the semiconductor element;
A portion that is joined to the electrode of the wiring member and a sealing body that seals so as to enclose the semiconductor element and the covering,
The covering body is formed of a material having a lower elastic modulus than the sealing body, and is spaced from the semiconductor element in the extending direction of the circuit surface, and in the height direction from the circuit surface, A semiconductor device, wherein the semiconductor device is formed to have a height not less than a height of a main surface of the semiconductor element and not reaching a surface of the sealing body.   The semiconductor device according to claim 1, wherein the covering is formed so as not to contact a bonding material that bonds the semiconductor element and the circuit surface.   The semiconductor device according to claim 1, wherein a height of the covering body is set to 3/4 or less of a height from the circuit surface to the surface of the sealing body.   4. The semiconductor according to claim 1, wherein an interval between the semiconductor element and the covering is set to be 0.2 times or less of a side length of the semiconductor element. 5. apparatus.   The covering is made of at least one of epoxy resin, silicone gel, silicone rubber, melamine resin, phenol resin, polyamide, polyimide, polybutylene terephthalate, polyether ether ketone, polyether imide, polyether sulfone, and polyphenylene sulfide. The semiconductor device according to claim 1, wherein the semiconductor device is formed by using the semiconductor device.   The semiconductor device according to claim 1, wherein the sealing body is formed by transfer molding. A case serving as an outer frame of the semiconductor device;
The semiconductor device according to claim 1, wherein the sealing body is formed by potting resin into the case.   The semiconductor device according to claim 1, wherein the circuit board is a heat transfer plate having an insulating layer formed on a back surface.   The semiconductor device according to claim 1, wherein the circuit board is an insulating board having a conductive layer formed on at least one surface of a ceramic base material.   The semiconductor device according to claim 1, wherein the semiconductor element is formed of a wide band gap semiconductor material.   The semiconductor device according to claim 10, wherein the wide band gap semiconductor material is any one of silicon carbide, a gallium nitride-based material, diamond, and a gallium oxide-based material.

Images