JP2015084497A - Switched capacitor circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid injection of extra noise during sample period by a simple configuration.SOLUTION: In an inverter INV10 creating an inverted sample clock signal SampleCK' for driving a MOS transistor M2 as a dummy capacitor, by inverting a sample clock signal SampleCK, the inverted sample clock signal SampleCK' is created so that the falling transition time of the inverted sample clock signal SampleCK' is longer than the rising transition time. When dampening the falling of the inverted sample clock signal SampleCK', feed-through noise is reduced by a highpass filter in the downstream.

Description

  The present invention relates to a switched capacitor circuit, and more particularly to a switched capacitor circuit designed to reduce feedthrough noise.

Conventionally, feed-through noise is a phenomenon that has been a problem as a source of noise and offset in switched capacitor circuits, and it is difficult to model parameters such as clock transition time, so it can be reproduced by simulation. Is also a difficult phenomenon.
FIG. 6 is an explanatory diagram for explaining the conventional switched capacitor circuit 1 and feedthrough.

  As shown in FIG. 6, in the switched capacitor circuit 1, an N-channel MOS transistor M1 is connected between an input terminal IN and an output terminal OUT, and one end of a capacitor Ch is connected to the source of the MOS transistor M1. The end is grounded. The clock signal CK is input to the gate of the MOS transistor M1. In FIG. 6, Vin is an input signal to the switched capacitor circuit 1, and Vout is an output signal of the switched capacitor circuit 1.

In such a switched capacitor circuit 1, as indicated by an arrow in FIG. 6, feedthrough noise ΔV appears in the input signal Vin and the output signal Vout due to slipping of the clock signal due to capacitive coupling between the gate and the source.
One countermeasure against this feedthrough is a method of providing a dummy capacitor (CAP), which is a capacitive component, in the switched capacitor circuit 1 shown in FIG. 6 as in the switched capacitor circuit 2 shown in FIG. (See Patent Document 1 and Patent Document 2).

In the switched capacitor circuit 2 shown in FIG. 7, the source and drain of an N-channel type MOS transistor M2 as a dummy capacitor are short-circuited and connected to the source of the MOS transistor M1, and the gate of the MOS transistor M1 is connected to the gate of the MOS transistor M1. The inverted clock signal CK ′ obtained by inverting the clock signal CK input to is input.
Inserting the MOS transistor M2 has the effect that the MOS transistor M2 absorbs the charge Δq1 injected by the feedthrough in the MOS transistor M1 immediately after the MOS transistor M1 is turned off (the charge Δq2 in FIG. 7). Noise can be canceled.

JP 59-117318 A JP-A-5-243944

  FIG. 8 shows a generally used switched capacitor circuit 3 including a clock circuit for generating an inverted signal of the clock signal. In the switched capacitor circuit 2 shown in FIG. Further, an inverter INV1 as a clock circuit is provided. FIG. 9 shows a timing chart of the sample clock signal SampleCK representing the sample timing of the input signal and the inverted sample clock signal SampleCK ′ which is an inverted signal thereof.

As shown in FIG. 8, the sample clock signal SampleCK is input to the gate of the MOS transistor M1 and input to the inverter INV1, and the output of the inverter INV1 is input to the gate of the MOS transistor M2 as the inverted sample clock signal SampleCK ′. .
Actually, an inverter is connected to the clock signal line for driving the MOS transistor M1 to generate an antiphase timing signal.

In FIG. 9, the point where the sample clock signal SampleCK falls (time point t3) is the timing at which the MOS transistor M1 is turned off. Immediately thereafter, the inverted sample clock signal SampleCK ′ rises (time t4) and cancels the feedthrough noise.
However, since the sample clock signal SampleCK rises at time t1 and sampling of the input signal Vin starts, the inverted sample clock signal SampleCK ′ falls at time t2, so that the MOS transistor M2 is turned on while the MOS transistor M1 is on. Will be turned off. That is, when the MOS transistor M2 is turned off, feedthrough in the MOS transistor M2 causes extra feedthrough noise to be injected into the input end IN side, the capacitor Ch side, and the output end OUT side during the sampling period. .

If noise enters the input terminal IN side, the capacitor Ch side, and the output terminal OUT side while the input signal Vin is being sampled in this way, it causes deterioration of the characteristics of the entire switched capacitor circuit.
As a method of avoiding this, there is a method of constructing a logic circuit in which the inverted sample clock signal SampleCK ′ falls before the sampling of the input signal Vin is started. An extra load is put in the path, which causes deterioration of characteristics of the entire circuit and an increase in power.

  The present invention has been made in view of such problems. The object of the present invention is to provide a simple configuration and extra feedthrough noise is injected into the input end side, the capacitor side, and the output side during the sample period. It is an object of the present invention to provide a switched capacitor circuit capable of avoiding this.

  One embodiment of the present invention is a switch having a first MOS transistor driven by a first clock signal (for example, the sample clock signal CK illustrated in FIG. 2) (for example, the MOS transistor M1 illustrated in FIG. 1); A capacitor (for example, capacitor Ch shown in FIG. 1) connected to the output terminal of the switch and a second clock signal (for example, inverted sample clock signal CK ′ shown in FIG. 2) obtained by inverting the first clock signal. A driven dummy capacitor (eg, MOS transistor M2 shown in FIG. 1), an inverter that inverts the first clock signal and generates the second clock signal (eg, inverter INV10 shown in FIG. 1), And the second clock signal has a falling transition time longer than the rising transition time. Switched-capacitor circuit that is.

Here, the dummy capacitor refers to a capacitance component such as a so-called feedthrough compensation MOS transistor.
The inverter includes a P-channel MOS transistor (for example, a P-channel MOS transistor M11 shown in FIG. 4) to which the first clock signal is input to the gate, and the P-channel MOS transistor to which the first clock signal is input to the gate. And an N-channel MOS transistor having a smaller transistor size than the MOS transistor (for example, an N-channel MOS transistor M12 shown in FIG. 4).

Here, the transistor size refers to the ratio W / L between the gate width W and the gate length L of the MOS transistor.
The inverter includes a P-channel MOS transistor (for example, a P-channel MOS transistor M21 shown in FIG. 5) to which the first clock signal is input to the gate, and an N-channel type to which the first clock signal is input to the gate. There may be provided a MOS transistor (for example, N-channel MOS transistor M22 shown in FIG. 5) and a resistance element (for example, resistor R10 shown in FIG. 5) connected to the output terminal of the N-channel MOS transistor. Good.

  The dummy capacitor may be a second MOS transistor (for example, MOS transistor M2 shown in FIG. 1).

  According to one embodiment of the present invention, it is possible to avoid injection of extra feedthrough noise on the input end side, the sampling capacitor side, and the output side during the sample period with a simple configuration.

It is a block diagram which shows an example of the switched capacitor circuit in this invention. It is an example of a sample clock signal and an inverted sample clock signal supplied to a switched capacitor circuit. It is an example of the equivalent circuit of a switched capacitor circuit. It is a specific example of an inverter included in a switched capacitor circuit. It is a specific example of an inverter included in a switched capacitor circuit. It is an example of the conventional switched capacitor circuit. It is an example of the conventional switched capacitor circuit. It is an example of the conventional switched capacitor circuit. It is an example of the conventional sample clock signal and inversion sample clock signal supplied to a switched capacitor circuit.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a circuit diagram showing an example of a switched capacitor circuit 10 including a clock circuit to which the present invention is applied.
The switched capacitor circuit 10 shown in FIG. 1 has the same configuration as the conventional switched capacitor circuit 3 shown in FIG. 8, but the output characteristics of the inverter INV10 are different.

  That is, the sampling capacitor Ch is connected to the source of the MOS transistor M1, and the source and drain of the MOS transistor M2 as a dummy capacitor are short-circuited and connected. The sample clock signal SampleCK is input to the gate of the MOS transistor M1, and the inverted sample clock signal SampleCK ′ obtained by inverting the sample clock signal SampleCK by the inverter INV10 is input to the gate of the MOS transistor M2. The MOS transistor M1 is, for example, an N channel type MOS transistor. The dummy capacitor is, for example, a MOS transistor M2 and is an N-channel type MOS transistor. The dummy capacitor may be, for example, a polycapacitor or an MIM capacitor whose electrodes are made of polysilicon. The MOS transistors M1 and M2 are either N-channel type or P-channel type if the MOS transistor M1 is turned on at the rising edge of the sample clock signal SampleCK and the MOS transistor M2 is turned off at the falling edge of the inverted sample clock signal SampleCK ′. It can be applied even if it exists. In FIG. 1, the case where both MOS transistors M1 and M2 are N-channel MOS transistors will be described.

FIG. 2 is a timing chart showing an example of the sample clock signal CK and the inverted sample clock signal CK ′.
As shown in FIG. 2, the inverted sample clock signal SampleCK ′ has the same rising characteristics as the conventional inverted sample clock signal SampleCK ′ shown in FIG. 9, but as shown at time t10, the inverted sample clock signal SampleCK ′. Only in the falling characteristic (for example, time t10), the falling transition time of the inverted sample clock signal SampleCK ′ is intentionally longer than the rising transition time. That is, the transition time of the fall of the inverted sample clock signal SampleCK ′ is set to a time at which feedthrough noise is sufficiently reduced by a high-pass filter described later.

  As described above, the path through which the feedthrough is injected passes from the gate of the MOS transistor M1 through the source thereof to the drain of the MOS transistor M2. Similarly, due to feedthrough in the MOS transistor M2, feedthrough noise is injected from the gate of the MOS transistor M2 through the source and drain thereof to the capacitor Ch side and the output terminal OUT side.

Here, as shown in the equivalent circuit of FIG. 3, the switched capacitor circuit 10 shown in FIG. 1 hangs from the capacitor C between the gate and the short-circuited source and drain of the MOS transistor M2 serving as a dummy capacitor, and the tip thereof. A high-pass filter is formed by the resistive impedance R.
At a sharp fall, the clock signal, that is, the inverted sample clock signal SampleCK ′ contains a large amount of high frequency components and is not attenuated even through a high-pass filter formed by the MOS transistor M2 and the resistive impedance R, but is shown in FIG. Thus, by dulling the fall of the inverted sample clock signal SampleCK ′ (for example, time t10), the high frequency component of the inverted sample clock signal SampleCK ′ is eliminated, and as a result, the noise component is attenuated by the high-pass filter. . That is, since the noise component is attenuated by slowing the falling edge of the inverted sample clock signal SampleCK ′, the feedthrough noise is reduced, and the feedthrough noise included in the output signal Vout is reduced. Become.

Example 1
FIG. 4 is a circuit diagram showing a specific example of inverter INV10 shown in FIG.
As shown in FIG. 4, the inverter INV10 in the first embodiment includes a CMOS inverter in which a P-channel MOS transistor M11 and an N-channel MOS transistor M12 are connected. At this time, the transistor size (W / L ratio of the gate width W to the gate length L) of the N-channel MOS transistor M12 is set to be intentionally smaller than usual. In other words, the transistor size of the N-channel MOS transistor M12 is determined so that the falling characteristic of the inverted sample clock signal SampleCK ′ becomes a characteristic that can sufficiently attenuate the feedthrough noise by the high-pass filter. The transistor size of the N-channel MOS transistor M12 is determined by experiments, for example.

In this way, by intentionally reducing the transistor size of the N-channel type MOS transistor M12, the fall of the inverted sample clock signal SampleCK ′ becomes dull. Therefore, high frequency components can be removed.
(Example 2)
FIG. 5 is a circuit diagram showing another example of the inverter INV10 shown in FIG.

As shown in FIG. 5, the inverter INV10 in the second embodiment includes a CMO inverter in which a P-channel MOS transistor M21 and an N-channel MOS transistor M22 are connected, and further includes a drain of the N-channel MOS transistor M22, that is, A resistor R10 is provided in the sink-side path.
In this way, by connecting the resistor R10 to the sink-side path, the fall of the inverted sample clock signal CK ′ becomes dull and the high frequency component can be removed.

  In the case of FIG. 5, one resistor R10 is added. The transistor size of the N-channel MOS transistor M21 may be the same as that of a normal CMOS inverter, and the N-channel MOS transistor shown in the first embodiment is used. Compared with the case where the transistor size of M11 is reduced, it is possible to suppress manufacturing variations in transistor characteristics that are increased by reducing the transistor size.

Note that the resistance value of the resistor R10 is determined by, for example, an experiment so that the falling characteristic of the inverted sample clock signal SampleCK ′ can be sufficiently attenuated by the high-pass filter. .
In this way, the fall of the inverted sample clock signal SampleCK ′ is blunted by adding the resistor R10. Therefore, high frequency components can be removed.

  It should be noted that the scope of the present invention is not limited to the illustrated and described exemplary embodiments, but includes all embodiments that provide the same effects as those intended by the present invention. Further, the scope of the invention can be defined by any desired combination of particular features among all the disclosed features.

10 Switched capacitor circuit M1 N-channel MOS transistor M2 N-channel MOS transistor (dummy capacitor)
M11, M21 P-channel MOS transistors M12, M22 N-channel MOS transistors INV1, INV10 Inverter Ch Capacitor R10 Resistance

Claims (4)

A switch having a first MOS transistor driven by a first clock signal;
A capacitor connected to the output terminal of the switch;
A dummy capacitor driven by a second clock signal obtained by inverting the first clock signal;
An inverter that inverts the first clock signal to generate the second clock signal,
The switched capacitor circuit, wherein the second clock signal has a falling transition time longer than a rising transition time. The inverter is
A P-channel MOS transistor to which the first clock signal is input to the gate;
An N-channel MOS transistor having the first clock signal input to a gate and a smaller transistor size than the P-channel MOS transistor;
The switched capacitor circuit according to claim 1, further comprising: The inverter is
A P-channel MOS transistor to which the first clock signal is input to the gate;
An N-channel MOS transistor to which the first clock signal is input to the gate;
A resistance element connected to the output terminal of the N-channel MOS transistor;
The switched capacitor circuit according to claim 1, further comprising:   The switched capacitor circuit according to any one of claims 1 to 3, wherein the dummy capacitor is a second MOS transistor.

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